[linux-block.git] / arch / sh / kernel / cf-enabler.c

/* $Id: cf-enabler.c,v 1.4 2004/02/22 22:44:36 kkojima Exp $
 *
 *  linux/drivers/block/cf-enabler.c
 *
 *  Copyright (C) 1999  Niibe Yutaka
 *  Copyright (C) 2000  Toshiharu Nozawa
 *  Copyright (C) 2001  A&D Co., Ltd.
 *
 *  Enable the CF configuration.
 */

#include <linux/init.h>
#include <linux/mm.h>
#include <linux/vmalloc.h>
#include <linux/interrupt.h>
#include <asm/io.h>
#include <asm/irq.h>

/*
 * You can connect Compact Flash directly to the bus of SuperH.
 * This is the enabler for that.
 *
 * SIM: How generic is this really? It looks pretty board, or at
 * least SH sub-type, specific to me.
 * I know it doesn't work on the Overdrive!
 */

/*
 * 0xB8000000 : Attribute
 * 0xB8001000 : Common Memory
 * 0xBA000000 : I/O
 */
#if defined(CONFIG_CPU_SH4)
/* SH4 can't access PCMCIA interface through P2 area.
 * we must remap it with appropriate attribute bit of the page set.
 * this part is based on Greg Banks' hd64465_ss.c implementation - Masahiro Abe */

#if defined(CONFIG_CF_AREA6)
#define slot_no 0
#else
#define slot_no 1
#endif

/* use this pointer to access to directly connected compact flash io area*/
void *cf_io_base;

static int __init allocate_cf_area(void)
{
	pgprot_t prot;
	unsigned long paddrbase, psize;

	/* open I/O area window */
	paddrbase = virt_to_phys((void*)CONFIG_CF_BASE_ADDR);
	psize = PAGE_SIZE;
	prot = PAGE_KERNEL_PCC(slot_no, _PAGE_PCC_IO16);
	cf_io_base = p3_ioremap(paddrbase, psize, prot.pgprot);
	if (!cf_io_base) {
		printk("allocate_cf_area : can't open CF I/O window!\n");
		return -ENOMEM;
	}
/*	printk("p3_ioremap(paddr=0x%08lx, psize=0x%08lx, prot=0x%08lx)=0x%08lx\n",
		paddrbase, psize, prot.pgprot, cf_io_base);*/

	/* XXX : do we need attribute and common-memory area also? */

	return 0;
}
#endif

static int __init cf_init_default(void)
{
/* You must have enabled the card, and set the level interrupt
 * before reaching this point. Possibly in boot ROM or boot loader.
 */
#if defined(CONFIG_CPU_SH4)
	allocate_cf_area();
#endif

	return 0;
}

#if defined(CONFIG_SH_SOLUTION_ENGINE)
#include <asm/se.h>
#elif defined(CONFIG_SH_7722_SOLUTION_ENGINE)
#include <asm/se7722.h>
#endif

/*
 * SolutionEngine Seriese
 *
 * about MS770xSE
 * 0xB8400000 : Common Memory
 * 0xB8500000 : Attribute
 * 0xB8600000 : I/O
 *
 * about MS7722SE
 * 0xB0400000 : Common Memory
 * 0xB0500000 : Attribute
 * 0xB0600000 : I/O
 */

#if defined(CONFIG_SH_SOLUTION_ENGINE) || defined(CONFIG_SH_7722_SOLUTION_ENGINE) 
static int __init cf_init_se(void)
{
	if ((ctrl_inw(MRSHPC_CSR) & 0x000c) != 0)
		return 0;	/* Not detected */

	if ((ctrl_inw(MRSHPC_CSR) & 0x0080) == 0) {
		ctrl_outw(0x0674, MRSHPC_CPWCR); /* Card Vcc is 3.3v? */
	} else {
		ctrl_outw(0x0678, MRSHPC_CPWCR); /* Card Vcc is 5V */
	}

	/*
	 *  PC-Card window open 
	 *  flag == COMMON/ATTRIBUTE/IO
	 */
	/* common window open */
	ctrl_outw(0x8a84, MRSHPC_MW0CR1);
	if((ctrl_inw(MRSHPC_CSR) & 0x4000) != 0)
		/* common mode & bus width 16bit SWAP = 1*/
		ctrl_outw(0x0b00, MRSHPC_MW0CR2);
	else
		/* common mode & bus width 16bit SWAP = 0*/
		ctrl_outw(0x0300, MRSHPC_MW0CR2); 

	/* attribute window open */
	ctrl_outw(0x8a85, MRSHPC_MW1CR1);
	if ((ctrl_inw(MRSHPC_CSR) & 0x4000) != 0)
		/* attribute mode & bus width 16bit SWAP = 1*/
		ctrl_outw(0x0a00, MRSHPC_MW1CR2);
	else
		/* attribute mode & bus width 16bit SWAP = 0*/
		ctrl_outw(0x0200, MRSHPC_MW1CR2);

	/* I/O window open */
	ctrl_outw(0x8a86, MRSHPC_IOWCR1);
	ctrl_outw(0x0008, MRSHPC_CDCR);	 /* I/O card mode */
	if ((ctrl_inw(MRSHPC_CSR) & 0x4000) != 0)
		ctrl_outw(0x0a00, MRSHPC_IOWCR2); /* bus width 16bit SWAP = 1*/
	else
		ctrl_outw(0x0200, MRSHPC_IOWCR2); /* bus width 16bit SWAP = 0*/

	ctrl_outw(0x2000, MRSHPC_ICR);
	ctrl_outb(0x00, PA_MRSHPC_MW2 + 0x206);
	ctrl_outb(0x42, PA_MRSHPC_MW2 + 0x200);
	return 0;
}
#else
static int __init cf_init_se(void)
{
	return -1;
}
#endif

int __init cf_init(void)
{
	if( mach_is_se() || mach_is_7722se() ){
		return cf_init_se();
	}
	
	return cf_init_default();
}

__initcall (cf_init);
Commit	Line	Data
1da177e4 LT	1	/* $Id: cf-enabler.c,v 1.4 2004/02/22 22:44:36 kkojima Exp $
	2	*
	3	* linux/drivers/block/cf-enabler.c
	4	*
	5	* Copyright (C) 1999 Niibe Yutaka
	6	* Copyright (C) 2000 Toshiharu Nozawa
	7	* Copyright (C) 2001 A&D Co., Ltd.
	8	*
	9	* Enable the CF configuration.
	10	*/
	11
1da177e4	12	#include <linux/init.h>
373e68b5 PM	13	#include <linux/mm.h>
373e68b5 PM	14	#include <linux/vmalloc.h>
66c5227e	15	#include <linux/interrupt.h>
1da177e4 LT	16	#include <asm/io.h>
	17	#include <asm/irq.h>
	18
	19	/*
	20	* You can connect Compact Flash directly to the bus of SuperH.
	21	* This is the enabler for that.
	22	*
	23	* SIM: How generic is this really? It looks pretty board, or at
	24	* least SH sub-type, specific to me.
	25	* I know it doesn't work on the Overdrive!
	26	*/
	27
	28	/*
	29	* 0xB8000000 : Attribute
	30	* 0xB8001000 : Common Memory
	31	* 0xBA000000 : I/O
	32	*/
6865f0ea	33	#if defined(CONFIG_CPU_SH4)
1da177e4	34	/* SH4 can't access PCMCIA interface through P2 area.
e868d612	35	* we must remap it with appropriate attribute bit of the page set.
1da177e4	36	* this part is based on Greg Banks' hd64465_ss.c implementation - Masahiro Abe */
1da177e4 LT	37
	38	#if defined(CONFIG_CF_AREA6)
	39	#define slot_no 0
	40	#else
	41	#define slot_no 1
	42	#endif
	43
1da177e4 LT	44	/* use this pointer to access to directly connected compact flash io area*/
	45	void *cf_io_base;
	46
	47	static int __init allocate_cf_area(void)
	48	{
	49	pgprot_t prot;
	50	unsigned long paddrbase, psize;
	51
	52	/* open I/O area window */
	53	paddrbase = virt_to_phys((void*)CONFIG_CF_BASE_ADDR);
	54	psize = PAGE_SIZE;
	55	prot = PAGE_KERNEL_PCC(slot_no, _PAGE_PCC_IO16);
	56	cf_io_base = p3_ioremap(paddrbase, psize, prot.pgprot);
	57	if (!cf_io_base) {
	58	printk("allocate_cf_area : can't open CF I/O window!\n");
	59	return -ENOMEM;
	60	}
	61	/* printk("p3_ioremap(paddr=0x%08lx, psize=0x%08lx, prot=0x%08lx)=0x%08lx\n",
d7cdc9e8	62	paddrbase, psize, prot.pgprot, cf_io_base);*/
1da177e4 LT	63
	64	/* XXX : do we need attribute and common-memory area also? */
	65
	66	return 0;
	67	}
	68	#endif
	69
	70	static int __init cf_init_default(void)
	71	{
	72	/* You must have enabled the card, and set the level interrupt
	73	* before reaching this point. Possibly in boot ROM or boot loader.
	74	*/
6865f0ea	75	#if defined(CONFIG_CPU_SH4)
1da177e4 LT	76	allocate_cf_area();
1da177e4 LT	77	#endif
fd8f20e8	78
1da177e4 LT	79	return 0;
	80	}
	81
	82	#if defined(CONFIG_SH_SOLUTION_ENGINE)
373e68b5	83	#include <asm/se.h>
6865f0ea RS	84	#elif defined(CONFIG_SH_7722_SOLUTION_ENGINE)
	85	#include <asm/se7722.h>
	86	#endif
1da177e4 LT	87
1da177e4 LT	88	/*
6865f0ea	89	* SolutionEngine Seriese
1da177e4	90	*
6865f0ea	91	* about MS770xSE
1da177e4 LT	92	* 0xB8400000 : Common Memory
	93	* 0xB8500000 : Attribute
	94	* 0xB8600000 : I/O
6865f0ea RS	95	*
	96	* about MS7722SE
	97	* 0xB0400000 : Common Memory
	98	* 0xB0500000 : Attribute
	99	* 0xB0600000 : I/O
1da177e4 LT	100	*/
1da177e4 LT	101
6865f0ea	102	#if defined(CONFIG_SH_SOLUTION_ENGINE) \|\| defined(CONFIG_SH_7722_SOLUTION_ENGINE)
1da177e4 LT	103	static int __init cf_init_se(void)
	104	{
	105	if ((ctrl_inw(MRSHPC_CSR) & 0x000c) != 0)
	106	return 0; /* Not detected */
	107
	108	if ((ctrl_inw(MRSHPC_CSR) & 0x0080) == 0) {
	109	ctrl_outw(0x0674, MRSHPC_CPWCR); /* Card Vcc is 3.3v? */
	110	} else {
	111	ctrl_outw(0x0678, MRSHPC_CPWCR); /* Card Vcc is 5V */
	112	}
	113
	114	/*
	115	* PC-Card window open
	116	* flag == COMMON/ATTRIBUTE/IO
	117	*/
	118	/* common window open */
6865f0ea	119	ctrl_outw(0x8a84, MRSHPC_MW0CR1);
1da177e4 LT	120	if((ctrl_inw(MRSHPC_CSR) & 0x4000) != 0)
	121	/* common mode & bus width 16bit SWAP = 1*/
	122	ctrl_outw(0x0b00, MRSHPC_MW0CR2);
	123	else
	124	/* common mode & bus width 16bit SWAP = 0*/
	125	ctrl_outw(0x0300, MRSHPC_MW0CR2);
	126
	127	/* attribute window open */
6865f0ea	128	ctrl_outw(0x8a85, MRSHPC_MW1CR1);
1da177e4 LT	129	if ((ctrl_inw(MRSHPC_CSR) & 0x4000) != 0)
	130	/* attribute mode & bus width 16bit SWAP = 1*/
	131	ctrl_outw(0x0a00, MRSHPC_MW1CR2);
	132	else
	133	/* attribute mode & bus width 16bit SWAP = 0*/
	134	ctrl_outw(0x0200, MRSHPC_MW1CR2);
	135
	136	/* I/O window open */
6865f0ea	137	ctrl_outw(0x8a86, MRSHPC_IOWCR1);
1da177e4 LT	138	ctrl_outw(0x0008, MRSHPC_CDCR); /* I/O card mode */
	139	if ((ctrl_inw(MRSHPC_CSR) & 0x4000) != 0)
	140	ctrl_outw(0x0a00, MRSHPC_IOWCR2); /* bus width 16bit SWAP = 1*/
	141	else
	142	ctrl_outw(0x0200, MRSHPC_IOWCR2); /* bus width 16bit SWAP = 0*/
	143
	144	ctrl_outw(0x2000, MRSHPC_ICR);
	145	ctrl_outb(0x00, PA_MRSHPC_MW2 + 0x206);
	146	ctrl_outb(0x42, PA_MRSHPC_MW2 + 0x200);
	147	return 0;
	148	}
66c5227e EP	149	#else
	150	static int __init cf_init_se(void)
	151	{
	152	return -1;
	153	}
1da177e4 LT	154	#endif
	155
	156	int __init cf_init(void)
	157	{
6865f0ea	158	if( mach_is_se() \|\| mach_is_7722se() ){
1da177e4	159	return cf_init_se();
6865f0ea RS	160	}
6865f0ea RS	161
1da177e4 LT	162	return cf_init_default();
	163	}
	164
	165	__initcall (cf_init);