[linux-2.6-block.git] / arch / sh / include / cpu-sh4 / cpu / cache.h

/*
 * include/asm-sh/cpu-sh4/cache.h
 *
 * Copyright (C) 1999 Niibe Yutaka
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 */
#ifndef __ASM_CPU_SH4_CACHE_H
#define __ASM_CPU_SH4_CACHE_H

#define L1_CACHE_SHIFT	5

#define SH_CACHE_VALID		1
#define SH_CACHE_UPDATED	2
#define SH_CACHE_COMBINED	4
#define SH_CACHE_ASSOC		8

#define SH_CCR		0xff00001c	/* Address of Cache Control Register */
#define CCR_CACHE_OCE	0x0001	/* Operand Cache Enable */
#define CCR_CACHE_WT	0x0002	/* Write-Through (for P0,U0,P3) (else writeback)*/
#define CCR_CACHE_CB	0x0004	/* Copy-Back (for P1) (else writethrough) */
#define CCR_CACHE_OCI	0x0008	/* OC Invalidate */
#define CCR_CACHE_ORA	0x0020	/* OC RAM Mode */
#define CCR_CACHE_OIX	0x0080	/* OC Index Enable */
#define CCR_CACHE_ICE	0x0100	/* Instruction Cache Enable */
#define CCR_CACHE_ICI	0x0800	/* IC Invalidate */
#define CCR_CACHE_IIX	0x8000	/* IC Index Enable */
#ifndef CONFIG_CPU_SH4A
#define CCR_CACHE_EMODE	0x80000000	/* EMODE Enable */
#endif

/* Default CCR setup: 8k+16k-byte cache,P1-wb,enable */
#define CCR_CACHE_ENABLE	(CCR_CACHE_OCE|CCR_CACHE_ICE)
#define CCR_CACHE_INVALIDATE	(CCR_CACHE_OCI|CCR_CACHE_ICI)

#define CACHE_IC_ADDRESS_ARRAY	0xf0000000
#define CACHE_OC_ADDRESS_ARRAY	0xf4000000

#define RAMCR			0xFF000074

#endif /* __ASM_CPU_SH4_CACHE_H */
Commit	Line	Data
1da177e4 LT	1	/*
	2	* include/asm-sh/cpu-sh4/cache.h
	3	*
	4	* Copyright (C) 1999 Niibe Yutaka
	5	*
	6	* This file is subject to the terms and conditions of the GNU General Public
	7	* License. See the file "COPYING" in the main directory of this archive
	8	* for more details.
	9	*/
	10	#ifndef __ASM_CPU_SH4_CACHE_H
	11	#define __ASM_CPU_SH4_CACHE_H
	12
	13	#define L1_CACHE_SHIFT 5
	14
8d5fb297 PM	15	#define SH_CACHE_VALID 1
	16	#define SH_CACHE_UPDATED 2
	17	#define SH_CACHE_COMBINED 4
	18	#define SH_CACHE_ASSOC 8
	19
a5f6ea29	20	#define SH_CCR 0xff00001c /* Address of Cache Control Register */
1da177e4 LT	21	#define CCR_CACHE_OCE 0x0001 /* Operand Cache Enable */
	22	#define CCR_CACHE_WT 0x0002 /* Write-Through (for P0,U0,P3) (else writeback)*/
	23	#define CCR_CACHE_CB 0x0004 /* Copy-Back (for P1) (else writethrough) */
	24	#define CCR_CACHE_OCI 0x0008 /* OC Invalidate */
	25	#define CCR_CACHE_ORA 0x0020 /* OC RAM Mode */
	26	#define CCR_CACHE_OIX 0x0080 /* OC Index Enable */
	27	#define CCR_CACHE_ICE 0x0100 /* Instruction Cache Enable */
	28	#define CCR_CACHE_ICI 0x0800 /* IC Invalidate */
	29	#define CCR_CACHE_IIX 0x8000 /* IC Index Enable */
41504c39	30	#ifndef CONFIG_CPU_SH4A
1da177e4	31	#define CCR_CACHE_EMODE 0x80000000 /* EMODE Enable */
5b19c908	32	#endif
1da177e4 LT	33
	34	/* Default CCR setup: 8k+16k-byte cache,P1-wb,enable */
	35	#define CCR_CACHE_ENABLE (CCR_CACHE_OCE\|CCR_CACHE_ICE)
	36	#define CCR_CACHE_INVALIDATE (CCR_CACHE_OCI\|CCR_CACHE_ICI)
	37
	38	#define CACHE_IC_ADDRESS_ARRAY 0xf0000000
	39	#define CACHE_OC_ADDRESS_ARRAY 0xf4000000
	40
d974ac24 KM	41	#define RAMCR 0xFF000074
d974ac24 KM	42
1da177e4 LT	43	#endif /* __ASM_CPU_SH4_CACHE_H */
1da177e4 LT	44