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af3c7dfe PM |
1 | /* |
2 | * include/asm-sh/processor.h | |
3 | * | |
4 | * Copyright (C) 1999, 2000 Niibe Yutaka | |
5 | * Copyright (C) 2002, 2003 Paul Mundt | |
6 | */ | |
7 | ||
8 | #ifndef __ASM_SH_PROCESSOR_32_H | |
9 | #define __ASM_SH_PROCESSOR_32_H | |
10 | #ifdef __KERNEL__ | |
11 | ||
12 | #include <linux/compiler.h> | |
fa43972f | 13 | #include <linux/linkage.h> |
af3c7dfe PM |
14 | #include <asm/page.h> |
15 | #include <asm/types.h> | |
4352fc1b | 16 | #include <asm/hw_breakpoint.h> |
af3c7dfe PM |
17 | |
18 | /* | |
19 | * Default implementation of macro that returns current | |
20 | * instruction pointer ("program counter"). | |
21 | */ | |
103340cc | 22 | #define current_text_addr() ({ void *pc; __asm__("mova 1f, %0\n.align 2\n1:":"=z" (pc)); pc; }) |
af3c7dfe PM |
23 | |
24 | /* Core Processor Version Register */ | |
25 | #define CCN_PVR 0xff000030 | |
26 | #define CCN_CVR 0xff000040 | |
27 | #define CCN_PRR 0xff000044 | |
28 | ||
af3c7dfe PM |
29 | /* |
30 | * User space process size: 2GB. | |
31 | * | |
32 | * Since SH7709 and SH7750 have "area 7", we can't use 0x7c000000--0x7fffffff | |
33 | */ | |
34 | #define TASK_SIZE 0x7c000000UL | |
35 | ||
922a70d3 DH |
36 | #define STACK_TOP TASK_SIZE |
37 | #define STACK_TOP_MAX STACK_TOP | |
38 | ||
af3c7dfe PM |
39 | /* This decides where the kernel will search for a free chunk of vm |
40 | * space during mmap's. | |
41 | */ | |
30c254ff | 42 | #define TASK_UNMAPPED_BASE PAGE_ALIGN(TASK_SIZE / 3) |
af3c7dfe PM |
43 | |
44 | /* | |
45 | * Bit of SR register | |
46 | * | |
47 | * FD-bit: | |
48 | * When it's set, it means the processor doesn't have right to use FPU, | |
49 | * and it results exception when the floating operation is executed. | |
50 | * | |
51 | * IMASK-bit: | |
52 | * Interrupt level mask | |
53 | */ | |
af3c7dfe PM |
54 | #define SR_DSP 0x00001000 |
55 | #define SR_IMASK 0x000000f0 | |
9bbafce2 | 56 | #define SR_FD 0x00008000 |
d3ea9fa0 | 57 | #define SR_MD 0x40000000 |
af3c7dfe | 58 | |
01ab1039 MT |
59 | /* |
60 | * DSP structure and data | |
61 | */ | |
62 | struct sh_dsp_struct { | |
63 | unsigned long dsp_regs[14]; | |
64 | long status; | |
65 | }; | |
66 | ||
af3c7dfe PM |
67 | /* |
68 | * FPU structure and data | |
69 | */ | |
70 | ||
71 | struct sh_fpu_hard_struct { | |
72 | unsigned long fp_regs[16]; | |
73 | unsigned long xfp_regs[16]; | |
74 | unsigned long fpscr; | |
75 | unsigned long fpul; | |
76 | ||
77 | long status; /* software status information */ | |
78 | }; | |
79 | ||
80 | /* Dummy fpu emulator */ | |
81 | struct sh_fpu_soft_struct { | |
82 | unsigned long fp_regs[16]; | |
83 | unsigned long xfp_regs[16]; | |
84 | unsigned long fpscr; | |
85 | unsigned long fpul; | |
86 | ||
87 | unsigned char lookahead; | |
88 | unsigned long entry_pc; | |
89 | }; | |
90 | ||
0ea820cf PM |
91 | union thread_xstate { |
92 | struct sh_fpu_hard_struct hardfpu; | |
93 | struct sh_fpu_soft_struct softfpu; | |
af3c7dfe PM |
94 | }; |
95 | ||
96 | struct thread_struct { | |
97 | /* Saved registers when thread is descheduled */ | |
98 | unsigned long sp; | |
99 | unsigned long pc; | |
100 | ||
94ea5e44 PM |
101 | /* Various thread flags, see SH_THREAD_xxx */ |
102 | unsigned long flags; | |
103 | ||
09a07294 | 104 | /* Save middle states of ptrace breakpoints */ |
94ea5e44 | 105 | struct perf_event *ptrace_bps[HBP_NUM]; |
01ab1039 MT |
106 | |
107 | #ifdef CONFIG_SH_DSP | |
108 | /* Dsp status information */ | |
109 | struct sh_dsp_struct dsp_status; | |
110 | #endif | |
af3c7dfe | 111 | |
0ea820cf PM |
112 | /* Extended processor state */ |
113 | union thread_xstate *xstate; | |
af3c7dfe | 114 | }; |
af3c7dfe PM |
115 | |
116 | #define INIT_THREAD { \ | |
117 | .sp = sizeof(init_stack) + (long) &init_stack, \ | |
94ea5e44 | 118 | .flags = 0, \ |
af3c7dfe PM |
119 | } |
120 | ||
af3c7dfe PM |
121 | /* Forward declaration, a strange C thing */ |
122 | struct task_struct; | |
70e068ee PM |
123 | |
124 | extern void start_thread(struct pt_regs *regs, unsigned long new_pc, unsigned long new_sp); | |
af3c7dfe PM |
125 | |
126 | /* Free all resources held by a thread. */ | |
127 | extern void release_thread(struct task_struct *); | |
128 | ||
af3c7dfe PM |
129 | /* Copy and release all segment info associated with a VM */ |
130 | #define copy_segments(p, mm) do { } while(0) | |
131 | #define release_segments(mm) do { } while(0) | |
132 | ||
133 | /* | |
134 | * FPU lazy state save handling. | |
135 | */ | |
136 | ||
137 | static __inline__ void disable_fpu(void) | |
138 | { | |
139 | unsigned long __dummy; | |
140 | ||
141 | /* Set FD flag in SR */ | |
142 | __asm__ __volatile__("stc sr, %0\n\t" | |
143 | "or %1, %0\n\t" | |
144 | "ldc %0, sr" | |
145 | : "=&r" (__dummy) | |
146 | : "r" (SR_FD)); | |
147 | } | |
148 | ||
149 | static __inline__ void enable_fpu(void) | |
150 | { | |
151 | unsigned long __dummy; | |
152 | ||
153 | /* Clear out FD flag in SR */ | |
154 | __asm__ __volatile__("stc sr, %0\n\t" | |
155 | "and %1, %0\n\t" | |
156 | "ldc %0, sr" | |
157 | : "=&r" (__dummy) | |
158 | : "r" (~SR_FD)); | |
159 | } | |
160 | ||
af3c7dfe PM |
161 | /* Double presision, NANS as NANS, rounding to nearest, no exceptions */ |
162 | #define FPSCR_INIT 0x00080000 | |
163 | ||
164 | #define FPSCR_CAUSE_MASK 0x0001f000 /* Cause bits */ | |
165 | #define FPSCR_FLAG_MASK 0x0000007c /* Flag bits */ | |
166 | ||
167 | /* | |
168 | * Return saved PC of a blocked thread. | |
169 | */ | |
170 | #define thread_saved_pc(tsk) (tsk->thread.pc) | |
171 | ||
172 | void show_trace(struct task_struct *tsk, unsigned long *sp, | |
173 | struct pt_regs *regs); | |
5d2685d0 PM |
174 | |
175 | #ifdef CONFIG_DUMP_CODE | |
9cfc9a9b | 176 | void show_code(struct pt_regs *regs); |
5d2685d0 PM |
177 | #else |
178 | static inline void show_code(struct pt_regs *regs) | |
179 | { | |
180 | } | |
181 | #endif | |
182 | ||
af3c7dfe PM |
183 | extern unsigned long get_wchan(struct task_struct *p); |
184 | ||
185 | #define KSTK_EIP(tsk) (task_pt_regs(tsk)->pc) | |
186 | #define KSTK_ESP(tsk) (task_pt_regs(tsk)->regs[15]) | |
187 | ||
a73090ff | 188 | #if defined(CONFIG_CPU_SH2A) || defined(CONFIG_CPU_SH4) |
c81fc389 | 189 | |
af3c7dfe PM |
190 | #define PREFETCH_STRIDE L1_CACHE_BYTES |
191 | #define ARCH_HAS_PREFETCH | |
192 | #define ARCH_HAS_PREFETCHW | |
c81fc389 PM |
193 | |
194 | static inline void prefetch(const void *x) | |
af3c7dfe | 195 | { |
d53e4307 | 196 | __builtin_prefetch(x, 0, 3); |
af3c7dfe PM |
197 | } |
198 | ||
c81fc389 | 199 | static inline void prefetchw(const void *x) |
d53e4307 GC |
200 | { |
201 | __builtin_prefetch(x, 1, 3); | |
202 | } | |
af3c7dfe PM |
203 | #endif |
204 | ||
af3c7dfe PM |
205 | #endif /* __KERNEL__ */ |
206 | #endif /* __ASM_SH_PROCESSOR_32_H */ |