Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | #ifndef __ASM_SH_IO_H |
2 | #define __ASM_SH_IO_H | |
1da177e4 LT |
3 | /* |
4 | * Convention: | |
14866543 | 5 | * read{b,w,l,q}/write{b,w,l,q} are for PCI, |
1da177e4 | 6 | * while in{b,w,l}/out{b,w,l} are for ISA |
14866543 | 7 | * |
1da177e4 LT |
8 | * In addition we have 'pausing' versions: in{b,w,l}_p/out{b,w,l}_p |
9 | * and 'string' versions: ins{b,w,l}/outs{b,w,l} | |
1da177e4 | 10 | * |
14866543 PM |
11 | * While read{b,w,l,q} and write{b,w,l,q} contain memory barriers |
12 | * automatically, there are also __raw versions, which do not. | |
13 | * | |
14 | * Historically, we have also had ctrl_in{b,w,l,q}/ctrl_out{b,w,l,q} for | |
15 | * SuperH specific I/O (raw I/O to on-chip CPU peripherals). In practice | |
16 | * these have the same semantics as the __raw variants, and as such, all | |
17 | * new code should be using the __raw versions. | |
18 | * | |
19 | * All ISA I/O routines are wrapped through the machine vector. If a | |
20 | * board does not provide overrides, a generic set that are copied in | |
21 | * from the default machine vector are used instead. These are largely | |
22 | * for old compat code for I/O offseting to SuperIOs, all of which are | |
23 | * better handled through the machvec ioport mapping routines these days. | |
1da177e4 | 24 | */ |
4f744aff | 25 | #include <linux/errno.h> |
1da177e4 LT |
26 | #include <asm/cache.h> |
27 | #include <asm/system.h> | |
28 | #include <asm/addrspace.h> | |
29 | #include <asm/machvec.h> | |
b66c1a39 PM |
30 | #include <asm/pgtable.h> |
31 | #include <asm-generic/iomap.h> | |
32 | ||
33 | #ifdef __KERNEL__ | |
1da177e4 LT |
34 | /* |
35 | * Depending on which platform we are running on, we need different | |
36 | * I/O functions. | |
37 | */ | |
b66c1a39 PM |
38 | #define __IO_PREFIX generic |
39 | #include <asm/io_generic.h> | |
e7cc9a73 | 40 | #include <asm/io_trapped.h> |
b66c1a39 | 41 | |
14866543 PM |
42 | #define inb(p) sh_mv.mv_inb((p)) |
43 | #define inw(p) sh_mv.mv_inw((p)) | |
44 | #define inl(p) sh_mv.mv_inl((p)) | |
45 | #define outb(x,p) sh_mv.mv_outb((x),(p)) | |
46 | #define outw(x,p) sh_mv.mv_outw((x),(p)) | |
47 | #define outl(x,p) sh_mv.mv_outl((x),(p)) | |
48 | ||
49 | #define inb_p(p) sh_mv.mv_inb_p((p)) | |
50 | #define inw_p(p) sh_mv.mv_inw_p((p)) | |
51 | #define inl_p(p) sh_mv.mv_inl_p((p)) | |
52 | #define outb_p(x,p) sh_mv.mv_outb_p((x),(p)) | |
53 | #define outw_p(x,p) sh_mv.mv_outw_p((x),(p)) | |
54 | #define outl_p(x,p) sh_mv.mv_outl_p((x),(p)) | |
55 | ||
56 | #define insb(p,b,c) sh_mv.mv_insb((p), (b), (c)) | |
57 | #define insw(p,b,c) sh_mv.mv_insw((p), (b), (c)) | |
58 | #define insl(p,b,c) sh_mv.mv_insl((p), (b), (c)) | |
59 | #define outsb(p,b,c) sh_mv.mv_outsb((p), (b), (c)) | |
60 | #define outsw(p,b,c) sh_mv.mv_outsw((p), (b), (c)) | |
61 | #define outsl(p,b,c) sh_mv.mv_outsl((p), (b), (c)) | |
62 | ||
63 | #define __raw_writeb(v,a) (__chk_io_ptr(a), *(volatile u8 __force *)(a) = (v)) | |
64 | #define __raw_writew(v,a) (__chk_io_ptr(a), *(volatile u16 __force *)(a) = (v)) | |
65 | #define __raw_writel(v,a) (__chk_io_ptr(a), *(volatile u32 __force *)(a) = (v)) | |
66 | #define __raw_writeq(v,a) (__chk_io_ptr(a), *(volatile u64 __force *)(a) = (v)) | |
67 | ||
68 | #define __raw_readb(a) (__chk_io_ptr(a), *(volatile u8 __force *)(a)) | |
69 | #define __raw_readw(a) (__chk_io_ptr(a), *(volatile u16 __force *)(a)) | |
70 | #define __raw_readl(a) (__chk_io_ptr(a), *(volatile u32 __force *)(a)) | |
71 | #define __raw_readq(a) (__chk_io_ptr(a), *(volatile u64 __force *)(a)) | |
72 | ||
73 | #define readb(a) ({ u8 r_ = __raw_readb(a); mb(); r_; }) | |
74 | #define readw(a) ({ u16 r_ = __raw_readw(a); mb(); r_; }) | |
75 | #define readl(a) ({ u32 r_ = __raw_readl(a); mb(); r_; }) | |
76 | #define readq(a) ({ u64 r_ = __raw_readq(a); mb(); r_; }) | |
77 | ||
78 | #define writeb(v,a) ({ __raw_writeb((v),(a)); mb(); }) | |
79 | #define writew(v,a) ({ __raw_writew((v),(a)); mb(); }) | |
80 | #define writel(v,a) ({ __raw_writel((v),(a)); mb(); }) | |
81 | #define writeq(v,a) ({ __raw_writeq((v),(a)); mb(); }) | |
1da177e4 | 82 | |
14866543 PM |
83 | /* SuperH on-chip I/O functions */ |
84 | #define ctrl_inb __raw_readb | |
85 | #define ctrl_inw __raw_readw | |
86 | #define ctrl_inl __raw_readl | |
87 | #define ctrl_inq __raw_readq | |
05ae9158 | 88 | |
14866543 PM |
89 | #define ctrl_outb __raw_writeb |
90 | #define ctrl_outw __raw_writew | |
91 | #define ctrl_outl __raw_writel | |
92 | #define ctrl_outq __raw_writeq | |
64c9627c | 93 | |
e9c58fc5 PM |
94 | extern unsigned long generic_io_base; |
95 | ||
14866543 PM |
96 | static inline void ctrl_delay(void) |
97 | { | |
e9c58fc5 | 98 | __raw_readw(generic_io_base); |
14866543 | 99 | } |
1da177e4 | 100 | |
da6b003a MD |
101 | #define __BUILD_MEMORY_STRING(bwlq, type) \ |
102 | \ | |
64c9627c | 103 | static inline void __raw_writes##bwlq(volatile void __iomem *mem, \ |
da6b003a MD |
104 | const void *addr, unsigned int count) \ |
105 | { \ | |
106 | const volatile type *__addr = addr; \ | |
107 | \ | |
108 | while (count--) { \ | |
109 | __raw_write##bwlq(*__addr, mem); \ | |
110 | __addr++; \ | |
111 | } \ | |
112 | } \ | |
113 | \ | |
64c9627c PM |
114 | static inline void __raw_reads##bwlq(volatile void __iomem *mem, \ |
115 | void *addr, unsigned int count) \ | |
da6b003a MD |
116 | { \ |
117 | volatile type *__addr = addr; \ | |
118 | \ | |
119 | while (count--) { \ | |
120 | *__addr = __raw_read##bwlq(mem); \ | |
121 | __addr++; \ | |
122 | } \ | |
123 | } | |
124 | ||
125 | __BUILD_MEMORY_STRING(b, u8) | |
126 | __BUILD_MEMORY_STRING(w, u16) | |
14866543 | 127 | |
6dbe47a1 | 128 | #ifdef CONFIG_SUPERH32 |
14866543 PM |
129 | void __raw_writesl(void __iomem *addr, const void *data, int longlen); |
130 | void __raw_readsl(const void __iomem *addr, void *data, int longlen); | |
6dbe47a1 PM |
131 | #else |
132 | __BUILD_MEMORY_STRING(l, u32) | |
133 | #endif | |
134 | ||
135 | __BUILD_MEMORY_STRING(q, u64) | |
64c9627c | 136 | |
14866543 PM |
137 | #define writesb __raw_writesb |
138 | #define writesw __raw_writesw | |
139 | #define writesl __raw_writesl | |
64c9627c | 140 | |
14866543 PM |
141 | #define readsb __raw_readsb |
142 | #define readsw __raw_readsw | |
143 | #define readsl __raw_readsl | |
05ae9158 | 144 | |
14866543 PM |
145 | #define readb_relaxed(a) readb(a) |
146 | #define readw_relaxed(a) readw(a) | |
147 | #define readl_relaxed(a) readl(a) | |
148 | #define readq_relaxed(a) readq(a) | |
1da177e4 | 149 | |
15444a89 | 150 | #ifndef CONFIG_GENERIC_IOMAP |
b66c1a39 | 151 | /* Simple MMIO */ |
64c9627c PM |
152 | #define ioread8(a) __raw_readb(a) |
153 | #define ioread16(a) __raw_readw(a) | |
b66c1a39 | 154 | #define ioread16be(a) be16_to_cpu(__raw_readw((a))) |
64c9627c | 155 | #define ioread32(a) __raw_readl(a) |
b66c1a39 | 156 | #define ioread32be(a) be32_to_cpu(__raw_readl((a))) |
1da177e4 | 157 | |
64c9627c PM |
158 | #define iowrite8(v,a) __raw_writeb((v),(a)) |
159 | #define iowrite16(v,a) __raw_writew((v),(a)) | |
b66c1a39 | 160 | #define iowrite16be(v,a) __raw_writew(cpu_to_be16((v)),(a)) |
64c9627c | 161 | #define iowrite32(v,a) __raw_writel((v),(a)) |
b66c1a39 PM |
162 | #define iowrite32be(v,a) __raw_writel(cpu_to_be32((v)),(a)) |
163 | ||
64c9627c PM |
164 | #define ioread8_rep(a, d, c) __raw_readsb((a), (d), (c)) |
165 | #define ioread16_rep(a, d, c) __raw_readsw((a), (d), (c)) | |
166 | #define ioread32_rep(a, d, c) __raw_readsl((a), (d), (c)) | |
b66c1a39 | 167 | |
64c9627c PM |
168 | #define iowrite8_rep(a, s, c) __raw_writesb((a), (s), (c)) |
169 | #define iowrite16_rep(a, s, c) __raw_writesw((a), (s), (c)) | |
170 | #define iowrite32_rep(a, s, c) __raw_writesl((a), (s), (c)) | |
15444a89 DM |
171 | #endif |
172 | ||
173 | #define mmio_insb(p,d,c) __raw_readsb(p,d,c) | |
174 | #define mmio_insw(p,d,c) __raw_readsw(p,d,c) | |
175 | #define mmio_insl(p,d,c) __raw_readsl(p,d,c) | |
176 | ||
177 | #define mmio_outsb(p,s,c) __raw_writesb(p,s,c) | |
178 | #define mmio_outsw(p,s,c) __raw_writesw(p,s,c) | |
179 | #define mmio_outsl(p,s,c) __raw_writesl(p,s,c) | |
b66c1a39 | 180 | |
14866543 PM |
181 | /* synco on SH-4A, otherwise a nop */ |
182 | #define mmiowb() wmb() | |
1da177e4 | 183 | |
0f2c15ce PM |
184 | #define IO_SPACE_LIMIT 0xffffffff |
185 | ||
1da177e4 | 186 | /* |
14866543 PM |
187 | * This function provides a method for the generic case where a |
188 | * board-specific ioport_map simply needs to return the port + some | |
189 | * arbitrary port base. | |
1da177e4 LT |
190 | * |
191 | * We use this at board setup time to implicitly set the port base, and | |
b66c1a39 | 192 | * as a result, we can use the generic ioport_map. |
1da177e4 LT |
193 | */ |
194 | static inline void __set_io_port_base(unsigned long pbase) | |
195 | { | |
1da177e4 LT |
196 | generic_io_base = pbase; |
197 | } | |
198 | ||
e7cc9a73 MD |
199 | #define __ioport_map(p, n) sh_mv.mv_ioport_map((p), (n)) |
200 | ||
1da177e4 | 201 | /* We really want to try and get these to memcpy etc */ |
14866543 PM |
202 | void memcpy_fromio(void *, const volatile void __iomem *, unsigned long); |
203 | void memcpy_toio(volatile void __iomem *, const void *, unsigned long); | |
204 | void memset_io(volatile void __iomem *, int, unsigned long); | |
959f85f8 | 205 | |
ac490a48 PM |
206 | /* Quad-word real-mode I/O, don't ask.. */ |
207 | unsigned long long peek_real_address_q(unsigned long long addr); | |
208 | unsigned long long poke_real_address_q(unsigned long long addr, | |
209 | unsigned long long val); | |
210 | ||
da06b8d0 PM |
211 | #if !defined(CONFIG_MMU) |
212 | #define virt_to_phys(address) ((unsigned long)(address)) | |
213 | #define phys_to_virt(address) ((void *)(address)) | |
d02b08f6 | 214 | #else |
da06b8d0 PM |
215 | #define virt_to_phys(address) (__pa(address)) |
216 | #define phys_to_virt(address) (__va(address)) | |
a2d1a5fa | 217 | #endif |
1da177e4 | 218 | |
1da177e4 | 219 | /* |
da06b8d0 PM |
220 | * On 32-bit SH, we traditionally have the whole physical address space |
221 | * mapped at all times (as MIPS does), so "ioremap()" and "iounmap()" do | |
222 | * not need to do anything but place the address in the proper segment. | |
223 | * This is true for P1 and P2 addresses, as well as some P3 ones. | |
224 | * However, most of the P3 addresses and newer cores using extended | |
225 | * addressing need to map through page tables, so the ioremap() | |
226 | * implementation becomes a bit more complicated. | |
1da177e4 | 227 | * |
da06b8d0 | 228 | * See arch/sh/mm/ioremap.c for additional notes on this. |
1da177e4 LT |
229 | * |
230 | * We cheat a bit and always return uncachable areas until we've fixed | |
b66c1a39 | 231 | * the drivers to handle caching properly. |
da06b8d0 PM |
232 | * |
233 | * On the SH-5 the concept of segmentation in the 1:1 PXSEG sense simply | |
234 | * doesn't exist, so everything must go through page tables. | |
1da177e4 | 235 | */ |
b66c1a39 | 236 | #ifdef CONFIG_MMU |
bf3cdeda | 237 | void __iomem *__ioremap_caller(unsigned long offset, unsigned long size, |
d57d6408 | 238 | pgprot_t prot, void *caller); |
b66c1a39 | 239 | void __iounmap(void __iomem *addr); |
ccd80587 | 240 | |
4d35b93a MF |
241 | #ifdef CONFIG_IOREMAP_FIXED |
242 | extern void __iomem *ioremap_fixed(resource_size_t, unsigned long, pgprot_t); | |
4f744aff | 243 | extern int iounmap_fixed(void __iomem *); |
4d35b93a | 244 | extern void ioremap_fixed_init(void); |
edf711b6 PM |
245 | #else |
246 | static inline void __iomem * | |
247 | ioremap_fixed(resource_size t phys_addr, unsigned long size, pgprot_t prot) | |
248 | { | |
249 | BUG(); | |
250 | } | |
251 | ||
252 | static inline void ioremap_fixed_init(void) { } | |
4f744aff | 253 | static inline int iounmap_fixed(void __iomem *addr) { return -EINVAL; } |
4d35b93a MF |
254 | #endif |
255 | ||
bf3cdeda | 256 | static inline void __iomem * |
d57d6408 | 257 | __ioremap(unsigned long offset, unsigned long size, pgprot_t prot) |
bf3cdeda | 258 | { |
d57d6408 | 259 | return __ioremap_caller(offset, size, prot, __builtin_return_address(0)); |
bf3cdeda PM |
260 | } |
261 | ||
b66c1a39 | 262 | static inline void __iomem * |
d57d6408 | 263 | __ioremap_29bit(unsigned long offset, unsigned long size, pgprot_t prot) |
1da177e4 | 264 | { |
a0ab3668 | 265 | #ifdef CONFIG_29BIT |
b66c1a39 PM |
266 | unsigned long last_addr = offset + size - 1; |
267 | ||
268 | /* | |
269 | * For P1 and P2 space this is trivial, as everything is already | |
270 | * mapped. Uncached access for P1 addresses are done through P2. | |
271 | * In the P3 case or for addresses outside of the 29-bit space, | |
272 | * mapping must be done by the PMB or by using page tables. | |
273 | */ | |
274 | if (likely(PXSEG(offset) < P3SEG && PXSEG(last_addr) < P3SEG)) { | |
d57d6408 | 275 | if (unlikely(pgprot_val(prot) & _PAGE_CACHABLE)) |
b66c1a39 PM |
276 | return (void __iomem *)P1SEGADDR(offset); |
277 | ||
278 | return (void __iomem *)P2SEGADDR(offset); | |
279 | } | |
716777db MD |
280 | |
281 | /* P4 above the store queues are always mapped. */ | |
282 | if (unlikely(offset >= P3_ADDR_MAX)) | |
283 | return (void __iomem *)P4SEGADDR(offset); | |
da06b8d0 | 284 | #endif |
b66c1a39 | 285 | |
a0ab3668 PM |
286 | return NULL; |
287 | } | |
288 | ||
289 | static inline void __iomem * | |
d57d6408 | 290 | __ioremap_mode(unsigned long offset, unsigned long size, pgprot_t prot) |
a0ab3668 PM |
291 | { |
292 | void __iomem *ret; | |
293 | ||
294 | ret = __ioremap_trapped(offset, size); | |
295 | if (ret) | |
296 | return ret; | |
297 | ||
d57d6408 | 298 | ret = __ioremap_29bit(offset, size, prot); |
a0ab3668 PM |
299 | if (ret) |
300 | return ret; | |
301 | ||
d57d6408 | 302 | return __ioremap(offset, size, prot); |
1da177e4 | 303 | } |
e6be3a25 | 304 | #else |
d57d6408 PM |
305 | #define __ioremap(offset, size, prot) ((void __iomem *)(offset)) |
306 | #define __ioremap_mode(offset, size, prot) ((void __iomem *)(offset)) | |
e6be3a25 MD |
307 | #define __iounmap(addr) do { } while (0) |
308 | #endif /* CONFIG_MMU */ | |
1da177e4 | 309 | |
d57d6408 PM |
310 | static inline void __iomem * |
311 | ioremap(unsigned long offset, unsigned long size) | |
312 | { | |
313 | return __ioremap_mode(offset, size, PAGE_KERNEL_NOCACHE); | |
314 | } | |
315 | ||
316 | static inline void __iomem * | |
317 | ioremap_cache(unsigned long offset, unsigned long size) | |
318 | { | |
319 | return __ioremap_mode(offset, size, PAGE_KERNEL); | |
320 | } | |
321 | ||
322 | static inline void __iomem * | |
323 | ioremap_prot(resource_size_t offset, unsigned long size, unsigned long flags) | |
324 | { | |
325 | return __ioremap_mode(offset, size, __pgprot(flags)); | |
326 | } | |
327 | ||
328 | #define ioremap_nocache ioremap | |
329 | #define p3_ioremap __ioremap | |
330 | #define iounmap __iounmap | |
b66c1a39 | 331 | |
14866543 PM |
332 | #define maybebadio(port) \ |
333 | printk(KERN_ERR "bad PC-like io %s:%u for port 0x%lx at 0x%08x\n", \ | |
334 | __func__, __LINE__, (port), (u32)__builtin_return_address(0)) | |
335 | ||
1da177e4 LT |
336 | /* |
337 | * Convert a physical pointer to a virtual kernel pointer for /dev/mem | |
338 | * access | |
339 | */ | |
340 | #define xlate_dev_mem_ptr(p) __va(p) | |
341 | ||
342 | /* | |
343 | * Convert a virtual cached pointer to an uncached pointer | |
344 | */ | |
345 | #define xlate_dev_kmem_ptr(p) p | |
346 | ||
185aed75 PM |
347 | #define ARCH_HAS_VALID_PHYS_ADDR_RANGE |
348 | int valid_phys_addr_range(unsigned long addr, size_t size); | |
349 | int valid_mmap_phys_addr_range(unsigned long pfn, size_t size); | |
350 | ||
1da177e4 LT |
351 | #endif /* __KERNEL__ */ |
352 | ||
353 | #endif /* __ASM_SH_IO_H */ |