Commit | Line | Data |
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36ddf31b PM |
1 | #ifndef __ASM_SH_CLOCK_H |
2 | #define __ASM_SH_CLOCK_H | |
3 | ||
36ddf31b PM |
4 | #include <linux/list.h> |
5 | #include <linux/seq_file.h> | |
a1153e27 | 6 | #include <linux/cpufreq.h> |
1d118562 | 7 | #include <linux/clk.h> |
de925426 | 8 | #include <linux/err.h> |
36ddf31b PM |
9 | |
10 | struct clk; | |
11 | ||
12 | struct clk_ops { | |
13 | void (*init)(struct clk *clk); | |
ae891a42 | 14 | int (*enable)(struct clk *clk); |
36ddf31b | 15 | void (*disable)(struct clk *clk); |
b68d8201 | 16 | unsigned long (*recalc)(struct clk *clk); |
1929cb34 | 17 | int (*set_rate)(struct clk *clk, unsigned long rate, int algo_id); |
d680c76e | 18 | int (*set_parent)(struct clk *clk, struct clk *parent); |
f6991b04 | 19 | long (*round_rate)(struct clk *clk, unsigned long rate); |
36ddf31b PM |
20 | }; |
21 | ||
22 | struct clk { | |
23 | struct list_head node; | |
24 | const char *name; | |
1d118562 | 25 | int id; |
36ddf31b PM |
26 | struct module *owner; |
27 | ||
28 | struct clk *parent; | |
29 | struct clk_ops *ops; | |
30 | ||
b1f6cfe4 PM |
31 | struct list_head children; |
32 | struct list_head sibling; /* node for children */ | |
33 | ||
4f5ecaa0 | 34 | int usecount; |
36ddf31b PM |
35 | |
36 | unsigned long rate; | |
37 | unsigned long flags; | |
a77b5ac0 | 38 | |
549b5e35 PM |
39 | void __iomem *enable_reg; |
40 | unsigned int enable_bit; | |
41 | ||
5c8f9d94 | 42 | unsigned long arch_flags; |
a77b5ac0 | 43 | void *priv; |
cedcf336 | 44 | struct dentry *dentry; |
a1153e27 | 45 | struct cpufreq_frequency_table *freq_table; |
36ddf31b PM |
46 | }; |
47 | ||
4ff29ff8 | 48 | #define CLK_ENABLE_ON_INIT (1 << 0) |
36ddf31b PM |
49 | |
50 | /* Should be defined by processor-specific code */ | |
253b0887 | 51 | void __deprecated arch_init_clk_ops(struct clk_ops **, int type); |
fa43972f | 52 | int __init arch_clk_init(void); |
36ddf31b PM |
53 | |
54 | /* arch/sh/kernel/cpu/clock.c */ | |
55 | int clk_init(void); | |
b1f6cfe4 PM |
56 | unsigned long followparent_recalc(struct clk *); |
57 | void recalculate_root_clocks(void); | |
58 | void propagate_rate(struct clk *); | |
aa87aa34 | 59 | int clk_reparent(struct clk *child, struct clk *parent); |
36ddf31b PM |
60 | int clk_register(struct clk *); |
61 | void clk_unregister(struct clk *); | |
62 | ||
253b0887 PM |
63 | /* arch/sh/kernel/cpu/clock-cpg.c */ |
64 | int __init __deprecated cpg_clk_init(void); | |
65 | ||
1929cb34 | 66 | /* the exported API, in addition to clk_set_rate */ |
67 | /** | |
68 | * clk_set_rate_ex - set the clock rate for a clock source, with additional parameter | |
69 | * @clk: clock source | |
70 | * @rate: desired clock rate in Hz | |
71 | * @algo_id: algorithm id to be passed down to ops->set_rate | |
72 | * | |
73 | * Returns success (0) or negative errno. | |
74 | */ | |
75 | int clk_set_rate_ex(struct clk *clk, unsigned long rate, int algo_id); | |
76 | ||
77 | enum clk_sh_algo_id { | |
78 | NO_CHANGE = 0, | |
79 | ||
80 | IUS_N1_N1, | |
81 | IUS_322, | |
82 | IUS_522, | |
83 | IUS_N11, | |
84 | ||
85 | SB_N1, | |
86 | ||
87 | SB3_N1, | |
88 | SB3_32, | |
89 | SB3_43, | |
90 | SB3_54, | |
91 | ||
92 | BP_N1, | |
93 | ||
94 | IP_N1, | |
95 | }; | |
b68d8201 | 96 | |
c94a8574 MD |
97 | struct clk_div_mult_table { |
98 | unsigned int *divisors; | |
99 | unsigned int nr_divisors; | |
100 | unsigned int *multipliers; | |
101 | unsigned int nr_multipliers; | |
102 | }; | |
103 | ||
104 | struct cpufreq_frequency_table; | |
105 | void clk_rate_table_build(struct clk *clk, | |
106 | struct cpufreq_frequency_table *freq_table, | |
107 | int nr_freqs, | |
108 | struct clk_div_mult_table *src_table, | |
109 | unsigned long *bitmap); | |
110 | ||
111 | long clk_rate_table_round(struct clk *clk, | |
112 | struct cpufreq_frequency_table *freq_table, | |
113 | unsigned long rate); | |
114 | ||
098dee99 MD |
115 | int clk_rate_table_find(struct clk *clk, |
116 | struct cpufreq_frequency_table *freq_table, | |
117 | unsigned long rate); | |
118 | ||
6881e8bf MD |
119 | #define SH_CLK_MSTP32(_name, _id, _parent, _enable_reg, \ |
120 | _enable_bit, _flags) \ | |
121 | { \ | |
122 | .name = _name, \ | |
123 | .id = _id, \ | |
124 | .parent = _parent, \ | |
125 | .enable_reg = (void __iomem *)_enable_reg, \ | |
126 | .enable_bit = _enable_bit, \ | |
127 | .flags = _flags, \ | |
128 | } | |
129 | ||
130 | int sh_clk_mstp32_register(struct clk *clks, int nr); | |
131 | ||
a1153e27 MD |
132 | #define SH_CLK_DIV4(_name, _parent, _reg, _shift, _div_bitmap, _flags) \ |
133 | { \ | |
134 | .name = _name, \ | |
135 | .parent = _parent, \ | |
136 | .enable_reg = (void __iomem *)_reg, \ | |
137 | .enable_bit = _shift, \ | |
138 | .arch_flags = _div_bitmap, \ | |
139 | .flags = _flags, \ | |
140 | } | |
141 | ||
0a5f337e MD |
142 | struct clk_div4_table { |
143 | struct clk_div_mult_table *div_mult_table; | |
7be85c6e | 144 | void (*kick)(struct clk *clk); |
0a5f337e MD |
145 | }; |
146 | ||
a1153e27 | 147 | int sh_clk_div4_register(struct clk *clks, int nr, |
0a5f337e | 148 | struct clk_div4_table *table); |
31c3af50 | 149 | int sh_clk_div4_enable_register(struct clk *clks, int nr, |
0a5f337e | 150 | struct clk_div4_table *table); |
31c3af50 | 151 | int sh_clk_div4_reparent_register(struct clk *clks, int nr, |
0a5f337e | 152 | struct clk_div4_table *table); |
a1153e27 | 153 | |
9e1985e1 MD |
154 | #define SH_CLK_DIV6(_parent, _reg, _flags) \ |
155 | { \ | |
156 | .parent = _parent, \ | |
157 | .enable_reg = (void __iomem *)_reg, \ | |
158 | .flags = _flags, \ | |
2693e274 MD |
159 | } |
160 | ||
161 | int sh_clk_div6_register(struct clk *clks, int nr); | |
162 | ||
36ddf31b | 163 | #endif /* __ASM_SH_CLOCK_H */ |