[linux-2.6-block.git] / arch / sh / boards / mach-migor / setup.c

/*
 * Renesas System Solutions Asia Pte. Ltd - Migo-R
 *
 * Copyright (C) 2008 Magnus Damm
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 */
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/interrupt.h>
#include <linux/input.h>
#include <linux/input/sh_keysc.h>
#include <linux/mmc/host.h>
#include <linux/mmc/sh_mobile_sdhi.h>
#include <linux/mtd/physmap.h>
#include <linux/mtd/nand.h>
#include <linux/i2c.h>
#include <linux/smc91x.h>
#include <linux/delay.h>
#include <linux/clk.h>
#include <linux/gpio.h>
#include <video/sh_mobile_lcdc.h>
#include <media/sh_mobile_ceu.h>
#include <media/ov772x.h>
#include <media/tw9910.h>
#include <asm/clock.h>
#include <asm/machvec.h>
#include <asm/io.h>
#include <asm/suspend.h>
#include <mach/migor.h>
#include <cpu/sh7722.h>

/* Address     IRQ  Size  Bus  Description
 * 0x00000000       64MB  16   NOR Flash (SP29PL256N)
 * 0x0c000000       64MB  64   SDRAM (2xK4M563233G)
 * 0x10000000  IRQ0       16   Ethernet (SMC91C111)
 * 0x14000000  IRQ4       16   USB 2.0 Host Controller (M66596)
 * 0x18000000       8GB    8   NAND Flash (K9K8G08U0A)
 */

static struct smc91x_platdata smc91x_info = {
	.flags = SMC91X_USE_16BIT | SMC91X_NOWAIT,
};

static struct resource smc91x_eth_resources[] = {
	[0] = {
		.name   = "SMC91C111" ,
		.start  = 0x10000300,
		.end    = 0x1000030f,
		.flags  = IORESOURCE_MEM,
	},
	[1] = {
		.start  = 32, /* IRQ0 */
		.flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
	},
};

static struct platform_device smc91x_eth_device = {
	.name           = "smc91x",
	.num_resources  = ARRAY_SIZE(smc91x_eth_resources),
	.resource       = smc91x_eth_resources,
	.dev	= {
		.platform_data	= &smc91x_info,
	},
};

static struct sh_keysc_info sh_keysc_info = {
	.mode = SH_KEYSC_MODE_2, /* KEYOUT0->4, KEYIN1->5 */
	.scan_timing = 3,
	.delay = 5,
	.keycodes = {
		0, KEY_UP, KEY_DOWN, KEY_LEFT, KEY_RIGHT, KEY_ENTER,
		0, KEY_F, KEY_C, KEY_D,	KEY_H, KEY_1,
		0, KEY_2, KEY_3, KEY_4,	KEY_5, KEY_6,
		0, KEY_7, KEY_8, KEY_9, KEY_S, KEY_0,
		0, KEY_P, KEY_STOP, KEY_REWIND, KEY_PLAY, KEY_FASTFORWARD,
	},
};

static struct resource sh_keysc_resources[] = {
	[0] = {
		.start  = 0x044b0000,
		.end    = 0x044b000f,
		.flags  = IORESOURCE_MEM,
	},
	[1] = {
		.start  = 79,
		.flags  = IORESOURCE_IRQ,
	},
};

static struct platform_device sh_keysc_device = {
	.name           = "sh_keysc",
	.id             = 0, /* "keysc0" clock */
	.num_resources  = ARRAY_SIZE(sh_keysc_resources),
	.resource       = sh_keysc_resources,
	.dev	= {
		.platform_data	= &sh_keysc_info,
	},
	.archdata = {
		.hwblk_id = HWBLK_KEYSC,
	},
};

static struct mtd_partition migor_nor_flash_partitions[] =
{
	{
		.name = "uboot",
		.offset = 0,
		.size = (1 * 1024 * 1024),
		.mask_flags = MTD_WRITEABLE,	/* Read-only */
	},
	{
		.name = "rootfs",
		.offset = MTDPART_OFS_APPEND,
		.size = (15 * 1024 * 1024),
	},
	{
		.name = "other",
		.offset = MTDPART_OFS_APPEND,
		.size = MTDPART_SIZ_FULL,
	},
};

static struct physmap_flash_data migor_nor_flash_data = {
	.width		= 2,
	.parts		= migor_nor_flash_partitions,
	.nr_parts	= ARRAY_SIZE(migor_nor_flash_partitions),
};

static struct resource migor_nor_flash_resources[] = {
	[0] = {
		.name		= "NOR Flash",
		.start		= 0x00000000,
		.end		= 0x03ffffff,
		.flags		= IORESOURCE_MEM,
	}
};

static struct platform_device migor_nor_flash_device = {
	.name		= "physmap-flash",
	.resource	= migor_nor_flash_resources,
	.num_resources	= ARRAY_SIZE(migor_nor_flash_resources),
	.dev		= {
		.platform_data = &migor_nor_flash_data,
	},
};

static struct mtd_partition migor_nand_flash_partitions[] = {
	{
		.name		= "nanddata1",
		.offset		= 0x0,
		.size		= 512 * 1024 * 1024,
	},
	{
		.name		= "nanddata2",
		.offset		= MTDPART_OFS_APPEND,
		.size		= 512 * 1024 * 1024,
	},
};

static void migor_nand_flash_cmd_ctl(struct mtd_info *mtd, int cmd,
				     unsigned int ctrl)
{
	struct nand_chip *chip = mtd->priv;

	if (cmd == NAND_CMD_NONE)
		return;

	if (ctrl & NAND_CLE)
		writeb(cmd, chip->IO_ADDR_W + 0x00400000);
	else if (ctrl & NAND_ALE)
		writeb(cmd, chip->IO_ADDR_W + 0x00800000);
	else
		writeb(cmd, chip->IO_ADDR_W);
}

static int migor_nand_flash_ready(struct mtd_info *mtd)
{
	return gpio_get_value(GPIO_PTA1); /* NAND_RBn */
}

static struct platform_nand_data migor_nand_flash_data = {
	.chip = {
		.nr_chips = 1,
		.partitions = migor_nand_flash_partitions,
		.nr_partitions = ARRAY_SIZE(migor_nand_flash_partitions),
		.chip_delay = 20,
		.part_probe_types = (const char *[]) { "cmdlinepart", NULL },
	},
	.ctrl = {
		.dev_ready = migor_nand_flash_ready,
		.cmd_ctrl = migor_nand_flash_cmd_ctl,
	},
};

static struct resource migor_nand_flash_resources[] = {
	[0] = {
		.name		= "NAND Flash",
		.start		= 0x18000000,
		.end		= 0x18ffffff,
		.flags		= IORESOURCE_MEM,
	},
};

static struct platform_device migor_nand_flash_device = {
	.name		= "gen_nand",
	.resource	= migor_nand_flash_resources,
	.num_resources	= ARRAY_SIZE(migor_nand_flash_resources),
	.dev		= {
		.platform_data = &migor_nand_flash_data,
	}
};

const static struct fb_videomode migor_lcd_modes[] = {
	{
#if defined(CONFIG_SH_MIGOR_RTA_WVGA)
		.name = "LB070WV1",
		.xres = 800,
		.yres = 480,
		.left_margin = 64,
		.right_margin = 16,
		.hsync_len = 120,
		.sync = 0,
#elif defined(CONFIG_SH_MIGOR_QVGA)
		.name = "PH240320T",
		.xres = 320,
		.yres = 240,
		.left_margin = 0,
		.right_margin = 16,
		.hsync_len = 8,
		.sync = FB_SYNC_HOR_HIGH_ACT,
#endif
		.upper_margin = 1,
		.lower_margin = 17,
		.vsync_len = 2,
	},
};

static struct sh_mobile_lcdc_info sh_mobile_lcdc_info = {
#if defined(CONFIG_SH_MIGOR_RTA_WVGA)
	.clock_source = LCDC_CLK_BUS,
	.ch[0] = {
		.chan = LCDC_CHAN_MAINLCD,
		.bpp = 16,
		.interface_type = RGB16,
		.clock_divider = 2,
		.lcd_cfg = migor_lcd_modes,
		.num_cfg = ARRAY_SIZE(migor_lcd_modes),
		.lcd_size_cfg = { /* 7.0 inch */
			.width = 152,
			.height = 91,
		},
	}
#elif defined(CONFIG_SH_MIGOR_QVGA)
	.clock_source = LCDC_CLK_PERIPHERAL,
	.ch[0] = {
		.chan = LCDC_CHAN_MAINLCD,
		.bpp = 16,
		.interface_type = SYS16A,
		.clock_divider = 10,
		.lcd_cfg = migor_lcd_modes,
		.num_cfg = ARRAY_SIZE(migor_lcd_modes),
		.lcd_size_cfg = { /* 2.4 inch */
			.width = 49,
			.height = 37,
		},
		.board_cfg = {
			.setup_sys = migor_lcd_qvga_setup,
		},
		.sys_bus_cfg = {
			.ldmt2r = 0x06000a09,
			.ldmt3r = 0x180e3418,
			/* set 1s delay to encourage fsync() */
			.deferred_io_msec = 1000,
		},
	}
#endif
};

static struct resource migor_lcdc_resources[] = {
	[0] = {
		.name	= "LCDC",
		.start	= 0xfe940000, /* P4-only space */
		.end	= 0xfe942fff,
		.flags	= IORESOURCE_MEM,
	},
	[1] = {
		.start	= 28,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct platform_device migor_lcdc_device = {
	.name		= "sh_mobile_lcdc_fb",
	.num_resources	= ARRAY_SIZE(migor_lcdc_resources),
	.resource	= migor_lcdc_resources,
	.dev	= {
		.platform_data	= &sh_mobile_lcdc_info,
	},
	.archdata = {
		.hwblk_id = HWBLK_LCDC,
	},
};

static struct clk *camera_clk;
static DEFINE_MUTEX(camera_lock);

static void camera_power_on(int is_tw)
{
	mutex_lock(&camera_lock);

	/* Use 10 MHz VIO_CKO instead of 24 MHz to work
	 * around signal quality issues on Panel Board V2.1.
	 */
	camera_clk = clk_get(NULL, "video_clk");
	clk_set_rate(camera_clk, 10000000);
	clk_enable(camera_clk);	/* start VIO_CKO */

	/* use VIO_RST to take camera out of reset */
	mdelay(10);
	if (is_tw) {
		gpio_set_value(GPIO_PTT2, 0);
		gpio_set_value(GPIO_PTT0, 0);
	} else {
		gpio_set_value(GPIO_PTT0, 1);
	}
	gpio_set_value(GPIO_PTT3, 0);
	mdelay(10);
	gpio_set_value(GPIO_PTT3, 1);
	mdelay(10); /* wait to let chip come out of reset */
}

static void camera_power_off(void)
{
	clk_disable(camera_clk); /* stop VIO_CKO */
	clk_put(camera_clk);

	gpio_set_value(GPIO_PTT3, 0);
	mutex_unlock(&camera_lock);
}

static int ov7725_power(struct device *dev, int mode)
{
	if (mode)
		camera_power_on(0);
	else
		camera_power_off();

	return 0;
}

static int tw9910_power(struct device *dev, int mode)
{
	if (mode)
		camera_power_on(1);
	else
		camera_power_off();

	return 0;
}

static struct sh_mobile_ceu_info sh_mobile_ceu_info = {
	.flags = SH_CEU_FLAG_USE_8BIT_BUS,
};

static struct resource migor_ceu_resources[] = {
	[0] = {
		.name	= "CEU",
		.start	= 0xfe910000,
		.end	= 0xfe91009f,
		.flags	= IORESOURCE_MEM,
	},
	[1] = {
		.start  = 52,
		.flags  = IORESOURCE_IRQ,
	},
	[2] = {
		/* place holder for contiguous memory */
	},
};

static struct platform_device migor_ceu_device = {
	.name		= "sh_mobile_ceu",
	.id             = 0, /* "ceu0" clock */
	.num_resources	= ARRAY_SIZE(migor_ceu_resources),
	.resource	= migor_ceu_resources,
	.dev	= {
		.platform_data	= &sh_mobile_ceu_info,
	},
	.archdata = {
		.hwblk_id = HWBLK_CEU,
	},
};

static struct resource sdhi_cn9_resources[] = {
	[0] = {
		.name	= "SDHI",
		.start	= 0x04ce0000,
		.end	= 0x04ce01ff,
		.flags	= IORESOURCE_MEM,
	},
	[1] = {
		.start	= 100,
		.flags  = IORESOURCE_IRQ,
	},
};

static struct sh_mobile_sdhi_info sh7724_sdhi_data = {
	.dma_slave_tx	= SHDMA_SLAVE_SDHI0_TX,
	.dma_slave_rx	= SHDMA_SLAVE_SDHI0_RX,
	.tmio_caps      = MMC_CAP_SDIO_IRQ,
};

static struct platform_device sdhi_cn9_device = {
	.name		= "sh_mobile_sdhi",
	.num_resources	= ARRAY_SIZE(sdhi_cn9_resources),
	.resource	= sdhi_cn9_resources,
	.dev = {
		.platform_data	= &sh7724_sdhi_data,
	},
	.archdata = {
		.hwblk_id = HWBLK_SDHI,
	},
};

static struct i2c_board_info migor_i2c_devices[] = {
	{
		I2C_BOARD_INFO("rs5c372b", 0x32),
	},
	{
		I2C_BOARD_INFO("migor_ts", 0x51),
		.irq = 38, /* IRQ6 */
	},
	{
		I2C_BOARD_INFO("wm8978", 0x1a),
	},
};

static struct i2c_board_info migor_i2c_camera[] = {
	{
		I2C_BOARD_INFO("ov772x", 0x21),
	},
	{
		I2C_BOARD_INFO("tw9910", 0x45),
	},
};

static struct ov772x_camera_info ov7725_info = {
	.flags		= OV772X_FLAG_8BIT,
};

static struct soc_camera_link ov7725_link = {
	.power		= ov7725_power,
	.board_info	= &migor_i2c_camera[0],
	.i2c_adapter_id	= 0,
	.priv		= &ov7725_info,
};

static struct tw9910_video_info tw9910_info = {
	.buswidth	= SOCAM_DATAWIDTH_8,
	.mpout		= TW9910_MPO_FIELD,
};

static struct soc_camera_link tw9910_link = {
	.power		= tw9910_power,
	.board_info	= &migor_i2c_camera[1],
	.i2c_adapter_id	= 0,
	.priv		= &tw9910_info,
};

static struct platform_device migor_camera[] = {
	{
		.name	= "soc-camera-pdrv",
		.id	= 0,
		.dev	= {
			.platform_data = &ov7725_link,
		},
	}, {
		.name	= "soc-camera-pdrv",
		.id	= 1,
		.dev	= {
			.platform_data = &tw9910_link,
		},
	},
};

static struct platform_device *migor_devices[] __initdata = {
	&smc91x_eth_device,
	&sh_keysc_device,
	&migor_lcdc_device,
	&migor_ceu_device,
	&migor_nor_flash_device,
	&migor_nand_flash_device,
	&sdhi_cn9_device,
	&migor_camera[0],
	&migor_camera[1],
};

extern char migor_sdram_enter_start;
extern char migor_sdram_enter_end;
extern char migor_sdram_leave_start;
extern char migor_sdram_leave_end;

static int __init migor_devices_setup(void)
{
	/* register board specific self-refresh code */
	sh_mobile_register_self_refresh(SUSP_SH_STANDBY | SUSP_SH_SF,
					&migor_sdram_enter_start,
					&migor_sdram_enter_end,
					&migor_sdram_leave_start,
					&migor_sdram_leave_end);
	/* Let D11 LED show STATUS0 */
	gpio_request(GPIO_FN_STATUS0, NULL);

	/* Lit D12 LED show PDSTATUS */
	gpio_request(GPIO_FN_PDSTATUS, NULL);

	/* SMC91C111 - Enable IRQ0, Setup CS4 for 16-bit fast access */
	gpio_request(GPIO_FN_IRQ0, NULL);
	__raw_writel(0x00003400, BSC_CS4BCR);
	__raw_writel(0x00110080, BSC_CS4WCR);

	/* KEYSC */
	gpio_request(GPIO_FN_KEYOUT0, NULL);
	gpio_request(GPIO_FN_KEYOUT1, NULL);
	gpio_request(GPIO_FN_KEYOUT2, NULL);
	gpio_request(GPIO_FN_KEYOUT3, NULL);
	gpio_request(GPIO_FN_KEYOUT4_IN6, NULL);
	gpio_request(GPIO_FN_KEYIN1, NULL);
	gpio_request(GPIO_FN_KEYIN2, NULL);
	gpio_request(GPIO_FN_KEYIN3, NULL);
	gpio_request(GPIO_FN_KEYIN4, NULL);
	gpio_request(GPIO_FN_KEYOUT5_IN5, NULL);

	/* NAND Flash */
	gpio_request(GPIO_FN_CS6A_CE2B, NULL);
	__raw_writel((__raw_readl(BSC_CS6ABCR) & ~0x0600) | 0x0200, BSC_CS6ABCR);
	gpio_request(GPIO_PTA1, NULL);
	gpio_direction_input(GPIO_PTA1);

	/* SDHI */
	gpio_request(GPIO_FN_SDHICD, NULL);
	gpio_request(GPIO_FN_SDHIWP, NULL);
	gpio_request(GPIO_FN_SDHID3, NULL);
	gpio_request(GPIO_FN_SDHID2, NULL);
	gpio_request(GPIO_FN_SDHID1, NULL);
	gpio_request(GPIO_FN_SDHID0, NULL);
	gpio_request(GPIO_FN_SDHICMD, NULL);
	gpio_request(GPIO_FN_SDHICLK, NULL);

	/* Touch Panel */
	gpio_request(GPIO_FN_IRQ6, NULL);

	/* LCD Panel */
#ifdef CONFIG_SH_MIGOR_QVGA /* LCDC - QVGA - Enable SYS Interface signals */
	gpio_request(GPIO_FN_LCDD17, NULL);
	gpio_request(GPIO_FN_LCDD16, NULL);
	gpio_request(GPIO_FN_LCDD15, NULL);
	gpio_request(GPIO_FN_LCDD14, NULL);
	gpio_request(GPIO_FN_LCDD13, NULL);
	gpio_request(GPIO_FN_LCDD12, NULL);
	gpio_request(GPIO_FN_LCDD11, NULL);
	gpio_request(GPIO_FN_LCDD10, NULL);
	gpio_request(GPIO_FN_LCDD8, NULL);
	gpio_request(GPIO_FN_LCDD7, NULL);
	gpio_request(GPIO_FN_LCDD6, NULL);
	gpio_request(GPIO_FN_LCDD5, NULL);
	gpio_request(GPIO_FN_LCDD4, NULL);
	gpio_request(GPIO_FN_LCDD3, NULL);
	gpio_request(GPIO_FN_LCDD2, NULL);
	gpio_request(GPIO_FN_LCDD1, NULL);
	gpio_request(GPIO_FN_LCDRS, NULL);
	gpio_request(GPIO_FN_LCDCS, NULL);
	gpio_request(GPIO_FN_LCDRD, NULL);
	gpio_request(GPIO_FN_LCDWR, NULL);
	gpio_request(GPIO_PTH2, NULL); /* LCD_DON */
	gpio_direction_output(GPIO_PTH2, 1);
#endif
#ifdef CONFIG_SH_MIGOR_RTA_WVGA /* LCDC - WVGA - Enable RGB Interface signals */
	gpio_request(GPIO_FN_LCDD15, NULL);
	gpio_request(GPIO_FN_LCDD14, NULL);
	gpio_request(GPIO_FN_LCDD13, NULL);
	gpio_request(GPIO_FN_LCDD12, NULL);
	gpio_request(GPIO_FN_LCDD11, NULL);
	gpio_request(GPIO_FN_LCDD10, NULL);
	gpio_request(GPIO_FN_LCDD9, NULL);
	gpio_request(GPIO_FN_LCDD8, NULL);
	gpio_request(GPIO_FN_LCDD7, NULL);
	gpio_request(GPIO_FN_LCDD6, NULL);
	gpio_request(GPIO_FN_LCDD5, NULL);
	gpio_request(GPIO_FN_LCDD4, NULL);
	gpio_request(GPIO_FN_LCDD3, NULL);
	gpio_request(GPIO_FN_LCDD2, NULL);
	gpio_request(GPIO_FN_LCDD1, NULL);
	gpio_request(GPIO_FN_LCDD0, NULL);
	gpio_request(GPIO_FN_LCDLCLK, NULL);
	gpio_request(GPIO_FN_LCDDCK, NULL);
	gpio_request(GPIO_FN_LCDVEPWC, NULL);
	gpio_request(GPIO_FN_LCDVCPWC, NULL);
	gpio_request(GPIO_FN_LCDVSYN, NULL);
	gpio_request(GPIO_FN_LCDHSYN, NULL);
	gpio_request(GPIO_FN_LCDDISP, NULL);
	gpio_request(GPIO_FN_LCDDON, NULL);
#endif

	/* CEU */
	gpio_request(GPIO_FN_VIO_CLK2, NULL);
	gpio_request(GPIO_FN_VIO_VD2, NULL);
	gpio_request(GPIO_FN_VIO_HD2, NULL);
	gpio_request(GPIO_FN_VIO_FLD, NULL);
	gpio_request(GPIO_FN_VIO_CKO, NULL);
	gpio_request(GPIO_FN_VIO_D15, NULL);
	gpio_request(GPIO_FN_VIO_D14, NULL);
	gpio_request(GPIO_FN_VIO_D13, NULL);
	gpio_request(GPIO_FN_VIO_D12, NULL);
	gpio_request(GPIO_FN_VIO_D11, NULL);
	gpio_request(GPIO_FN_VIO_D10, NULL);
	gpio_request(GPIO_FN_VIO_D9, NULL);
	gpio_request(GPIO_FN_VIO_D8, NULL);

	gpio_request(GPIO_PTT3, NULL); /* VIO_RST */
	gpio_direction_output(GPIO_PTT3, 0);
	gpio_request(GPIO_PTT2, NULL); /* TV_IN_EN */
	gpio_direction_output(GPIO_PTT2, 1);
	gpio_request(GPIO_PTT0, NULL); /* CAM_EN */
#ifdef CONFIG_SH_MIGOR_RTA_WVGA
	gpio_direction_output(GPIO_PTT0, 0);
#else
	gpio_direction_output(GPIO_PTT0, 1);
#endif
	__raw_writew(__raw_readw(PORT_MSELCRB) | 0x2000, PORT_MSELCRB); /* D15->D8 */

	platform_resource_setup_memory(&migor_ceu_device, "ceu", 4 << 20);

	/* SIU: Port B */
	gpio_request(GPIO_FN_SIUBOLR, NULL);
	gpio_request(GPIO_FN_SIUBOBT, NULL);
	gpio_request(GPIO_FN_SIUBISLD, NULL);
	gpio_request(GPIO_FN_SIUBOSLD, NULL);
	gpio_request(GPIO_FN_SIUMCKB, NULL);

	/*
	 * The original driver sets SIUB OLR/OBT, ILR/IBT, and SIUA OLR/OBT to
	 * output. Need only SIUB, set to output for master mode (table 34.2)
	 */
	__raw_writew(__raw_readw(PORT_MSELCRA) | 1, PORT_MSELCRA);

	i2c_register_board_info(0, migor_i2c_devices,
				ARRAY_SIZE(migor_i2c_devices));

	return platform_add_devices(migor_devices, ARRAY_SIZE(migor_devices));
}
arch_initcall(migor_devices_setup);

/* Return the board specific boot mode pin configuration */
static int migor_mode_pins(void)
{
	/* MD0=1, MD1=1, MD2=0: Clock Mode 3
	 * MD3=0: 16-bit Area0 Bus Width
	 * MD5=1: Little Endian
	 * TSTMD=1, MD8=0: Test Mode Disabled
	 */
	return MODE_PIN0 | MODE_PIN1 | MODE_PIN5;
}

/*
 * The Machine Vector
 */
static struct sh_machine_vector mv_migor __initmv = {
	.mv_name		= "Migo-R",
	.mv_mode_pins		= migor_mode_pins,
};
Commit	Line	Data
70f784ec MD	1	/*
	2	* Renesas System Solutions Asia Pte. Ltd - Migo-R
	3	*
	4	* Copyright (C) 2008 Magnus Damm
	5	*
	6	* This file is subject to the terms and conditions of the GNU General Public
	7	* License. See the file "COPYING" in the main directory of this archive
	8	* for more details.
	9	*/
	10	#include <linux/init.h>
	11	#include <linux/platform_device.h>
	12	#include <linux/interrupt.h>
92cfeb61	13	#include <linux/input.h>
fc1d003d	14	#include <linux/input/sh_keysc.h>
464495e5	15	#include <linux/mmc/host.h>
960b9e7e	16	#include <linux/mmc/sh_mobile_sdhi.h>
b8808786	17	#include <linux/mtd/physmap.h>
3c803a9a	18	#include <linux/mtd/nand.h>
0c6111ec	19	#include <linux/i2c.h>
8a3ee0fc	20	#include <linux/smc91x.h>
1765534c MD	21	#include <linux/delay.h>
1765534c MD	22	#include <linux/clk.h>
91b6f3c5	23	#include <linux/gpio.h>
70e5c4f0	24	#include <video/sh_mobile_lcdc.h>
1765534c	25	#include <media/sh_mobile_ceu.h>
ff04ea40	26	#include <media/ov772x.h>
deae7b86	27	#include <media/tw9910.h>
6c7d826c	28	#include <asm/clock.h>
70f784ec MD	29	#include <asm/machvec.h>
70f784ec MD	30	#include <asm/io.h>
13fa551b	31	#include <asm/suspend.h>
7639a454	32	#include <mach/migor.h>
f7275650	33	#include <cpu/sh7722.h>
70f784ec MD	34
	35	/* Address IRQ Size Bus Description
	36	* 0x00000000 64MB 16 NOR Flash (SP29PL256N)
	37	* 0x0c000000 64MB 64 SDRAM (2xK4M563233G)
	38	* 0x10000000 IRQ0 16 Ethernet (SMC91C111)
	39	* 0x14000000 IRQ4 16 USB 2.0 Host Controller (M66596)
	40	* 0x18000000 8GB 8 NAND Flash (K9K8G08U0A)
	41	*/
	42
8a3ee0fc	43	static struct smc91x_platdata smc91x_info = {
a30c89ad	44	.flags = SMC91X_USE_16BIT \| SMC91X_NOWAIT,
8a3ee0fc MD	45	};
8a3ee0fc MD	46
70f784ec MD	47	static struct resource smc91x_eth_resources[] = {
70f784ec MD	48	[0] = {
b026a23c MD	49	.name = "SMC91C111" ,
	50	.start = 0x10000300,
	51	.end = 0x1000030f,
70f784ec MD	52	.flags = IORESOURCE_MEM,
	53	},
	54	[1] = {
	55	.start = 32, /* IRQ0 */
d280eadc	56	.flags = IORESOURCE_IRQ \| IORESOURCE_IRQ_HIGHLEVEL,
70f784ec MD	57	},
	58	};
	59
	60	static struct platform_device smc91x_eth_device = {
	61	.name = "smc91x",
	62	.num_resources = ARRAY_SIZE(smc91x_eth_resources),
	63	.resource = smc91x_eth_resources,
8a3ee0fc MD	64	.dev = {
	65	.platform_data = &smc91x_info,
	66	},
70f784ec MD	67	};
70f784ec MD	68
92cfeb61 MD	69	static struct sh_keysc_info sh_keysc_info = {
	70	.mode = SH_KEYSC_MODE_2, /* KEYOUT0->4, KEYIN1->5 */
	71	.scan_timing = 3,
	72	.delay = 5,
	73	.keycodes = {
	74	0, KEY_UP, KEY_DOWN, KEY_LEFT, KEY_RIGHT, KEY_ENTER,
	75	0, KEY_F, KEY_C, KEY_D, KEY_H, KEY_1,
	76	0, KEY_2, KEY_3, KEY_4, KEY_5, KEY_6,
	77	0, KEY_7, KEY_8, KEY_9, KEY_S, KEY_0,
	78	0, KEY_P, KEY_STOP, KEY_REWIND, KEY_PLAY, KEY_FASTFORWARD,
	79	},
	80	};
	81
	82	static struct resource sh_keysc_resources[] = {
	83	[0] = {
	84	.start = 0x044b0000,
	85	.end = 0x044b000f,
	86	.flags = IORESOURCE_MEM,
	87	},
	88	[1] = {
	89	.start = 79,
	90	.flags = IORESOURCE_IRQ,
	91	},
	92	};
	93
	94	static struct platform_device sh_keysc_device = {
	95	.name = "sh_keysc",
090d951b	96	.id = 0, /* "keysc0" clock */
92cfeb61 MD	97	.num_resources = ARRAY_SIZE(sh_keysc_resources),
	98	.resource = sh_keysc_resources,
	99	.dev = {
	100	.platform_data = &sh_keysc_info,
	101	},
2de63cf3 MD	102	.archdata = {
	103	.hwblk_id = HWBLK_KEYSC,
	104	},
92cfeb61 MD	105	};
92cfeb61 MD	106
b8808786 MD	107	static struct mtd_partition migor_nor_flash_partitions[] =
	108	{
	109	{
	110	.name = "uboot",
	111	.offset = 0,
	112	.size = (1 * 1024 * 1024),
	113	.mask_flags = MTD_WRITEABLE, /* Read-only */
	114	},
	115	{
	116	.name = "rootfs",
	117	.offset = MTDPART_OFS_APPEND,
	118	.size = (15 * 1024 * 1024),
	119	},
	120	{
	121	.name = "other",
	122	.offset = MTDPART_OFS_APPEND,
	123	.size = MTDPART_SIZ_FULL,
	124	},
	125	};
	126
	127	static struct physmap_flash_data migor_nor_flash_data = {
	128	.width = 2,
	129	.parts = migor_nor_flash_partitions,
	130	.nr_parts = ARRAY_SIZE(migor_nor_flash_partitions),
	131	};
	132
	133	static struct resource migor_nor_flash_resources[] = {
	134	[0] = {
	135	.name = "NOR Flash",
	136	.start = 0x00000000,
	137	.end = 0x03ffffff,
	138	.flags = IORESOURCE_MEM,
	139	}
	140	};
	141
	142	static struct platform_device migor_nor_flash_device = {
	143	.name = "physmap-flash",
	144	.resource = migor_nor_flash_resources,
	145	.num_resources = ARRAY_SIZE(migor_nor_flash_resources),
	146	.dev = {
	147	.platform_data = &migor_nor_flash_data,
	148	},
	149	};
	150
3c803a9a MD	151	static struct mtd_partition migor_nand_flash_partitions[] = {
	152	{
	153	.name = "nanddata1",
	154	.offset = 0x0,
	155	.size = 512 * 1024 * 1024,
	156	},
	157	{
	158	.name = "nanddata2",
	159	.offset = MTDPART_OFS_APPEND,
	160	.size = 512 * 1024 * 1024,
	161	},
	162	};
	163
	164	static void migor_nand_flash_cmd_ctl(struct mtd_info *mtd, int cmd,
	165	unsigned int ctrl)
	166	{
	167	struct nand_chip *chip = mtd->priv;
	168
	169	if (cmd == NAND_CMD_NONE)
	170	return;
	171
	172	if (ctrl & NAND_CLE)
	173	writeb(cmd, chip->IO_ADDR_W + 0x00400000);
	174	else if (ctrl & NAND_ALE)
	175	writeb(cmd, chip->IO_ADDR_W + 0x00800000);
	176	else
	177	writeb(cmd, chip->IO_ADDR_W);
	178	}
	179
	180	static int migor_nand_flash_ready(struct mtd_info *mtd)
	181	{
91b6f3c5	182	return gpio_get_value(GPIO_PTA1); /* NAND_RBn */
3c803a9a MD	183	}
3c803a9a MD	184
30e0cc1a	185	static struct platform_nand_data migor_nand_flash_data = {
3c803a9a MD	186	.chip = {
	187	.nr_chips = 1,
	188	.partitions = migor_nand_flash_partitions,
	189	.nr_partitions = ARRAY_SIZE(migor_nand_flash_partitions),
	190	.chip_delay = 20,
	191	.part_probe_types = (const char *[]) { "cmdlinepart", NULL },
	192	},
	193	.ctrl = {
	194	.dev_ready = migor_nand_flash_ready,
	195	.cmd_ctrl = migor_nand_flash_cmd_ctl,
	196	},
	197	};
	198
	199	static struct resource migor_nand_flash_resources[] = {
	200	[0] = {
	201	.name = "NAND Flash",
	202	.start = 0x18000000,
	203	.end = 0x18ffffff,
	204	.flags = IORESOURCE_MEM,
	205	},
	206	};
	207
	208	static struct platform_device migor_nand_flash_device = {
	209	.name = "gen_nand",
	210	.resource = migor_nand_flash_resources,
	211	.num_resources = ARRAY_SIZE(migor_nand_flash_resources),
	212	.dev = {
	213	.platform_data = &migor_nand_flash_data,
	214	}
	215	};
	216
44432407 GL	217	const static struct fb_videomode migor_lcd_modes[] = {
	218	{
	219	#if defined(CONFIG_SH_MIGOR_RTA_WVGA)
	220	.name = "LB070WV1",
	221	.xres = 800,
	222	.yres = 480,
	223	.left_margin = 64,
	224	.right_margin = 16,
	225	.hsync_len = 120,
	226	.sync = 0,
	227	#elif defined(CONFIG_SH_MIGOR_QVGA)
	228	.name = "PH240320T",
	229	.xres = 320,
	230	.yres = 240,
	231	.left_margin = 0,
	232	.right_margin = 16,
	233	.hsync_len = 8,
	234	.sync = FB_SYNC_HOR_HIGH_ACT,
	235	#endif
	236	.upper_margin = 1,
	237	.lower_margin = 17,
	238	.vsync_len = 2,
	239	},
	240	};
	241
8b1285f1	242	static struct sh_mobile_lcdc_info sh_mobile_lcdc_info = {
44432407	243	#if defined(CONFIG_SH_MIGOR_RTA_WVGA)
8b1285f1 MD	244	.clock_source = LCDC_CLK_BUS,
	245	.ch[0] = {
	246	.chan = LCDC_CHAN_MAINLCD,
	247	.bpp = 16,
	248	.interface_type = RGB16,
	249	.clock_divider = 2,
44432407 GL	250	.lcd_cfg = migor_lcd_modes,
44432407 GL	251	.num_cfg = ARRAY_SIZE(migor_lcd_modes),
ce9c008c MD	252	.lcd_size_cfg = { /* 7.0 inch */
	253	.width = 152,
	254	.height = 91,
	255	},
8b1285f1	256	}
44432407	257	#elif defined(CONFIG_SH_MIGOR_QVGA)
8b1285f1 MD	258	.clock_source = LCDC_CLK_PERIPHERAL,
	259	.ch[0] = {
	260	.chan = LCDC_CHAN_MAINLCD,
	261	.bpp = 16,
	262	.interface_type = SYS16A,
	263	.clock_divider = 10,
44432407 GL	264	.lcd_cfg = migor_lcd_modes,
44432407 GL	265	.num_cfg = ARRAY_SIZE(migor_lcd_modes),
ce9c008c MD	266	.lcd_size_cfg = { /* 2.4 inch */
	267	.width = 49,
	268	.height = 37,
	269	},
8b1285f1 MD	270	.board_cfg = {
	271	.setup_sys = migor_lcd_qvga_setup,
	272	},
	273	.sys_bus_cfg = {
	274	.ldmt2r = 0x06000a09,
	275	.ldmt3r = 0x180e3418,
b5868e8c MD	276	/* set 1s delay to encourage fsync() */
b5868e8c MD	277	.deferred_io_msec = 1000,
8b1285f1 MD	278	},
	279	}
	280	#endif
	281	};
	282
	283	static struct resource migor_lcdc_resources[] = {
	284	[0] = {
	285	.name = "LCDC",
	286	.start = 0xfe940000, /* P4-only space */
a6f15ade	287	.end = 0xfe942fff,
8b1285f1 MD	288	.flags = IORESOURCE_MEM,
8b1285f1 MD	289	},
07905554 MD	290	[1] = {
	291	.start = 28,
	292	.flags = IORESOURCE_IRQ,
	293	},
8b1285f1 MD	294	};
	295
	296	static struct platform_device migor_lcdc_device = {
	297	.name = "sh_mobile_lcdc_fb",
	298	.num_resources = ARRAY_SIZE(migor_lcdc_resources),
	299	.resource = migor_lcdc_resources,
	300	.dev = {
	301	.platform_data = &sh_mobile_lcdc_info,
	302	},
2de63cf3 MD	303	.archdata = {
	304	.hwblk_id = HWBLK_LCDC,
	305	},
8b1285f1 MD	306	};
8b1285f1 MD	307
1765534c	308	static struct clk *camera_clk;
deae7b86	309	static DEFINE_MUTEX(camera_lock);
1765534c	310
deae7b86	311	static void camera_power_on(int is_tw)
1765534c	312	{
deae7b86 KM	313	mutex_lock(&camera_lock);
deae7b86 KM	314
22ee3ba6 MD	315	/* Use 10 MHz VIO_CKO instead of 24 MHz to work
	316	* around signal quality issues on Panel Board V2.1.
	317	*/
1765534c	318	camera_clk = clk_get(NULL, "video_clk");
22ee3ba6	319	clk_set_rate(camera_clk, 10000000);
1765534c MD	320	clk_enable(camera_clk); /* start VIO_CKO */
1765534c MD	321
91b6f3c5	322	/* use VIO_RST to take camera out of reset */
1765534c	323	mdelay(10);
deae7b86 KM	324	if (is_tw) {
	325	gpio_set_value(GPIO_PTT2, 0);
	326	gpio_set_value(GPIO_PTT0, 0);
	327	} else {
	328	gpio_set_value(GPIO_PTT0, 1);
	329	}
91b6f3c5	330	gpio_set_value(GPIO_PTT3, 0);
1765534c	331	mdelay(10);
91b6f3c5	332	gpio_set_value(GPIO_PTT3, 1);
4545bfa0	333	mdelay(10); /* wait to let chip come out of reset */
1765534c MD	334	}
	335
	336	static void camera_power_off(void)
	337	{
	338	clk_disable(camera_clk); /* stop VIO_CKO */
	339	clk_put(camera_clk);
	340
91b6f3c5	341	gpio_set_value(GPIO_PTT3, 0);
deae7b86	342	mutex_unlock(&camera_lock);
1765534c MD	343	}
1765534c MD	344
ff04ea40 KM	345	static int ov7725_power(struct device *dev, int mode)
	346	{
	347	if (mode)
deae7b86 KM	348	camera_power_on(0);
	349	else
	350	camera_power_off();
	351
	352	return 0;
	353	}
	354
	355	static int tw9910_power(struct device *dev, int mode)
	356	{
	357	if (mode)
	358	camera_power_on(1);
ff04ea40 KM	359	else
	360	camera_power_off();
	361
	362	return 0;
	363	}
	364
1765534c	365	static struct sh_mobile_ceu_info sh_mobile_ceu_info = {
64935056	366	.flags = SH_CEU_FLAG_USE_8BIT_BUS,
1765534c MD	367	};
	368
	369	static struct resource migor_ceu_resources[] = {
	370	[0] = {
	371	.name = "CEU",
	372	.start = 0xfe910000,
	373	.end = 0xfe91009f,
	374	.flags = IORESOURCE_MEM,
	375	},
	376	[1] = {
	377	.start = 52,
	378	.flags = IORESOURCE_IRQ,
	379	},
	380	[2] = {
	381	/* place holder for contiguous memory */
	382	},
	383	};
	384
	385	static struct platform_device migor_ceu_device = {
	386	.name = "sh_mobile_ceu",
a42b6dd6	387	.id = 0, /* "ceu0" clock */
1765534c MD	388	.num_resources = ARRAY_SIZE(migor_ceu_resources),
	389	.resource = migor_ceu_resources,
	390	.dev = {
	391	.platform_data = &sh_mobile_ceu_info,
	392	},
2de63cf3 MD	393	.archdata = {
	394	.hwblk_id = HWBLK_CEU,
	395	},
1765534c MD	396	};
1765534c MD	397
2e3fc56c MD	398	static struct resource sdhi_cn9_resources[] = {
	399	[0] = {
	400	.name = "SDHI",
	401	.start = 0x04ce0000,
	402	.end = 0x04ce01ff,
	403	.flags = IORESOURCE_MEM,
	404	},
	405	[1] = {
8d9adaba	406	.start = 100,
2e3fc56c MD	407	.flags = IORESOURCE_IRQ,
2e3fc56c MD	408	},
70e5c4f0 MD	409	};
70e5c4f0 MD	410
65a1b034 GL	411	static struct sh_mobile_sdhi_info sh7724_sdhi_data = {
	412	.dma_slave_tx = SHDMA_SLAVE_SDHI0_TX,
	413	.dma_slave_rx = SHDMA_SLAVE_SDHI0_RX,
464495e5	414	.tmio_caps = MMC_CAP_SDIO_IRQ,
65a1b034 GL	415	};
65a1b034 GL	416
2e3fc56c MD	417	static struct platform_device sdhi_cn9_device = {
	418	.name = "sh_mobile_sdhi",
	419	.num_resources = ARRAY_SIZE(sdhi_cn9_resources),
	420	.resource = sdhi_cn9_resources,
65a1b034 GL	421	.dev = {
	422	.platform_data = &sh7724_sdhi_data,
	423	},
2e3fc56c MD	424	.archdata = {
2e3fc56c MD	425	.hwblk_id = HWBLK_SDHI,
70e5c4f0 MD	426	},
	427	};
	428
1765534c	429	static struct i2c_board_info migor_i2c_devices[] = {
57795867	430	{
3760f736	431	I2C_BOARD_INFO("rs5c372b", 0x32),
57795867	432	},
67908abf MD	433	{
	434	I2C_BOARD_INFO("migor_ts", 0x51),
	435	.irq = 38, /* IRQ6 */
	436	},
920925f9 GL	437	{
	438	I2C_BOARD_INFO("wm8978", 0x1a),
	439	},
2cb582ca GL	440	};
	441
	442	static struct i2c_board_info migor_i2c_camera[] = {
ff04ea40 KM	443	{
ff04ea40 KM	444	I2C_BOARD_INFO("ov772x", 0x21),
ff04ea40	445	},
deae7b86 KM	446	{
deae7b86 KM	447	I2C_BOARD_INFO("tw9910", 0x45),
deae7b86	448	},
0c6111ec MD	449	};
0c6111ec MD	450
2cb582ca	451	static struct ov772x_camera_info ov7725_info = {
3675c750	452	.flags = OV772X_FLAG_8BIT,
0f448294 GL	453	};
	454
	455	static struct soc_camera_link ov7725_link = {
	456	.power = ov7725_power,
	457	.board_info = &migor_i2c_camera[0],
	458	.i2c_adapter_id = 0,
0f448294	459	.priv = &ov7725_info,
2cb582ca GL	460	};
	461
	462	static struct tw9910_video_info tw9910_info = {
	463	.buswidth = SOCAM_DATAWIDTH_8,
	464	.mpout = TW9910_MPO_FIELD,
0f448294 GL	465	};
	466
	467	static struct soc_camera_link tw9910_link = {
	468	.power = tw9910_power,
	469	.board_info = &migor_i2c_camera[1],
	470	.i2c_adapter_id = 0,
0f448294	471	.priv = &tw9910_info,
2cb582ca GL	472	};
	473
	474	static struct platform_device migor_camera[] = {
	475	{
	476	.name = "soc-camera-pdrv",
	477	.id = 0,
	478	.dev = {
0f448294	479	.platform_data = &ov7725_link,
2cb582ca GL	480	},
	481	}, {
	482	.name = "soc-camera-pdrv",
	483	.id = 1,
	484	.dev = {
0f448294	485	.platform_data = &tw9910_link,
2cb582ca GL	486	},
	487	},
	488	};
	489
	490	static struct platform_device *migor_devices[] __initdata = {
	491	&smc91x_eth_device,
	492	&sh_keysc_device,
	493	&migor_lcdc_device,
	494	&migor_ceu_device,
	495	&migor_nor_flash_device,
	496	&migor_nand_flash_device,
2e3fc56c	497	&sdhi_cn9_device,
2cb582ca GL	498	&migor_camera[0],
	499	&migor_camera[1],
	500	};
	501
13fa551b MD	502	extern char migor_sdram_enter_start;
	503	extern char migor_sdram_enter_end;
	504	extern char migor_sdram_leave_start;
	505	extern char migor_sdram_leave_end;
	506
70f784ec MD	507	static int __init migor_devices_setup(void)
70f784ec MD	508	{
13fa551b MD	509	/* register board specific self-refresh code */
	510	sh_mobile_register_self_refresh(SUSP_SH_STANDBY \| SUSP_SH_SF,
	511	&migor_sdram_enter_start,
	512	&migor_sdram_enter_end,
	513	&migor_sdram_leave_start,
	514	&migor_sdram_leave_end);
50840714 MD	515	/* Let D11 LED show STATUS0 */
	516	gpio_request(GPIO_FN_STATUS0, NULL);
	517
	518	/* Lit D12 LED show PDSTATUS */
	519	gpio_request(GPIO_FN_PDSTATUS, NULL);
91b6f3c5	520
a30c89ad	521	/* SMC91C111 - Enable IRQ0, Setup CS4 for 16-bit fast access */
91b6f3c5	522	gpio_request(GPIO_FN_IRQ0, NULL);
9d56dd3b PM	523	__raw_writel(0x00003400, BSC_CS4BCR);
9d56dd3b PM	524	__raw_writel(0x00110080, BSC_CS4WCR);
91b6f3c5 MD	525
91b6f3c5 MD	526	/* KEYSC */
91b6f3c5 MD	527	gpio_request(GPIO_FN_KEYOUT0, NULL);
	528	gpio_request(GPIO_FN_KEYOUT1, NULL);
	529	gpio_request(GPIO_FN_KEYOUT2, NULL);
	530	gpio_request(GPIO_FN_KEYOUT3, NULL);
	531	gpio_request(GPIO_FN_KEYOUT4_IN6, NULL);
	532	gpio_request(GPIO_FN_KEYIN1, NULL);
	533	gpio_request(GPIO_FN_KEYIN2, NULL);
	534	gpio_request(GPIO_FN_KEYIN3, NULL);
	535	gpio_request(GPIO_FN_KEYIN4, NULL);
	536	gpio_request(GPIO_FN_KEYOUT5_IN5, NULL);
	537
	538	/* NAND Flash */
	539	gpio_request(GPIO_FN_CS6A_CE2B, NULL);
9d56dd3b	540	__raw_writel((__raw_readl(BSC_CS6ABCR) & ~0x0600) \| 0x0200, BSC_CS6ABCR);
91b6f3c5 MD	541	gpio_request(GPIO_PTA1, NULL);
	542	gpio_direction_input(GPIO_PTA1);
	543
2e3fc56c MD	544	/* SDHI */
	545	gpio_request(GPIO_FN_SDHICD, NULL);
	546	gpio_request(GPIO_FN_SDHIWP, NULL);
	547	gpio_request(GPIO_FN_SDHID3, NULL);
	548	gpio_request(GPIO_FN_SDHID2, NULL);
	549	gpio_request(GPIO_FN_SDHID1, NULL);
	550	gpio_request(GPIO_FN_SDHID0, NULL);
	551	gpio_request(GPIO_FN_SDHICMD, NULL);
	552	gpio_request(GPIO_FN_SDHICLK, NULL);
	553
91b6f3c5 MD	554	/* Touch Panel */
	555	gpio_request(GPIO_FN_IRQ6, NULL);
	556
	557	/* LCD Panel */
91b6f3c5 MD	558	#ifdef CONFIG_SH_MIGOR_QVGA /* LCDC - QVGA - Enable SYS Interface signals */
	559	gpio_request(GPIO_FN_LCDD17, NULL);
	560	gpio_request(GPIO_FN_LCDD16, NULL);
	561	gpio_request(GPIO_FN_LCDD15, NULL);
	562	gpio_request(GPIO_FN_LCDD14, NULL);
	563	gpio_request(GPIO_FN_LCDD13, NULL);
	564	gpio_request(GPIO_FN_LCDD12, NULL);
	565	gpio_request(GPIO_FN_LCDD11, NULL);
	566	gpio_request(GPIO_FN_LCDD10, NULL);
	567	gpio_request(GPIO_FN_LCDD8, NULL);
	568	gpio_request(GPIO_FN_LCDD7, NULL);
	569	gpio_request(GPIO_FN_LCDD6, NULL);
	570	gpio_request(GPIO_FN_LCDD5, NULL);
	571	gpio_request(GPIO_FN_LCDD4, NULL);
	572	gpio_request(GPIO_FN_LCDD3, NULL);
	573	gpio_request(GPIO_FN_LCDD2, NULL);
	574	gpio_request(GPIO_FN_LCDD1, NULL);
	575	gpio_request(GPIO_FN_LCDRS, NULL);
	576	gpio_request(GPIO_FN_LCDCS, NULL);
	577	gpio_request(GPIO_FN_LCDRD, NULL);
	578	gpio_request(GPIO_FN_LCDWR, NULL);
	579	gpio_request(GPIO_PTH2, NULL); /* LCD_DON */
	580	gpio_direction_output(GPIO_PTH2, 1);
	581	#endif
	582	#ifdef CONFIG_SH_MIGOR_RTA_WVGA /* LCDC - WVGA - Enable RGB Interface signals */
	583	gpio_request(GPIO_FN_LCDD15, NULL);
	584	gpio_request(GPIO_FN_LCDD14, NULL);
	585	gpio_request(GPIO_FN_LCDD13, NULL);
	586	gpio_request(GPIO_FN_LCDD12, NULL);
	587	gpio_request(GPIO_FN_LCDD11, NULL);
	588	gpio_request(GPIO_FN_LCDD10, NULL);
	589	gpio_request(GPIO_FN_LCDD9, NULL);
	590	gpio_request(GPIO_FN_LCDD8, NULL);
	591	gpio_request(GPIO_FN_LCDD7, NULL);
	592	gpio_request(GPIO_FN_LCDD6, NULL);
	593	gpio_request(GPIO_FN_LCDD5, NULL);
	594	gpio_request(GPIO_FN_LCDD4, NULL);
	595	gpio_request(GPIO_FN_LCDD3, NULL);
	596	gpio_request(GPIO_FN_LCDD2, NULL);
	597	gpio_request(GPIO_FN_LCDD1, NULL);
	598	gpio_request(GPIO_FN_LCDD0, NULL);
	599	gpio_request(GPIO_FN_LCDLCLK, NULL);
	600	gpio_request(GPIO_FN_LCDDCK, NULL);
	601	gpio_request(GPIO_FN_LCDVEPWC, NULL);
	602	gpio_request(GPIO_FN_LCDVCPWC, NULL);
	603	gpio_request(GPIO_FN_LCDVSYN, NULL);
	604	gpio_request(GPIO_FN_LCDHSYN, NULL);
	605	gpio_request(GPIO_FN_LCDDISP, NULL);
	606	gpio_request(GPIO_FN_LCDDON, NULL);
	607	#endif
	608
	609	/* CEU */
91b6f3c5 MD	610	gpio_request(GPIO_FN_VIO_CLK2, NULL);
	611	gpio_request(GPIO_FN_VIO_VD2, NULL);
	612	gpio_request(GPIO_FN_VIO_HD2, NULL);
	613	gpio_request(GPIO_FN_VIO_FLD, NULL);
	614	gpio_request(GPIO_FN_VIO_CKO, NULL);
	615	gpio_request(GPIO_FN_VIO_D15, NULL);
	616	gpio_request(GPIO_FN_VIO_D14, NULL);
	617	gpio_request(GPIO_FN_VIO_D13, NULL);
	618	gpio_request(GPIO_FN_VIO_D12, NULL);
	619	gpio_request(GPIO_FN_VIO_D11, NULL);
	620	gpio_request(GPIO_FN_VIO_D10, NULL);
	621	gpio_request(GPIO_FN_VIO_D9, NULL);
	622	gpio_request(GPIO_FN_VIO_D8, NULL);
	623
	624	gpio_request(GPIO_PTT3, NULL); /* VIO_RST */
	625	gpio_direction_output(GPIO_PTT3, 0);
	626	gpio_request(GPIO_PTT2, NULL); /* TV_IN_EN */
	627	gpio_direction_output(GPIO_PTT2, 1);
	628	gpio_request(GPIO_PTT0, NULL); /* CAM_EN */
	629	#ifdef CONFIG_SH_MIGOR_RTA_WVGA
	630	gpio_direction_output(GPIO_PTT0, 0);
	631	#else
	632	gpio_direction_output(GPIO_PTT0, 1);
	633	#endif
9d56dd3b	634	__raw_writew(__raw_readw(PORT_MSELCRB) \| 0x2000, PORT_MSELCRB); /* D15->D8 */
1765534c MD	635
1765534c MD	636	platform_resource_setup_memory(&migor_ceu_device, "ceu", 4 << 20);
6c7d826c	637
920925f9 GL	638	/* SIU: Port B */
	639	gpio_request(GPIO_FN_SIUBOLR, NULL);
	640	gpio_request(GPIO_FN_SIUBOBT, NULL);
	641	gpio_request(GPIO_FN_SIUBISLD, NULL);
	642	gpio_request(GPIO_FN_SIUBOSLD, NULL);
	643	gpio_request(GPIO_FN_SIUMCKB, NULL);
	644
	645	/*
	646	* The original driver sets SIUB OLR/OBT, ILR/IBT, and SIUA OLR/OBT to
	647	* output. Need only SIUB, set to output for master mode (table 34.2)
	648	*/
7d0b0a44	649	__raw_writew(__raw_readw(PORT_MSELCRA) \| 1, PORT_MSELCRA);
920925f9	650
0c6111ec MD	651	i2c_register_board_info(0, migor_i2c_devices,
0c6111ec MD	652	ARRAY_SIZE(migor_i2c_devices));
91b6f3c5	653
70f784ec MD	654	return platform_add_devices(migor_devices, ARRAY_SIZE(migor_devices));
70f784ec MD	655	}
ba3a1701	656	arch_initcall(migor_devices_setup);
0ec80fdd MD	657
	658	/* Return the board specific boot mode pin configuration */
	659	static int migor_mode_pins(void)
	660	{
	661	/* MD0=1, MD1=1, MD2=0: Clock Mode 3
	662	* MD3=0: 16-bit Area0 Bus Width
	663	* MD5=1: Little Endian
	664	* TSTMD=1, MD8=0: Test Mode Disabled
	665	*/
	666	return MODE_PIN0 \| MODE_PIN1 \| MODE_PIN5;
	667	}
	668
	669	/*
	670	* The Machine Vector
	671	*/
	672	static struct sh_machine_vector mv_migor __initmv = {
	673	.mv_name = "Migo-R",
	674	.mv_mode_pins = migor_mode_pins,
	675	};