[linux-2.6-block.git] / arch / sh / boards / mach-migor / setup.c

// SPDX-License-Identifier: GPL-2.0
/*
 * Renesas System Solutions Asia Pte. Ltd - Migo-R
 *
 * Copyright (C) 2008 Magnus Damm
 */
#include <linux/clkdev.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/interrupt.h>
#include <linux/input.h>
#include <linux/input/sh_keysc.h>
#include <linux/memblock.h>
#include <linux/mmc/host.h>
#include <linux/mtd/physmap.h>
#include <linux/mfd/tmio.h>
#include <linux/mtd/platnand.h>
#include <linux/i2c.h>
#include <linux/regulator/fixed.h>
#include <linux/regulator/machine.h>
#include <linux/smc91x.h>
#include <linux/delay.h>
#include <linux/clk.h>
#include <linux/gpio.h>
#include <linux/gpio/machine.h>
#include <linux/videodev2.h>
#include <linux/sh_intc.h>
#include <video/sh_mobile_lcdc.h>
#include <media/drv-intf/renesas-ceu.h>
#include <media/i2c/ov772x.h>
#include <media/i2c/tw9910.h>
#include <asm/clock.h>
#include <asm/machvec.h>
#include <asm/io.h>
#include <asm/suspend.h>
#include <mach/migor.h>
#include <cpu/sh7722.h>

/* Address     IRQ  Size  Bus  Description
 * 0x00000000       64MB  16   NOR Flash (SP29PL256N)
 * 0x0c000000       64MB  64   SDRAM (2xK4M563233G)
 * 0x10000000  IRQ0       16   Ethernet (SMC91C111)
 * 0x14000000  IRQ4       16   USB 2.0 Host Controller (M66596)
 * 0x18000000       8GB    8   NAND Flash (K9K8G08U0A)
 */

#define CEU_BUFFER_MEMORY_SIZE		(4 << 20)
static phys_addr_t ceu_dma_membase;

static struct smc91x_platdata smc91x_info = {
	.flags = SMC91X_USE_16BIT | SMC91X_NOWAIT,
};

static struct resource smc91x_eth_resources[] = {
	[0] = {
		.name   = "SMC91C111" ,
		.start  = 0x10000300,
		.end    = 0x1000030f,
		.flags  = IORESOURCE_MEM,
	},
	[1] = {
		.start  = evt2irq(0x600), /* IRQ0 */
		.flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
	},
};

static struct platform_device smc91x_eth_device = {
	.name           = "smc91x",
	.num_resources  = ARRAY_SIZE(smc91x_eth_resources),
	.resource       = smc91x_eth_resources,
	.dev	= {
		.platform_data	= &smc91x_info,
	},
};

static struct sh_keysc_info sh_keysc_info = {
	.mode = SH_KEYSC_MODE_2, /* KEYOUT0->4, KEYIN1->5 */
	.scan_timing = 3,
	.delay = 5,
	.keycodes = {
		0, KEY_UP, KEY_DOWN, KEY_LEFT, KEY_RIGHT, KEY_ENTER,
		0, KEY_F, KEY_C, KEY_D,	KEY_H, KEY_1,
		0, KEY_2, KEY_3, KEY_4,	KEY_5, KEY_6,
		0, KEY_7, KEY_8, KEY_9, KEY_S, KEY_0,
		0, KEY_P, KEY_STOP, KEY_REWIND, KEY_PLAY, KEY_FASTFORWARD,
	},
};

static struct resource sh_keysc_resources[] = {
	[0] = {
		.start  = 0x044b0000,
		.end    = 0x044b000f,
		.flags  = IORESOURCE_MEM,
	},
	[1] = {
		.start  = evt2irq(0xbe0),
		.flags  = IORESOURCE_IRQ,
	},
};

static struct platform_device sh_keysc_device = {
	.name           = "sh_keysc",
	.id             = 0, /* "keysc0" clock */
	.num_resources  = ARRAY_SIZE(sh_keysc_resources),
	.resource       = sh_keysc_resources,
	.dev	= {
		.platform_data	= &sh_keysc_info,
	},
};

static struct mtd_partition migor_nor_flash_partitions[] =
{
	{
		.name = "uboot",
		.offset = 0,
		.size = (1 * 1024 * 1024),
		.mask_flags = MTD_WRITEABLE,	/* Read-only */
	},
	{
		.name = "rootfs",
		.offset = MTDPART_OFS_APPEND,
		.size = (15 * 1024 * 1024),
	},
	{
		.name = "other",
		.offset = MTDPART_OFS_APPEND,
		.size = MTDPART_SIZ_FULL,
	},
};

static struct physmap_flash_data migor_nor_flash_data = {
	.width		= 2,
	.parts		= migor_nor_flash_partitions,
	.nr_parts	= ARRAY_SIZE(migor_nor_flash_partitions),
};

static struct resource migor_nor_flash_resources[] = {
	[0] = {
		.name		= "NOR Flash",
		.start		= 0x00000000,
		.end		= 0x03ffffff,
		.flags		= IORESOURCE_MEM,
	}
};

static struct platform_device migor_nor_flash_device = {
	.name		= "physmap-flash",
	.resource	= migor_nor_flash_resources,
	.num_resources	= ARRAY_SIZE(migor_nor_flash_resources),
	.dev		= {
		.platform_data = &migor_nor_flash_data,
	},
};

static struct mtd_partition migor_nand_flash_partitions[] = {
	{
		.name		= "nanddata1",
		.offset		= 0x0,
		.size		= 512 * 1024 * 1024,
	},
	{
		.name		= "nanddata2",
		.offset		= MTDPART_OFS_APPEND,
		.size		= 512 * 1024 * 1024,
	},
};

static void migor_nand_flash_cmd_ctl(struct nand_chip *chip, int cmd,
				     unsigned int ctrl)
{
	if (cmd == NAND_CMD_NONE)
		return;

	if (ctrl & NAND_CLE)
		writeb(cmd, chip->legacy.IO_ADDR_W + 0x00400000);
	else if (ctrl & NAND_ALE)
		writeb(cmd, chip->legacy.IO_ADDR_W + 0x00800000);
	else
		writeb(cmd, chip->legacy.IO_ADDR_W);
}

static int migor_nand_flash_ready(struct nand_chip *chip)
{
	return gpio_get_value(GPIO_PTA1); /* NAND_RBn */
}

static struct platform_nand_data migor_nand_flash_data = {
	.chip = {
		.nr_chips = 1,
		.partitions = migor_nand_flash_partitions,
		.nr_partitions = ARRAY_SIZE(migor_nand_flash_partitions),
		.chip_delay = 20,
	},
	.ctrl = {
		.dev_ready = migor_nand_flash_ready,
		.cmd_ctrl = migor_nand_flash_cmd_ctl,
	},
};

static struct resource migor_nand_flash_resources[] = {
	[0] = {
		.name		= "NAND Flash",
		.start		= 0x18000000,
		.end		= 0x18ffffff,
		.flags		= IORESOURCE_MEM,
	},
};

static struct platform_device migor_nand_flash_device = {
	.name		= "gen_nand",
	.resource	= migor_nand_flash_resources,
	.num_resources	= ARRAY_SIZE(migor_nand_flash_resources),
	.dev		= {
		.platform_data = &migor_nand_flash_data,
	}
};

static const struct fb_videomode migor_lcd_modes[] = {
	{
#if defined(CONFIG_SH_MIGOR_RTA_WVGA)
		.name = "LB070WV1",
		.xres = 800,
		.yres = 480,
		.left_margin = 64,
		.right_margin = 16,
		.hsync_len = 120,
		.sync = 0,
#elif defined(CONFIG_SH_MIGOR_QVGA)
		.name = "PH240320T",
		.xres = 320,
		.yres = 240,
		.left_margin = 0,
		.right_margin = 16,
		.hsync_len = 8,
		.sync = FB_SYNC_HOR_HIGH_ACT,
#endif
		.upper_margin = 1,
		.lower_margin = 17,
		.vsync_len = 2,
	},
};

static struct sh_mobile_lcdc_info sh_mobile_lcdc_info = {
#if defined(CONFIG_SH_MIGOR_RTA_WVGA)
	.clock_source = LCDC_CLK_BUS,
	.ch[0] = {
		.chan = LCDC_CHAN_MAINLCD,
		.fourcc = V4L2_PIX_FMT_RGB565,
		.interface_type = RGB16,
		.clock_divider = 2,
		.lcd_modes = migor_lcd_modes,
		.num_modes = ARRAY_SIZE(migor_lcd_modes),
		.panel_cfg = { /* 7.0 inch */
			.width = 152,
			.height = 91,
		},
	}
#elif defined(CONFIG_SH_MIGOR_QVGA)
	.clock_source = LCDC_CLK_PERIPHERAL,
	.ch[0] = {
		.chan = LCDC_CHAN_MAINLCD,
		.fourcc = V4L2_PIX_FMT_RGB565,
		.interface_type = SYS16A,
		.clock_divider = 10,
		.lcd_modes = migor_lcd_modes,
		.num_modes = ARRAY_SIZE(migor_lcd_modes),
		.panel_cfg = {
			.width = 49,	/* 2.4 inch */
			.height = 37,
			.setup_sys = migor_lcd_qvga_setup,
		},
		.sys_bus_cfg = {
			.ldmt2r = 0x06000a09,
			.ldmt3r = 0x180e3418,
			/* set 1s delay to encourage fsync() */
			.deferred_io_msec = 1000,
		},
	}
#endif
};

static struct resource migor_lcdc_resources[] = {
	[0] = {
		.name	= "LCDC",
		.start	= 0xfe940000, /* P4-only space */
		.end	= 0xfe942fff,
		.flags	= IORESOURCE_MEM,
	},
	[1] = {
		.start	= evt2irq(0x580),
		.flags	= IORESOURCE_IRQ,
	},
};

static struct platform_device migor_lcdc_device = {
	.name		= "sh_mobile_lcdc_fb",
	.num_resources	= ARRAY_SIZE(migor_lcdc_resources),
	.resource	= migor_lcdc_resources,
	.dev	= {
		.platform_data	= &sh_mobile_lcdc_info,
	},
};

static struct ceu_platform_data ceu_pdata = {
	.num_subdevs			= 2,
	.subdevs = {
		{ /* [0] = ov772x */
			.flags		= 0,
			.bus_width	= 8,
			.bus_shift	= 0,
			.i2c_adapter_id	= 0,
			.i2c_address	= 0x21,
		},
		{ /* [1] = tw9910 */
			.flags		= 0,
			.bus_width	= 8,
			.bus_shift	= 0,
			.i2c_adapter_id	= 0,
			.i2c_address	= 0x45,
		},
	},
};

static struct resource migor_ceu_resources[] = {
	[0] = {
		.name	= "CEU",
		.start	= 0xfe910000,
		.end	= 0xfe91009f,
		.flags	= IORESOURCE_MEM,
	},
	[1] = {
		.start  = evt2irq(0x880),
		.flags  = IORESOURCE_IRQ,
	},
};

static struct platform_device migor_ceu_device = {
	.name		= "renesas-ceu",
	.id             = 0, /* ceu.0 */
	.num_resources	= ARRAY_SIZE(migor_ceu_resources),
	.resource	= migor_ceu_resources,
	.dev	= {
		.platform_data	= &ceu_pdata,
	},
};

/* Powerdown/reset gpios for CEU image sensors */
static struct gpiod_lookup_table ov7725_gpios = {
	.dev_id		= "0-0021",
	.table		= {
		GPIO_LOOKUP("sh7722_pfc", GPIO_PTT0, "powerdown",
			    GPIO_ACTIVE_HIGH),
		GPIO_LOOKUP("sh7722_pfc", GPIO_PTT3, "reset", GPIO_ACTIVE_LOW),
	},
};

static struct gpiod_lookup_table tw9910_gpios = {
	.dev_id		= "0-0045",
	.table		= {
		GPIO_LOOKUP("sh7722_pfc", GPIO_PTT2, "pdn", GPIO_ACTIVE_LOW),
		GPIO_LOOKUP("sh7722_pfc", GPIO_PTT3, "rstb", GPIO_ACTIVE_LOW),
	},
};

/* Fixed 3.3V regulator to be used by SDHI0 */
static struct regulator_consumer_supply fixed3v3_power_consumers[] =
{
	REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi.0"),
	REGULATOR_SUPPLY("vqmmc", "sh_mobile_sdhi.0"),
};

static struct resource sdhi_cn9_resources[] = {
	[0] = {
		.name	= "SDHI",
		.start	= 0x04ce0000,
		.end	= 0x04ce00ff,
		.flags	= IORESOURCE_MEM,
	},
	[1] = {
		.start	= evt2irq(0xe80),
		.flags  = IORESOURCE_IRQ,
	},
};

static struct tmio_mmc_data sh7724_sdhi_data = {
	.chan_priv_tx	= (void *)SHDMA_SLAVE_SDHI0_TX,
	.chan_priv_rx	= (void *)SHDMA_SLAVE_SDHI0_RX,
	.capabilities	= MMC_CAP_SDIO_IRQ,
};

static struct platform_device sdhi_cn9_device = {
	.name		= "sh_mobile_sdhi",
	.num_resources	= ARRAY_SIZE(sdhi_cn9_resources),
	.resource	= sdhi_cn9_resources,
	.dev = {
		.platform_data	= &sh7724_sdhi_data,
	},
};

static struct ov772x_camera_info ov7725_info = {
	.flags		= 0,
};

static struct tw9910_video_info tw9910_info = {
	.buswidth       = 8,
	.mpout          = TW9910_MPO_FIELD,
};

static struct i2c_board_info migor_i2c_devices[] = {
	{
		I2C_BOARD_INFO("rs5c372b", 0x32),
	},
	{
		I2C_BOARD_INFO("migor_ts", 0x51),
		.irq = evt2irq(0x6c0), /* IRQ6 */
	},
	{
		I2C_BOARD_INFO("wm8978", 0x1a),
	},
	{
		I2C_BOARD_INFO("ov772x", 0x21),
		.platform_data = &ov7725_info,
	},
	{
		I2C_BOARD_INFO("tw9910", 0x45),
		.platform_data = &tw9910_info,
	},
};

static struct platform_device *migor_devices[] __initdata = {
	&smc91x_eth_device,
	&sh_keysc_device,
	&migor_lcdc_device,
	&migor_nor_flash_device,
	&migor_nand_flash_device,
	&sdhi_cn9_device,
};

extern char migor_sdram_enter_start;
extern char migor_sdram_enter_end;
extern char migor_sdram_leave_start;
extern char migor_sdram_leave_end;

static int __init migor_devices_setup(void)
{
	struct clk *video_clk;

	/* register board specific self-refresh code */
	sh_mobile_register_self_refresh(SUSP_SH_STANDBY | SUSP_SH_SF,
					&migor_sdram_enter_start,
					&migor_sdram_enter_end,
					&migor_sdram_leave_start,
					&migor_sdram_leave_end);

	regulator_register_always_on(0, "fixed-3.3V", fixed3v3_power_consumers,
				     ARRAY_SIZE(fixed3v3_power_consumers), 3300000);

	/* Let D11 LED show STATUS0 */
	gpio_request(GPIO_FN_STATUS0, NULL);

	/* Lit D12 LED show PDSTATUS */
	gpio_request(GPIO_FN_PDSTATUS, NULL);

	/* SMC91C111 - Enable IRQ0, Setup CS4 for 16-bit fast access */
	gpio_request(GPIO_FN_IRQ0, NULL);
	__raw_writel(0x00003400, BSC_CS4BCR);
	__raw_writel(0x00110080, BSC_CS4WCR);

	/* KEYSC */
	gpio_request(GPIO_FN_KEYOUT0, NULL);
	gpio_request(GPIO_FN_KEYOUT1, NULL);
	gpio_request(GPIO_FN_KEYOUT2, NULL);
	gpio_request(GPIO_FN_KEYOUT3, NULL);
	gpio_request(GPIO_FN_KEYOUT4_IN6, NULL);
	gpio_request(GPIO_FN_KEYIN1, NULL);
	gpio_request(GPIO_FN_KEYIN2, NULL);
	gpio_request(GPIO_FN_KEYIN3, NULL);
	gpio_request(GPIO_FN_KEYIN4, NULL);
	gpio_request(GPIO_FN_KEYOUT5_IN5, NULL);

	/* NAND Flash */
	gpio_request(GPIO_FN_CS6A_CE2B, NULL);
	__raw_writel((__raw_readl(BSC_CS6ABCR) & ~0x0600) | 0x0200, BSC_CS6ABCR);
	gpio_request(GPIO_PTA1, NULL);
	gpio_direction_input(GPIO_PTA1);

	/* SDHI */
	gpio_request(GPIO_FN_SDHICD, NULL);
	gpio_request(GPIO_FN_SDHIWP, NULL);
	gpio_request(GPIO_FN_SDHID3, NULL);
	gpio_request(GPIO_FN_SDHID2, NULL);
	gpio_request(GPIO_FN_SDHID1, NULL);
	gpio_request(GPIO_FN_SDHID0, NULL);
	gpio_request(GPIO_FN_SDHICMD, NULL);
	gpio_request(GPIO_FN_SDHICLK, NULL);

	/* Touch Panel */
	gpio_request(GPIO_FN_IRQ6, NULL);

	/* LCD Panel */
#ifdef CONFIG_SH_MIGOR_QVGA /* LCDC - QVGA - Enable SYS Interface signals */
	gpio_request(GPIO_FN_LCDD17, NULL);
	gpio_request(GPIO_FN_LCDD16, NULL);
	gpio_request(GPIO_FN_LCDD15, NULL);
	gpio_request(GPIO_FN_LCDD14, NULL);
	gpio_request(GPIO_FN_LCDD13, NULL);
	gpio_request(GPIO_FN_LCDD12, NULL);
	gpio_request(GPIO_FN_LCDD11, NULL);
	gpio_request(GPIO_FN_LCDD10, NULL);
	gpio_request(GPIO_FN_LCDD8, NULL);
	gpio_request(GPIO_FN_LCDD7, NULL);
	gpio_request(GPIO_FN_LCDD6, NULL);
	gpio_request(GPIO_FN_LCDD5, NULL);
	gpio_request(GPIO_FN_LCDD4, NULL);
	gpio_request(GPIO_FN_LCDD3, NULL);
	gpio_request(GPIO_FN_LCDD2, NULL);
	gpio_request(GPIO_FN_LCDD1, NULL);
	gpio_request(GPIO_FN_LCDRS, NULL);
	gpio_request(GPIO_FN_LCDCS, NULL);
	gpio_request(GPIO_FN_LCDRD, NULL);
	gpio_request(GPIO_FN_LCDWR, NULL);
	gpio_request(GPIO_PTH2, NULL); /* LCD_DON */
	gpio_direction_output(GPIO_PTH2, 1);
#endif
#ifdef CONFIG_SH_MIGOR_RTA_WVGA /* LCDC - WVGA - Enable RGB Interface signals */
	gpio_request(GPIO_FN_LCDD15, NULL);
	gpio_request(GPIO_FN_LCDD14, NULL);
	gpio_request(GPIO_FN_LCDD13, NULL);
	gpio_request(GPIO_FN_LCDD12, NULL);
	gpio_request(GPIO_FN_LCDD11, NULL);
	gpio_request(GPIO_FN_LCDD10, NULL);
	gpio_request(GPIO_FN_LCDD9, NULL);
	gpio_request(GPIO_FN_LCDD8, NULL);
	gpio_request(GPIO_FN_LCDD7, NULL);
	gpio_request(GPIO_FN_LCDD6, NULL);
	gpio_request(GPIO_FN_LCDD5, NULL);
	gpio_request(GPIO_FN_LCDD4, NULL);
	gpio_request(GPIO_FN_LCDD3, NULL);
	gpio_request(GPIO_FN_LCDD2, NULL);
	gpio_request(GPIO_FN_LCDD1, NULL);
	gpio_request(GPIO_FN_LCDD0, NULL);
	gpio_request(GPIO_FN_LCDLCLK, NULL);
	gpio_request(GPIO_FN_LCDDCK, NULL);
	gpio_request(GPIO_FN_LCDVEPWC, NULL);
	gpio_request(GPIO_FN_LCDVCPWC, NULL);
	gpio_request(GPIO_FN_LCDVSYN, NULL);
	gpio_request(GPIO_FN_LCDHSYN, NULL);
	gpio_request(GPIO_FN_LCDDISP, NULL);
	gpio_request(GPIO_FN_LCDDON, NULL);
#endif

	/* CEU */
	gpio_request(GPIO_FN_VIO_CLK2, NULL);
	gpio_request(GPIO_FN_VIO_VD2, NULL);
	gpio_request(GPIO_FN_VIO_HD2, NULL);
	gpio_request(GPIO_FN_VIO_FLD, NULL);
	gpio_request(GPIO_FN_VIO_CKO, NULL);
	gpio_request(GPIO_FN_VIO_D15, NULL);
	gpio_request(GPIO_FN_VIO_D14, NULL);
	gpio_request(GPIO_FN_VIO_D13, NULL);
	gpio_request(GPIO_FN_VIO_D12, NULL);
	gpio_request(GPIO_FN_VIO_D11, NULL);
	gpio_request(GPIO_FN_VIO_D10, NULL);
	gpio_request(GPIO_FN_VIO_D9, NULL);
	gpio_request(GPIO_FN_VIO_D8, NULL);

	__raw_writew(__raw_readw(PORT_MSELCRB) | 0x2000, PORT_MSELCRB); /* D15->D8 */

	/* SIU: Port B */
	gpio_request(GPIO_FN_SIUBOLR, NULL);
	gpio_request(GPIO_FN_SIUBOBT, NULL);
	gpio_request(GPIO_FN_SIUBISLD, NULL);
	gpio_request(GPIO_FN_SIUBOSLD, NULL);
	gpio_request(GPIO_FN_SIUMCKB, NULL);

	/*
	 * The original driver sets SIUB OLR/OBT, ILR/IBT, and SIUA OLR/OBT to
	 * output. Need only SIUB, set to output for master mode (table 34.2)
	 */
	__raw_writew(__raw_readw(PORT_MSELCRA) | 1, PORT_MSELCRA);

	 /*
	  * Use 10 MHz VIO_CKO instead of 24 MHz to work around signal quality
	  * issues on Panel Board V2.1.
	  */
	video_clk = clk_get(NULL, "video_clk");
	if (!IS_ERR(video_clk)) {
		clk_set_rate(video_clk, clk_round_rate(video_clk, 10000000));
		clk_put(video_clk);
	}

	/* Add a clock alias for ov7725 xclk source. */
	clk_add_alias(NULL, "0-0021", "video_clk", NULL);

	/* Register GPIOs for video sources. */
	gpiod_add_lookup_table(&ov7725_gpios);
	gpiod_add_lookup_table(&tw9910_gpios);

	i2c_register_board_info(0, migor_i2c_devices,
				ARRAY_SIZE(migor_i2c_devices));

	/* Initialize CEU platform device separately to map memory first */
	device_initialize(&migor_ceu_device.dev);
	arch_setup_pdev_archdata(&migor_ceu_device);
	dma_declare_coherent_memory(&migor_ceu_device.dev,
				    ceu_dma_membase, ceu_dma_membase,
				    ceu_dma_membase + CEU_BUFFER_MEMORY_SIZE - 1,
				    DMA_MEMORY_EXCLUSIVE);

	platform_device_add(&migor_ceu_device);

	return platform_add_devices(migor_devices, ARRAY_SIZE(migor_devices));
}
arch_initcall(migor_devices_setup);

/* Return the board specific boot mode pin configuration */
static int migor_mode_pins(void)
{
	/* MD0=1, MD1=1, MD2=0: Clock Mode 3
	 * MD3=0: 16-bit Area0 Bus Width
	 * MD5=1: Little Endian
	 * TSTMD=1, MD8=0: Test Mode Disabled
	 */
	return MODE_PIN0 | MODE_PIN1 | MODE_PIN5;
}

/* Reserve a portion of memory for CEU buffers */
static void __init migor_mv_mem_reserve(void)
{
	phys_addr_t phys;
	phys_addr_t size = CEU_BUFFER_MEMORY_SIZE;

	phys = memblock_alloc_base(size, PAGE_SIZE, MEMBLOCK_ALLOC_ANYWHERE);
	memblock_free(phys, size);
	memblock_remove(phys, size);

	ceu_dma_membase = phys;
}

/*
 * The Machine Vector
 */
static struct sh_machine_vector mv_migor __initmv = {
	.mv_name		= "Migo-R",
	.mv_mode_pins		= migor_mode_pins,
	.mv_mem_reserve		= migor_mv_mem_reserve,
};
Commit	Line	Data
186c446f	1	// SPDX-License-Identifier: GPL-2.0
70f784ec MD	2	/*
	3	* Renesas System Solutions Asia Pte. Ltd - Migo-R
	4	*
	5	* Copyright (C) 2008 Magnus Damm
70f784ec	6	*/
186c446f	7	#include <linux/clkdev.h>
70f784ec MD	8	#include <linux/init.h>
	9	#include <linux/platform_device.h>
	10	#include <linux/interrupt.h>
92cfeb61	11	#include <linux/input.h>
fc1d003d	12	#include <linux/input/sh_keysc.h>
186c446f	13	#include <linux/memblock.h>
464495e5	14	#include <linux/mmc/host.h>
b8808786	15	#include <linux/mtd/physmap.h>
84f11d5b	16	#include <linux/mfd/tmio.h>
c7921bb3	17	#include <linux/mtd/platnand.h>
0c6111ec	18	#include <linux/i2c.h>
48aff643 GL	19	#include <linux/regulator/fixed.h>
48aff643 GL	20	#include <linux/regulator/machine.h>
8a3ee0fc	21	#include <linux/smc91x.h>
1765534c MD	22	#include <linux/delay.h>
1765534c MD	23	#include <linux/clk.h>
91b6f3c5	24	#include <linux/gpio.h>
186c446f	25	#include <linux/gpio/machine.h>
a1ad8033	26	#include <linux/videodev2.h>
26819fcb	27	#include <linux/sh_intc.h>
70e5c4f0	28	#include <video/sh_mobile_lcdc.h>
186c446f	29	#include <media/drv-intf/renesas-ceu.h>
b5dcee22	30	#include <media/i2c/ov772x.h>
b5dcee22	31	#include <media/i2c/tw9910.h>
6c7d826c	32	#include <asm/clock.h>
70f784ec MD	33	#include <asm/machvec.h>
70f784ec MD	34	#include <asm/io.h>
13fa551b	35	#include <asm/suspend.h>
7639a454	36	#include <mach/migor.h>
f7275650	37	#include <cpu/sh7722.h>
70f784ec MD	38
	39	/* Address IRQ Size Bus Description
	40	* 0x00000000 64MB 16 NOR Flash (SP29PL256N)
	41	* 0x0c000000 64MB 64 SDRAM (2xK4M563233G)
	42	* 0x10000000 IRQ0 16 Ethernet (SMC91C111)
	43	* 0x14000000 IRQ4 16 USB 2.0 Host Controller (M66596)
	44	* 0x18000000 8GB 8 NAND Flash (K9K8G08U0A)
	45	*/
	46
186c446f JM	47	#define CEU_BUFFER_MEMORY_SIZE (4 << 20)
	48	static phys_addr_t ceu_dma_membase;
	49
8a3ee0fc	50	static struct smc91x_platdata smc91x_info = {
a30c89ad	51	.flags = SMC91X_USE_16BIT \| SMC91X_NOWAIT,
8a3ee0fc MD	52	};
8a3ee0fc MD	53
70f784ec MD	54	static struct resource smc91x_eth_resources[] = {
70f784ec MD	55	[0] = {
b026a23c MD	56	.name = "SMC91C111" ,
	57	.start = 0x10000300,
	58	.end = 0x1000030f,
70f784ec MD	59	.flags = IORESOURCE_MEM,
	60	},
	61	[1] = {
26819fcb	62	.start = evt2irq(0x600), /* IRQ0 */
d280eadc	63	.flags = IORESOURCE_IRQ \| IORESOURCE_IRQ_HIGHLEVEL,
70f784ec MD	64	},
	65	};
	66
	67	static struct platform_device smc91x_eth_device = {
	68	.name = "smc91x",
	69	.num_resources = ARRAY_SIZE(smc91x_eth_resources),
	70	.resource = smc91x_eth_resources,
8a3ee0fc MD	71	.dev = {
	72	.platform_data = &smc91x_info,
	73	},
70f784ec MD	74	};
70f784ec MD	75
92cfeb61 MD	76	static struct sh_keysc_info sh_keysc_info = {
	77	.mode = SH_KEYSC_MODE_2, /* KEYOUT0->4, KEYIN1->5 */
	78	.scan_timing = 3,
	79	.delay = 5,
	80	.keycodes = {
	81	0, KEY_UP, KEY_DOWN, KEY_LEFT, KEY_RIGHT, KEY_ENTER,
	82	0, KEY_F, KEY_C, KEY_D, KEY_H, KEY_1,
	83	0, KEY_2, KEY_3, KEY_4, KEY_5, KEY_6,
	84	0, KEY_7, KEY_8, KEY_9, KEY_S, KEY_0,
	85	0, KEY_P, KEY_STOP, KEY_REWIND, KEY_PLAY, KEY_FASTFORWARD,
	86	},
	87	};
	88
	89	static struct resource sh_keysc_resources[] = {
	90	[0] = {
	91	.start = 0x044b0000,
	92	.end = 0x044b000f,
	93	.flags = IORESOURCE_MEM,
	94	},
	95	[1] = {
26819fcb	96	.start = evt2irq(0xbe0),
92cfeb61 MD	97	.flags = IORESOURCE_IRQ,
	98	},
	99	};
	100
	101	static struct platform_device sh_keysc_device = {
	102	.name = "sh_keysc",
090d951b	103	.id = 0, /* "keysc0" clock */
92cfeb61 MD	104	.num_resources = ARRAY_SIZE(sh_keysc_resources),
	105	.resource = sh_keysc_resources,
	106	.dev = {
	107	.platform_data = &sh_keysc_info,
	108	},
	109	};
	110
b8808786 MD	111	static struct mtd_partition migor_nor_flash_partitions[] =
	112	{
	113	{
	114	.name = "uboot",
	115	.offset = 0,
	116	.size = (1 * 1024 * 1024),
	117	.mask_flags = MTD_WRITEABLE, /* Read-only */
	118	},
	119	{
	120	.name = "rootfs",
	121	.offset = MTDPART_OFS_APPEND,
	122	.size = (15 * 1024 * 1024),
	123	},
	124	{
	125	.name = "other",
	126	.offset = MTDPART_OFS_APPEND,
	127	.size = MTDPART_SIZ_FULL,
	128	},
	129	};
	130
	131	static struct physmap_flash_data migor_nor_flash_data = {
	132	.width = 2,
	133	.parts = migor_nor_flash_partitions,
	134	.nr_parts = ARRAY_SIZE(migor_nor_flash_partitions),
	135	};
	136
	137	static struct resource migor_nor_flash_resources[] = {
	138	[0] = {
	139	.name = "NOR Flash",
	140	.start = 0x00000000,
	141	.end = 0x03ffffff,
	142	.flags = IORESOURCE_MEM,
	143	}
	144	};
	145
	146	static struct platform_device migor_nor_flash_device = {
	147	.name = "physmap-flash",
	148	.resource = migor_nor_flash_resources,
	149	.num_resources = ARRAY_SIZE(migor_nor_flash_resources),
	150	.dev = {
	151	.platform_data = &migor_nor_flash_data,
	152	},
	153	};
	154
3c803a9a MD	155	static struct mtd_partition migor_nand_flash_partitions[] = {
	156	{
	157	.name = "nanddata1",
	158	.offset = 0x0,
	159	.size = 512 * 1024 * 1024,
	160	},
	161	{
	162	.name = "nanddata2",
	163	.offset = MTDPART_OFS_APPEND,
	164	.size = 512 * 1024 * 1024,
	165	},
	166	};
	167
47bd59e5	168	static void migor_nand_flash_cmd_ctl(struct nand_chip *chip, int cmd,
3c803a9a MD	169	unsigned int ctrl)
3c803a9a MD	170	{
3c803a9a MD	171	if (cmd == NAND_CMD_NONE)
	172	return;
	173
	174	if (ctrl & NAND_CLE)
82fc5099	175	writeb(cmd, chip->legacy.IO_ADDR_W + 0x00400000);
3c803a9a	176	else if (ctrl & NAND_ALE)
82fc5099	177	writeb(cmd, chip->legacy.IO_ADDR_W + 0x00800000);
3c803a9a	178	else
82fc5099	179	writeb(cmd, chip->legacy.IO_ADDR_W);
3c803a9a MD	180	}
3c803a9a MD	181
47bd59e5	182	static int migor_nand_flash_ready(struct nand_chip *chip)
3c803a9a	183	{
91b6f3c5	184	return gpio_get_value(GPIO_PTA1); /* NAND_RBn */
3c803a9a MD	185	}
3c803a9a MD	186
30e0cc1a	187	static struct platform_nand_data migor_nand_flash_data = {
3c803a9a MD	188	.chip = {
	189	.nr_chips = 1,
	190	.partitions = migor_nand_flash_partitions,
	191	.nr_partitions = ARRAY_SIZE(migor_nand_flash_partitions),
	192	.chip_delay = 20,
3c803a9a MD	193	},
	194	.ctrl = {
	195	.dev_ready = migor_nand_flash_ready,
	196	.cmd_ctrl = migor_nand_flash_cmd_ctl,
	197	},
	198	};
	199
	200	static struct resource migor_nand_flash_resources[] = {
	201	[0] = {
	202	.name = "NAND Flash",
	203	.start = 0x18000000,
	204	.end = 0x18ffffff,
	205	.flags = IORESOURCE_MEM,
	206	},
	207	};
	208
	209	static struct platform_device migor_nand_flash_device = {
	210	.name = "gen_nand",
	211	.resource = migor_nand_flash_resources,
	212	.num_resources = ARRAY_SIZE(migor_nand_flash_resources),
	213	.dev = {
	214	.platform_data = &migor_nand_flash_data,
	215	}
	216	};
	217
e04008eb	218	static const struct fb_videomode migor_lcd_modes[] = {
44432407 GL	219	{
	220	#if defined(CONFIG_SH_MIGOR_RTA_WVGA)
	221	.name = "LB070WV1",
	222	.xres = 800,
	223	.yres = 480,
	224	.left_margin = 64,
	225	.right_margin = 16,
	226	.hsync_len = 120,
	227	.sync = 0,
	228	#elif defined(CONFIG_SH_MIGOR_QVGA)
	229	.name = "PH240320T",
	230	.xres = 320,
	231	.yres = 240,
	232	.left_margin = 0,
	233	.right_margin = 16,
	234	.hsync_len = 8,
	235	.sync = FB_SYNC_HOR_HIGH_ACT,
	236	#endif
	237	.upper_margin = 1,
	238	.lower_margin = 17,
	239	.vsync_len = 2,
	240	},
	241	};
	242
8b1285f1	243	static struct sh_mobile_lcdc_info sh_mobile_lcdc_info = {
44432407	244	#if defined(CONFIG_SH_MIGOR_RTA_WVGA)
8b1285f1 MD	245	.clock_source = LCDC_CLK_BUS,
	246	.ch[0] = {
	247	.chan = LCDC_CHAN_MAINLCD,
edd153a3	248	.fourcc = V4L2_PIX_FMT_RGB565,
8b1285f1 MD	249	.interface_type = RGB16,
8b1285f1 MD	250	.clock_divider = 2,
93ff2598 LP	251	.lcd_modes = migor_lcd_modes,
93ff2598 LP	252	.num_modes = ARRAY_SIZE(migor_lcd_modes),
afaad83b	253	.panel_cfg = { /* 7.0 inch */
ce9c008c MD	254	.width = 152,
	255	.height = 91,
	256	},
8b1285f1	257	}
44432407	258	#elif defined(CONFIG_SH_MIGOR_QVGA)
8b1285f1 MD	259	.clock_source = LCDC_CLK_PERIPHERAL,
	260	.ch[0] = {
	261	.chan = LCDC_CHAN_MAINLCD,
edd153a3	262	.fourcc = V4L2_PIX_FMT_RGB565,
8b1285f1 MD	263	.interface_type = SYS16A,
8b1285f1 MD	264	.clock_divider = 10,
93ff2598 LP	265	.lcd_modes = migor_lcd_modes,
93ff2598 LP	266	.num_modes = ARRAY_SIZE(migor_lcd_modes),
afaad83b LP	267	.panel_cfg = {
afaad83b LP	268	.width = 49, /* 2.4 inch */
ce9c008c	269	.height = 37,
8b1285f1 MD	270	.setup_sys = migor_lcd_qvga_setup,
	271	},
	272	.sys_bus_cfg = {
	273	.ldmt2r = 0x06000a09,
	274	.ldmt3r = 0x180e3418,
b5868e8c MD	275	/* set 1s delay to encourage fsync() */
b5868e8c MD	276	.deferred_io_msec = 1000,
8b1285f1 MD	277	},
	278	}
	279	#endif
	280	};
	281
	282	static struct resource migor_lcdc_resources[] = {
	283	[0] = {
	284	.name = "LCDC",
	285	.start = 0xfe940000, /* P4-only space */
a6f15ade	286	.end = 0xfe942fff,
8b1285f1 MD	287	.flags = IORESOURCE_MEM,
8b1285f1 MD	288	},
07905554	289	[1] = {
26819fcb	290	.start = evt2irq(0x580),
07905554 MD	291	.flags = IORESOURCE_IRQ,
07905554 MD	292	},
8b1285f1 MD	293	};
	294
	295	static struct platform_device migor_lcdc_device = {
	296	.name = "sh_mobile_lcdc_fb",
	297	.num_resources = ARRAY_SIZE(migor_lcdc_resources),
	298	.resource = migor_lcdc_resources,
	299	.dev = {
	300	.platform_data = &sh_mobile_lcdc_info,
	301	},
	302	};
	303
186c446f JM	304	static struct ceu_platform_data ceu_pdata = {
	305	.num_subdevs = 2,
	306	.subdevs = {
	307	{ /* [0] = ov772x */
	308	.flags = 0,
	309	.bus_width = 8,
	310	.bus_shift = 0,
	311	.i2c_adapter_id = 0,
	312	.i2c_address = 0x21,
	313	},
	314	{ /* [1] = tw9910 */
	315	.flags = 0,
	316	.bus_width = 8,
	317	.bus_shift = 0,
	318	.i2c_adapter_id = 0,
	319	.i2c_address = 0x45,
	320	},
	321	},
1765534c MD	322	};
	323
	324	static struct resource migor_ceu_resources[] = {
	325	[0] = {
	326	.name = "CEU",
	327	.start = 0xfe910000,
	328	.end = 0xfe91009f,
	329	.flags = IORESOURCE_MEM,
	330	},
	331	[1] = {
26819fcb	332	.start = evt2irq(0x880),
1765534c MD	333	.flags = IORESOURCE_IRQ,
1765534c MD	334	},
1765534c MD	335	};
	336
	337	static struct platform_device migor_ceu_device = {
186c446f JM	338	.name = "renesas-ceu",
186c446f JM	339	.id = 0, /* ceu.0 */
1765534c MD	340	.num_resources = ARRAY_SIZE(migor_ceu_resources),
	341	.resource = migor_ceu_resources,
	342	.dev = {
186c446f JM	343	.platform_data = &ceu_pdata,
	344	},
	345	};
	346
	347	/* Powerdown/reset gpios for CEU image sensors */
	348	static struct gpiod_lookup_table ov7725_gpios = {
	349	.dev_id = "0-0021",
	350	.table = {
40519d54 AM	351	GPIO_LOOKUP("sh7722_pfc", GPIO_PTT0, "powerdown",
	352	GPIO_ACTIVE_HIGH),
	353	GPIO_LOOKUP("sh7722_pfc", GPIO_PTT3, "reset", GPIO_ACTIVE_LOW),
186c446f JM	354	},
	355	};
	356
	357	static struct gpiod_lookup_table tw9910_gpios = {
	358	.dev_id = "0-0045",
	359	.table = {
2b787b66	360	GPIO_LOOKUP("sh7722_pfc", GPIO_PTT2, "pdn", GPIO_ACTIVE_LOW),
186c446f	361	GPIO_LOOKUP("sh7722_pfc", GPIO_PTT3, "rstb", GPIO_ACTIVE_LOW),
1765534c MD	362	},
	363	};
	364
48aff643 GL	365	/* Fixed 3.3V regulator to be used by SDHI0 */
	366	static struct regulator_consumer_supply fixed3v3_power_consumers[] =
	367	{
	368	REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi.0"),
	369	REGULATOR_SUPPLY("vqmmc", "sh_mobile_sdhi.0"),
	370	};
	371
2e3fc56c MD	372	static struct resource sdhi_cn9_resources[] = {
	373	[0] = {
	374	.name = "SDHI",
	375	.start = 0x04ce0000,
d80e9221	376	.end = 0x04ce00ff,
2e3fc56c MD	377	.flags = IORESOURCE_MEM,
	378	},
	379	[1] = {
26819fcb	380	.start = evt2irq(0xe80),
2e3fc56c MD	381	.flags = IORESOURCE_IRQ,
2e3fc56c MD	382	},
70e5c4f0 MD	383	};
70e5c4f0 MD	384
84f11d5b KM	385	static struct tmio_mmc_data sh7724_sdhi_data = {
	386	.chan_priv_tx = (void *)SHDMA_SLAVE_SDHI0_TX,
	387	.chan_priv_rx = (void *)SHDMA_SLAVE_SDHI0_RX,
	388	.capabilities = MMC_CAP_SDIO_IRQ,
65a1b034 GL	389	};
65a1b034 GL	390
2e3fc56c MD	391	static struct platform_device sdhi_cn9_device = {
	392	.name = "sh_mobile_sdhi",
	393	.num_resources = ARRAY_SIZE(sdhi_cn9_resources),
	394	.resource = sdhi_cn9_resources,
65a1b034 GL	395	.dev = {
	396	.platform_data = &sh7724_sdhi_data,
	397	},
70e5c4f0 MD	398	};
70e5c4f0 MD	399
186c446f JM	400	static struct ov772x_camera_info ov7725_info = {
	401	.flags = 0,
	402	};
	403
	404	static struct tw9910_video_info tw9910_info = {
	405	.buswidth = 8,
	406	.mpout = TW9910_MPO_FIELD,
	407	};
	408
1765534c	409	static struct i2c_board_info migor_i2c_devices[] = {
57795867	410	{
3760f736	411	I2C_BOARD_INFO("rs5c372b", 0x32),
57795867	412	},
67908abf MD	413	{
67908abf MD	414	I2C_BOARD_INFO("migor_ts", 0x51),
26819fcb	415	.irq = evt2irq(0x6c0), /* IRQ6 */
67908abf	416	},
920925f9 GL	417	{
	418	I2C_BOARD_INFO("wm8978", 0x1a),
	419	},
ff04ea40 KM	420	{
ff04ea40 KM	421	I2C_BOARD_INFO("ov772x", 0x21),
186c446f	422	.platform_data = &ov7725_info,
ff04ea40	423	},
deae7b86 KM	424	{
deae7b86 KM	425	I2C_BOARD_INFO("tw9910", 0x45),
186c446f	426	.platform_data = &tw9910_info,
2cb582ca GL	427	},
	428	};
	429
	430	static struct platform_device *migor_devices[] __initdata = {
	431	&smc91x_eth_device,
	432	&sh_keysc_device,
	433	&migor_lcdc_device,
2cb582ca GL	434	&migor_nor_flash_device,
2cb582ca GL	435	&migor_nand_flash_device,
2e3fc56c	436	&sdhi_cn9_device,
2cb582ca GL	437	};
2cb582ca GL	438
13fa551b MD	439	extern char migor_sdram_enter_start;
	440	extern char migor_sdram_enter_end;
	441	extern char migor_sdram_leave_start;
	442	extern char migor_sdram_leave_end;
	443
70f784ec MD	444	static int __init migor_devices_setup(void)
70f784ec MD	445	{
186c446f JM	446	struct clk *video_clk;
186c446f JM	447
13fa551b MD	448	/* register board specific self-refresh code */
	449	sh_mobile_register_self_refresh(SUSP_SH_STANDBY \| SUSP_SH_SF,
	450	&migor_sdram_enter_start,
	451	&migor_sdram_enter_end,
	452	&migor_sdram_leave_start,
	453	&migor_sdram_leave_end);
48aff643 GL	454
	455	regulator_register_always_on(0, "fixed-3.3V", fixed3v3_power_consumers,
	456	ARRAY_SIZE(fixed3v3_power_consumers), 3300000);
	457
50840714 MD	458	/* Let D11 LED show STATUS0 */
	459	gpio_request(GPIO_FN_STATUS0, NULL);
	460
	461	/* Lit D12 LED show PDSTATUS */
	462	gpio_request(GPIO_FN_PDSTATUS, NULL);
91b6f3c5	463
a30c89ad	464	/* SMC91C111 - Enable IRQ0, Setup CS4 for 16-bit fast access */
91b6f3c5	465	gpio_request(GPIO_FN_IRQ0, NULL);
9d56dd3b PM	466	__raw_writel(0x00003400, BSC_CS4BCR);
9d56dd3b PM	467	__raw_writel(0x00110080, BSC_CS4WCR);
91b6f3c5 MD	468
91b6f3c5 MD	469	/* KEYSC */
91b6f3c5 MD	470	gpio_request(GPIO_FN_KEYOUT0, NULL);
	471	gpio_request(GPIO_FN_KEYOUT1, NULL);
	472	gpio_request(GPIO_FN_KEYOUT2, NULL);
	473	gpio_request(GPIO_FN_KEYOUT3, NULL);
	474	gpio_request(GPIO_FN_KEYOUT4_IN6, NULL);
	475	gpio_request(GPIO_FN_KEYIN1, NULL);
	476	gpio_request(GPIO_FN_KEYIN2, NULL);
	477	gpio_request(GPIO_FN_KEYIN3, NULL);
	478	gpio_request(GPIO_FN_KEYIN4, NULL);
	479	gpio_request(GPIO_FN_KEYOUT5_IN5, NULL);
	480
	481	/* NAND Flash */
	482	gpio_request(GPIO_FN_CS6A_CE2B, NULL);
9d56dd3b	483	__raw_writel((__raw_readl(BSC_CS6ABCR) & ~0x0600) \| 0x0200, BSC_CS6ABCR);
91b6f3c5 MD	484	gpio_request(GPIO_PTA1, NULL);
	485	gpio_direction_input(GPIO_PTA1);
	486
2e3fc56c MD	487	/* SDHI */
	488	gpio_request(GPIO_FN_SDHICD, NULL);
	489	gpio_request(GPIO_FN_SDHIWP, NULL);
	490	gpio_request(GPIO_FN_SDHID3, NULL);
	491	gpio_request(GPIO_FN_SDHID2, NULL);
	492	gpio_request(GPIO_FN_SDHID1, NULL);
	493	gpio_request(GPIO_FN_SDHID0, NULL);
	494	gpio_request(GPIO_FN_SDHICMD, NULL);
	495	gpio_request(GPIO_FN_SDHICLK, NULL);
	496
91b6f3c5 MD	497	/* Touch Panel */
	498	gpio_request(GPIO_FN_IRQ6, NULL);
	499
	500	/* LCD Panel */
91b6f3c5 MD	501	#ifdef CONFIG_SH_MIGOR_QVGA /* LCDC - QVGA - Enable SYS Interface signals */
	502	gpio_request(GPIO_FN_LCDD17, NULL);
	503	gpio_request(GPIO_FN_LCDD16, NULL);
	504	gpio_request(GPIO_FN_LCDD15, NULL);
	505	gpio_request(GPIO_FN_LCDD14, NULL);
	506	gpio_request(GPIO_FN_LCDD13, NULL);
	507	gpio_request(GPIO_FN_LCDD12, NULL);
	508	gpio_request(GPIO_FN_LCDD11, NULL);
	509	gpio_request(GPIO_FN_LCDD10, NULL);
	510	gpio_request(GPIO_FN_LCDD8, NULL);
	511	gpio_request(GPIO_FN_LCDD7, NULL);
	512	gpio_request(GPIO_FN_LCDD6, NULL);
	513	gpio_request(GPIO_FN_LCDD5, NULL);
	514	gpio_request(GPIO_FN_LCDD4, NULL);
	515	gpio_request(GPIO_FN_LCDD3, NULL);
	516	gpio_request(GPIO_FN_LCDD2, NULL);
	517	gpio_request(GPIO_FN_LCDD1, NULL);
	518	gpio_request(GPIO_FN_LCDRS, NULL);
	519	gpio_request(GPIO_FN_LCDCS, NULL);
	520	gpio_request(GPIO_FN_LCDRD, NULL);
	521	gpio_request(GPIO_FN_LCDWR, NULL);
	522	gpio_request(GPIO_PTH2, NULL); /* LCD_DON */
	523	gpio_direction_output(GPIO_PTH2, 1);
	524	#endif
	525	#ifdef CONFIG_SH_MIGOR_RTA_WVGA /* LCDC - WVGA - Enable RGB Interface signals */
	526	gpio_request(GPIO_FN_LCDD15, NULL);
	527	gpio_request(GPIO_FN_LCDD14, NULL);
	528	gpio_request(GPIO_FN_LCDD13, NULL);
	529	gpio_request(GPIO_FN_LCDD12, NULL);
	530	gpio_request(GPIO_FN_LCDD11, NULL);
	531	gpio_request(GPIO_FN_LCDD10, NULL);
	532	gpio_request(GPIO_FN_LCDD9, NULL);
	533	gpio_request(GPIO_FN_LCDD8, NULL);
	534	gpio_request(GPIO_FN_LCDD7, NULL);
	535	gpio_request(GPIO_FN_LCDD6, NULL);
	536	gpio_request(GPIO_FN_LCDD5, NULL);
	537	gpio_request(GPIO_FN_LCDD4, NULL);
	538	gpio_request(GPIO_FN_LCDD3, NULL);
	539	gpio_request(GPIO_FN_LCDD2, NULL);
	540	gpio_request(GPIO_FN_LCDD1, NULL);
	541	gpio_request(GPIO_FN_LCDD0, NULL);
	542	gpio_request(GPIO_FN_LCDLCLK, NULL);
	543	gpio_request(GPIO_FN_LCDDCK, NULL);
	544	gpio_request(GPIO_FN_LCDVEPWC, NULL);
	545	gpio_request(GPIO_FN_LCDVCPWC, NULL);
	546	gpio_request(GPIO_FN_LCDVSYN, NULL);
	547	gpio_request(GPIO_FN_LCDHSYN, NULL);
	548	gpio_request(GPIO_FN_LCDDISP, NULL);
	549	gpio_request(GPIO_FN_LCDDON, NULL);
	550	#endif
	551
	552	/* CEU */
91b6f3c5 MD	553	gpio_request(GPIO_FN_VIO_CLK2, NULL);
	554	gpio_request(GPIO_FN_VIO_VD2, NULL);
	555	gpio_request(GPIO_FN_VIO_HD2, NULL);
	556	gpio_request(GPIO_FN_VIO_FLD, NULL);
	557	gpio_request(GPIO_FN_VIO_CKO, NULL);
	558	gpio_request(GPIO_FN_VIO_D15, NULL);
	559	gpio_request(GPIO_FN_VIO_D14, NULL);
	560	gpio_request(GPIO_FN_VIO_D13, NULL);
	561	gpio_request(GPIO_FN_VIO_D12, NULL);
	562	gpio_request(GPIO_FN_VIO_D11, NULL);
	563	gpio_request(GPIO_FN_VIO_D10, NULL);
	564	gpio_request(GPIO_FN_VIO_D9, NULL);
	565	gpio_request(GPIO_FN_VIO_D8, NULL);
	566
9d56dd3b	567	__raw_writew(__raw_readw(PORT_MSELCRB) \| 0x2000, PORT_MSELCRB); /* D15->D8 */
1765534c	568
920925f9 GL	569	/* SIU: Port B */
	570	gpio_request(GPIO_FN_SIUBOLR, NULL);
	571	gpio_request(GPIO_FN_SIUBOBT, NULL);
	572	gpio_request(GPIO_FN_SIUBISLD, NULL);
	573	gpio_request(GPIO_FN_SIUBOSLD, NULL);
	574	gpio_request(GPIO_FN_SIUMCKB, NULL);
	575
	576	/*
	577	* The original driver sets SIUB OLR/OBT, ILR/IBT, and SIUA OLR/OBT to
	578	* output. Need only SIUB, set to output for master mode (table 34.2)
	579	*/
7d0b0a44	580	__raw_writew(__raw_readw(PORT_MSELCRA) \| 1, PORT_MSELCRA);
920925f9	581
186c446f JM	582	/*
	583	* Use 10 MHz VIO_CKO instead of 24 MHz to work around signal quality
	584	* issues on Panel Board V2.1.
	585	*/
	586	video_clk = clk_get(NULL, "video_clk");
	587	if (!IS_ERR(video_clk)) {
	588	clk_set_rate(video_clk, clk_round_rate(video_clk, 10000000));
	589	clk_put(video_clk);
	590	}
	591
	592	/* Add a clock alias for ov7725 xclk source. */
89ce93fd	593	clk_add_alias(NULL, "0-0021", "video_clk", NULL);
186c446f JM	594
	595	/* Register GPIOs for video sources. */
	596	gpiod_add_lookup_table(&ov7725_gpios);
	597	gpiod_add_lookup_table(&tw9910_gpios);
	598
0c6111ec MD	599	i2c_register_board_info(0, migor_i2c_devices,
0c6111ec MD	600	ARRAY_SIZE(migor_i2c_devices));
91b6f3c5	601
186c446f JM	602	/* Initialize CEU platform device separately to map memory first */
	603	device_initialize(&migor_ceu_device.dev);
	604	arch_setup_pdev_archdata(&migor_ceu_device);
	605	dma_declare_coherent_memory(&migor_ceu_device.dev,
	606	ceu_dma_membase, ceu_dma_membase,
	607	ceu_dma_membase + CEU_BUFFER_MEMORY_SIZE - 1,
	608	DMA_MEMORY_EXCLUSIVE);
	609
	610	platform_device_add(&migor_ceu_device);
	611
70f784ec MD	612	return platform_add_devices(migor_devices, ARRAY_SIZE(migor_devices));
70f784ec MD	613	}
ba3a1701	614	arch_initcall(migor_devices_setup);
0ec80fdd MD	615
	616	/* Return the board specific boot mode pin configuration */
	617	static int migor_mode_pins(void)
	618	{
	619	/* MD0=1, MD1=1, MD2=0: Clock Mode 3
	620	* MD3=0: 16-bit Area0 Bus Width
	621	* MD5=1: Little Endian
	622	* TSTMD=1, MD8=0: Test Mode Disabled
	623	*/
	624	return MODE_PIN0 \| MODE_PIN1 \| MODE_PIN5;
	625	}
	626
186c446f JM	627	/* Reserve a portion of memory for CEU buffers */
	628	static void __init migor_mv_mem_reserve(void)
	629	{
	630	phys_addr_t phys;
	631	phys_addr_t size = CEU_BUFFER_MEMORY_SIZE;
	632
	633	phys = memblock_alloc_base(size, PAGE_SIZE, MEMBLOCK_ALLOC_ANYWHERE);
	634	memblock_free(phys, size);
	635	memblock_remove(phys, size);
	636
	637	ceu_dma_membase = phys;
	638	}
	639
0ec80fdd MD	640	/*
	641	* The Machine Vector
	642	*/
	643	static struct sh_machine_vector mv_migor __initmv = {
	644	.mv_name = "Migo-R",
	645	.mv_mode_pins = migor_mode_pins,
186c446f	646	.mv_mem_reserve = migor_mv_mem_reserve,
0ec80fdd	647	};