[linux-2.6-block.git] / arch / sh / boards / board-sh7785lcr.c

/*
 * Renesas Technology Corp. R0P7785LC0011RL Support.
 *
 * Copyright (C) 2008  Yoshihiro Shimoda
 * Copyright (C) 2009  Paul Mundt
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 */
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/sm501.h>
#include <linux/sm501-regs.h>
#include <linux/fb.h>
#include <linux/mtd/physmap.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/i2c.h>
#include <linux/platform_data/i2c-pca-platform.h>
#include <linux/i2c-algo-pca.h>
#include <linux/usb/r8a66597.h>
#include <linux/sh_intc.h>
#include <linux/irq.h>
#include <linux/io.h>
#include <linux/clk.h>
#include <linux/errno.h>
#include <linux/gpio/machine.h>
#include <mach/sh7785lcr.h>
#include <cpu/sh7785.h>
#include <asm/heartbeat.h>
#include <asm/clock.h>
#include <asm/bl_bit.h>

/*
 * NOTE: This board has 2 physical memory maps.
 *	 Please look at include/asm-sh/sh7785lcr.h or hardware manual.
 */
static struct resource heartbeat_resource = {
	.start	= PLD_LEDCR,
	.end	= PLD_LEDCR,
	.flags	= IORESOURCE_MEM | IORESOURCE_MEM_8BIT,
};

static struct platform_device heartbeat_device = {
	.name		= "heartbeat",
	.id		= -1,
	.num_resources	= 1,
	.resource	= &heartbeat_resource,
};

static struct mtd_partition nor_flash_partitions[] = {
	{
		.name		= "loader",
		.offset		= 0x00000000,
		.size		= 512 * 1024,
	},
	{
		.name		= "bootenv",
		.offset		= MTDPART_OFS_APPEND,
		.size		= 512 * 1024,
	},
	{
		.name		= "kernel",
		.offset		= MTDPART_OFS_APPEND,
		.size		= 4 * 1024 * 1024,
	},
	{
		.name		= "data",
		.offset		= MTDPART_OFS_APPEND,
		.size		= MTDPART_SIZ_FULL,
	},
};

static struct physmap_flash_data nor_flash_data = {
	.width		= 4,
	.parts		= nor_flash_partitions,
	.nr_parts	= ARRAY_SIZE(nor_flash_partitions),
};

static struct resource nor_flash_resources[] = {
	[0]	= {
		.start	= NOR_FLASH_ADDR,
		.end	= NOR_FLASH_ADDR + NOR_FLASH_SIZE - 1,
		.flags	= IORESOURCE_MEM,
	}
};

static struct platform_device nor_flash_device = {
	.name		= "physmap-flash",
	.dev		= {
		.platform_data	= &nor_flash_data,
	},
	.num_resources	= ARRAY_SIZE(nor_flash_resources),
	.resource	= nor_flash_resources,
};

static struct r8a66597_platdata r8a66597_data = {
	.xtal = R8A66597_PLATDATA_XTAL_12MHZ,
	.vif = 1,
};

static struct resource r8a66597_usb_host_resources[] = {
	[0] = {
		.start	= R8A66597_ADDR,
		.end	= R8A66597_ADDR + R8A66597_SIZE - 1,
		.flags	= IORESOURCE_MEM,
	},
	[1] = {
		.start	= evt2irq(0x240),
		.end	= evt2irq(0x240),
		.flags	= IORESOURCE_IRQ | IRQF_TRIGGER_LOW,
	},
};

static struct platform_device r8a66597_usb_host_device = {
	.name		= "r8a66597_hcd",
	.id		= -1,
	.dev = {
		.dma_mask		= NULL,
		.coherent_dma_mask	= 0xffffffff,
		.platform_data		= &r8a66597_data,
	},
	.num_resources	= ARRAY_SIZE(r8a66597_usb_host_resources),
	.resource	= r8a66597_usb_host_resources,
};

static struct resource sm501_resources[] = {
	[0]	= {
		.start	= SM107_MEM_ADDR,
		.end	= SM107_MEM_ADDR + SM107_MEM_SIZE - 1,
		.flags	= IORESOURCE_MEM,
	},
	[1]	= {
		.start	= SM107_REG_ADDR,
		.end	= SM107_REG_ADDR + SM107_REG_SIZE - 1,
		.flags	= IORESOURCE_MEM,
	},
	[2]	= {
		.start	= evt2irq(0x340),
		.flags	= IORESOURCE_IRQ,
	},
};

static struct fb_videomode sm501_default_mode_crt = {
	.pixclock	= 35714,	/* 28MHz */
	.xres		= 640,
	.yres		= 480,
	.left_margin	= 105,
	.right_margin	= 16,
	.upper_margin	= 33,
	.lower_margin	= 10,
	.hsync_len	= 39,
	.vsync_len	= 2,
	.sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
};

static struct fb_videomode sm501_default_mode_pnl = {
	.pixclock	= 40000,	/* 25MHz */
	.xres		= 640,
	.yres		= 480,
	.left_margin	= 2,
	.right_margin	= 16,
	.upper_margin	= 33,
	.lower_margin	= 10,
	.hsync_len	= 39,
	.vsync_len	= 2,
	.sync		= 0,
};

static struct sm501_platdata_fbsub sm501_pdata_fbsub_pnl = {
	.def_bpp	= 16,
	.def_mode	= &sm501_default_mode_pnl,
	.flags		= SM501FB_FLAG_USE_INIT_MODE |
			  SM501FB_FLAG_USE_HWCURSOR |
			  SM501FB_FLAG_USE_HWACCEL |
			  SM501FB_FLAG_DISABLE_AT_EXIT |
			  SM501FB_FLAG_PANEL_NO_VBIASEN,
};

static struct sm501_platdata_fbsub sm501_pdata_fbsub_crt = {
	.def_bpp	= 16,
	.def_mode	= &sm501_default_mode_crt,
	.flags		= SM501FB_FLAG_USE_INIT_MODE |
			  SM501FB_FLAG_USE_HWCURSOR |
			  SM501FB_FLAG_USE_HWACCEL |
			  SM501FB_FLAG_DISABLE_AT_EXIT,
};

static struct sm501_platdata_fb sm501_fb_pdata = {
	.fb_route	= SM501_FB_OWN,
	.fb_crt		= &sm501_pdata_fbsub_crt,
	.fb_pnl		= &sm501_pdata_fbsub_pnl,
};

static struct sm501_initdata sm501_initdata = {
	.gpio_high	= {
		.set	= 0x00001fe0,
		.mask	= 0x0,
	},
	.devices	= 0,
	.mclk		= 84 * 1000000,
	.m1xclk		= 112 * 1000000,
};

static struct sm501_platdata sm501_platform_data = {
	.init		= &sm501_initdata,
	.fb		= &sm501_fb_pdata,
};

static struct platform_device sm501_device = {
	.name		= "sm501",
	.id		= -1,
	.dev		= {
		.platform_data	= &sm501_platform_data,
	},
	.num_resources	= ARRAY_SIZE(sm501_resources),
	.resource	= sm501_resources,
};

static struct resource i2c_proto_resources[] = {
	[0] = {
		.start	= PCA9564_PROTO_32BIT_ADDR,
		.end	= PCA9564_PROTO_32BIT_ADDR + PCA9564_SIZE - 1,
		.flags	= IORESOURCE_MEM | IORESOURCE_MEM_8BIT,
	},
	[1] = {
		.start	= evt2irq(0x380),
		.end	= evt2irq(0x380),
		.flags	= IORESOURCE_IRQ,
	},
};

static struct resource i2c_resources[] = {
	[0] = {
		.start	= PCA9564_ADDR,
		.end	= PCA9564_ADDR + PCA9564_SIZE - 1,
		.flags	= IORESOURCE_MEM | IORESOURCE_MEM_8BIT,
	},
	[1] = {
		.start	= evt2irq(0x380),
		.end	= evt2irq(0x380),
		.flags	= IORESOURCE_IRQ,
	},
};

static struct gpiod_lookup_table i2c_gpio_table = {
	.dev_id = "i2c.0",
	.table = {
		GPIO_LOOKUP("pfc-sh7757", 0, "reset-gpios", GPIO_ACTIVE_LOW),
		{ },
	},
};

static struct i2c_pca9564_pf_platform_data i2c_platform_data = {
	.i2c_clock_speed	= I2C_PCA_CON_330kHz,
	.timeout		= HZ,
};

static struct platform_device i2c_device = {
	.name		= "i2c-pca-platform",
	.id		= -1,
	.dev		= {
		.platform_data	= &i2c_platform_data,
	},
	.num_resources	= ARRAY_SIZE(i2c_resources),
	.resource	= i2c_resources,
};

static struct platform_device *sh7785lcr_devices[] __initdata = {
	&heartbeat_device,
	&nor_flash_device,
	&r8a66597_usb_host_device,
	&sm501_device,
	&i2c_device,
};

static struct i2c_board_info __initdata sh7785lcr_i2c_devices[] = {
	{
		I2C_BOARD_INFO("r2025sd", 0x32),
	},
};

static int __init sh7785lcr_devices_setup(void)
{
	i2c_register_board_info(0, sh7785lcr_i2c_devices,
				ARRAY_SIZE(sh7785lcr_i2c_devices));

	if (mach_is_sh7785lcr_pt()) {
		i2c_device.resource = i2c_proto_resources;
		i2c_device.num_resources = ARRAY_SIZE(i2c_proto_resources);
	}

	gpiod_add_lookup_table(&i2c_gpio_table);
	return platform_add_devices(sh7785lcr_devices,
				    ARRAY_SIZE(sh7785lcr_devices));
}
device_initcall(sh7785lcr_devices_setup);

/* Initialize IRQ setting */
void __init init_sh7785lcr_IRQ(void)
{
	plat_irq_setup_pins(IRQ_MODE_IRQ7654);
	plat_irq_setup_pins(IRQ_MODE_IRQ3210);
}

static int sh7785lcr_clk_init(void)
{
	struct clk *clk;
	int ret;

	clk = clk_get(NULL, "extal");
	if (IS_ERR(clk))
		return PTR_ERR(clk);
	ret = clk_set_rate(clk, 33333333);
	clk_put(clk);

	return ret;
}

static void sh7785lcr_power_off(void)
{
	unsigned char *p;

	p = ioremap(PLD_POFCR, PLD_POFCR + 1);
	if (!p) {
		printk(KERN_ERR "%s: ioremap error.\n", __func__);
		return;
	}
	*p = 0x01;
	iounmap(p);
	set_bl_bit();
	while (1)
		cpu_relax();
}

/* Initialize the board */
static void __init sh7785lcr_setup(char **cmdline_p)
{
	void __iomem *sm501_reg;

	printk(KERN_INFO "Renesas Technology Corp. R0P7785LC0011RL support.\n");

	pm_power_off = sh7785lcr_power_off;

	/* sm501 DRAM configuration */
	sm501_reg = ioremap_nocache(SM107_REG_ADDR, SM501_DRAM_CONTROL);
	if (!sm501_reg) {
		printk(KERN_ERR "%s: ioremap error.\n", __func__);
		return;
	}

	writel(0x000307c2, sm501_reg + SM501_DRAM_CONTROL);
	iounmap(sm501_reg);
}

/* Return the board specific boot mode pin configuration */
static int sh7785lcr_mode_pins(void)
{
	int value = 0;

	/* These are the factory default settings of S1 and S2.
	 * If you change these dip switches then you will need to
	 * adjust the values below as well.
	 */
	value |= MODE_PIN4; /* Clock Mode 16 */
	value |= MODE_PIN5; /* 32-bit Area0 bus width */
	value |= MODE_PIN6; /* 32-bit Area0 bus width */
	value |= MODE_PIN7; /* Area 0 SRAM interface [fixed] */
	value |= MODE_PIN8; /* Little Endian */
	value |= MODE_PIN9; /* Master Mode */
	value |= MODE_PIN14; /* No PLL step-up */

	return value;
}

/*
 * The Machine Vector
 */
static struct sh_machine_vector mv_sh7785lcr __initmv = {
	.mv_name		= "SH7785LCR",
	.mv_setup		= sh7785lcr_setup,
	.mv_clk_init		= sh7785lcr_clk_init,
	.mv_init_irq		= init_sh7785lcr_IRQ,
	.mv_mode_pins		= sh7785lcr_mode_pins,
};
Commit	Line	Data
cbe9da02 YS	1	/*
	2	* Renesas Technology Corp. R0P7785LC0011RL Support.
	3	*
	4	* Copyright (C) 2008 Yoshihiro Shimoda
a77b5ac0	5	* Copyright (C) 2009 Paul Mundt
cbe9da02 YS	6	*
	7	* This file is subject to the terms and conditions of the GNU General Public
	8	* License. See the file "COPYING" in the main directory of this archive
	9	* for more details.
	10	*/
cbe9da02 YS	11	#include <linux/init.h>
	12	#include <linux/platform_device.h>
	13	#include <linux/sm501.h>
	14	#include <linux/sm501-regs.h>
	15	#include <linux/fb.h>
	16	#include <linux/mtd/physmap.h>
	17	#include <linux/delay.h>
5a62a225	18	#include <linux/interrupt.h>
cbe9da02	19	#include <linux/i2c.h>
e5c71377	20	#include <linux/platform_data/i2c-pca-platform.h>
cbe9da02	21	#include <linux/i2c-algo-pca.h>
5a62a225	22	#include <linux/usb/r8a66597.h>
c825abc4	23	#include <linux/sh_intc.h>
604437f0	24	#include <linux/irq.h>
d57d6408	25	#include <linux/io.h>
a77b5ac0 PM	26	#include <linux/clk.h>
a77b5ac0 PM	27	#include <linux/errno.h>
df0d3234	28	#include <linux/gpio/machine.h>
7639a454	29	#include <mach/sh7785lcr.h>
5a62a225	30	#include <cpu/sh7785.h>
a77b5ac0 PM	31	#include <asm/heartbeat.h>
a77b5ac0 PM	32	#include <asm/clock.h>
f03c4866	33	#include <asm/bl_bit.h>
cbe9da02 YS	34
	35	/*
	36	* NOTE: This board has 2 physical memory maps.
	37	* Please look at include/asm-sh/sh7785lcr.h or hardware manual.
	38	*/
a09d2831 PM	39	static struct resource heartbeat_resource = {
	40	.start = PLD_LEDCR,
	41	.end = PLD_LEDCR,
	42	.flags = IORESOURCE_MEM \| IORESOURCE_MEM_8BIT,
cbe9da02 YS	43	};
	44
	45	static struct platform_device heartbeat_device = {
	46	.name = "heartbeat",
	47	.id = -1,
a09d2831 PM	48	.num_resources = 1,
a09d2831 PM	49	.resource = &heartbeat_resource,
cbe9da02 YS	50	};
	51
	52	static struct mtd_partition nor_flash_partitions[] = {
	53	{
	54	.name = "loader",
	55	.offset = 0x00000000,
	56	.size = 512 * 1024,
	57	},
	58	{
	59	.name = "bootenv",
	60	.offset = MTDPART_OFS_APPEND,
	61	.size = 512 * 1024,
	62	},
	63	{
	64	.name = "kernel",
	65	.offset = MTDPART_OFS_APPEND,
	66	.size = 4 * 1024 * 1024,
	67	},
	68	{
	69	.name = "data",
	70	.offset = MTDPART_OFS_APPEND,
	71	.size = MTDPART_SIZ_FULL,
	72	},
	73	};
	74
	75	static struct physmap_flash_data nor_flash_data = {
	76	.width = 4,
	77	.parts = nor_flash_partitions,
	78	.nr_parts = ARRAY_SIZE(nor_flash_partitions),
	79	};
	80
	81	static struct resource nor_flash_resources[] = {
	82	[0] = {
	83	.start = NOR_FLASH_ADDR,
	84	.end = NOR_FLASH_ADDR + NOR_FLASH_SIZE - 1,
	85	.flags = IORESOURCE_MEM,
	86	}
	87	};
	88
	89	static struct platform_device nor_flash_device = {
	90	.name = "physmap-flash",
	91	.dev = {
	92	.platform_data = &nor_flash_data,
	93	},
	94	.num_resources = ARRAY_SIZE(nor_flash_resources),
	95	.resource = nor_flash_resources,
	96	};
	97
5a62a225 YS	98	static struct r8a66597_platdata r8a66597_data = {
	99	.xtal = R8A66597_PLATDATA_XTAL_12MHZ,
	100	.vif = 1,
	101	};
	102
cbe9da02 YS	103	static struct resource r8a66597_usb_host_resources[] = {
cbe9da02 YS	104	[0] = {
cbe9da02 YS	105	.start = R8A66597_ADDR,
	106	.end = R8A66597_ADDR + R8A66597_SIZE - 1,
	107	.flags = IORESOURCE_MEM,
	108	},
	109	[1] = {
c825abc4 PM	110	.start = evt2irq(0x240),
c825abc4 PM	111	.end = evt2irq(0x240),
5a62a225	112	.flags = IORESOURCE_IRQ \| IRQF_TRIGGER_LOW,
cbe9da02 YS	113	},
	114	};
	115
	116	static struct platform_device r8a66597_usb_host_device = {
	117	.name = "r8a66597_hcd",
	118	.id = -1,
	119	.dev = {
	120	.dma_mask = NULL,
	121	.coherent_dma_mask = 0xffffffff,
5a62a225	122	.platform_data = &r8a66597_data,
cbe9da02 YS	123	},
	124	.num_resources = ARRAY_SIZE(r8a66597_usb_host_resources),
	125	.resource = r8a66597_usb_host_resources,
	126	};
	127
	128	static struct resource sm501_resources[] = {
	129	[0] = {
	130	.start = SM107_MEM_ADDR,
	131	.end = SM107_MEM_ADDR + SM107_MEM_SIZE - 1,
	132	.flags = IORESOURCE_MEM,
	133	},
	134	[1] = {
	135	.start = SM107_REG_ADDR,
	136	.end = SM107_REG_ADDR + SM107_REG_SIZE - 1,
	137	.flags = IORESOURCE_MEM,
	138	},
	139	[2] = {
c825abc4	140	.start = evt2irq(0x340),
cbe9da02 YS	141	.flags = IORESOURCE_IRQ,
	142	},
	143	};
	144
	145	static struct fb_videomode sm501_default_mode_crt = {
	146	.pixclock = 35714, /* 28MHz */
	147	.xres = 640,
	148	.yres = 480,
	149	.left_margin = 105,
	150	.right_margin = 16,
	151	.upper_margin = 33,
	152	.lower_margin = 10,
	153	.hsync_len = 39,
	154	.vsync_len = 2,
	155	.sync = FB_SYNC_HOR_HIGH_ACT \| FB_SYNC_VERT_HIGH_ACT,
	156	};
	157
	158	static struct fb_videomode sm501_default_mode_pnl = {
	159	.pixclock = 40000, /* 25MHz */
	160	.xres = 640,
	161	.yres = 480,
	162	.left_margin = 2,
	163	.right_margin = 16,
	164	.upper_margin = 33,
	165	.lower_margin = 10,
	166	.hsync_len = 39,
	167	.vsync_len = 2,
	168	.sync = 0,
	169	};
	170
	171	static struct sm501_platdata_fbsub sm501_pdata_fbsub_pnl = {
	172	.def_bpp = 16,
	173	.def_mode = &sm501_default_mode_pnl,
	174	.flags = SM501FB_FLAG_USE_INIT_MODE \|
	175	SM501FB_FLAG_USE_HWCURSOR \|
	176	SM501FB_FLAG_USE_HWACCEL \|
	177	SM501FB_FLAG_DISABLE_AT_EXIT \|
	178	SM501FB_FLAG_PANEL_NO_VBIASEN,
	179	};
	180
	181	static struct sm501_platdata_fbsub sm501_pdata_fbsub_crt = {
	182	.def_bpp = 16,
	183	.def_mode = &sm501_default_mode_crt,
	184	.flags = SM501FB_FLAG_USE_INIT_MODE \|
	185	SM501FB_FLAG_USE_HWCURSOR \|
	186	SM501FB_FLAG_USE_HWACCEL \|
	187	SM501FB_FLAG_DISABLE_AT_EXIT,
	188	};
	189
	190	static struct sm501_platdata_fb sm501_fb_pdata = {
	191	.fb_route = SM501_FB_OWN,
	192	.fb_crt = &sm501_pdata_fbsub_crt,
	193	.fb_pnl = &sm501_pdata_fbsub_pnl,
	194	};
	195
	196	static struct sm501_initdata sm501_initdata = {
	197	.gpio_high = {
	198	.set = 0x00001fe0,
	199	.mask = 0x0,
	200	},
	201	.devices = 0,
	202	.mclk = 84 * 1000000,
	203	.m1xclk = 112 * 1000000,
	204	};
205
206	static struct sm501_platdata sm501_platform_data = {
207	.init = &sm501_initdata,
208	.fb = &sm501_fb_pdata,
209	};
210
211	static struct platform_device sm501_device = {
212	.name = "sm501",
213	.id = -1,
214	.dev = {
215	.platform_data = &sm501_platform_data,
216	},
217	.num_resources = ARRAY_SIZE(sm501_resources),
218	.resource = sm501_resources,
219	};
220
e79d5747 YS	221	static struct resource i2c_proto_resources[] = {
	222	[0] = {
	223	.start = PCA9564_PROTO_32BIT_ADDR,
	224	.end = PCA9564_PROTO_32BIT_ADDR + PCA9564_SIZE - 1,
	225	.flags = IORESOURCE_MEM \| IORESOURCE_MEM_8BIT,
	226	},
	227	[1] = {
c825abc4 PM	228	.start = evt2irq(0x380),
c825abc4 PM	229	.end = evt2irq(0x380),
e79d5747 YS	230	.flags = IORESOURCE_IRQ,
	231	},
	232	};
	233
cbe9da02 YS	234	static struct resource i2c_resources[] = {
	235	[0] = {
	236	.start = PCA9564_ADDR,
	237	.end = PCA9564_ADDR + PCA9564_SIZE - 1,
	238	.flags = IORESOURCE_MEM \| IORESOURCE_MEM_8BIT,
	239	},
	240	[1] = {
c825abc4 PM	241	.start = evt2irq(0x380),
c825abc4 PM	242	.end = evt2irq(0x380),
cbe9da02 YS	243	.flags = IORESOURCE_IRQ,
	244	},
	245	};
	246
df0d3234 CP	247	static struct gpiod_lookup_table i2c_gpio_table = {
	248	.dev_id = "i2c.0",
	249	.table = {
	250	GPIO_LOOKUP("pfc-sh7757", 0, "reset-gpios", GPIO_ACTIVE_LOW),
	251	{ },
	252	},
	253	};
	254
cbe9da02	255	static struct i2c_pca9564_pf_platform_data i2c_platform_data = {
cbe9da02	256	.i2c_clock_speed = I2C_PCA_CON_330kHz,
8e99ada8	257	.timeout = HZ,
cbe9da02 YS	258	};
	259
	260	static struct platform_device i2c_device = {
	261	.name = "i2c-pca-platform",
	262	.id = -1,
	263	.dev = {
	264	.platform_data = &i2c_platform_data,
	265	},
	266	.num_resources = ARRAY_SIZE(i2c_resources),
	267	.resource = i2c_resources,
	268	};
	269
	270	static struct platform_device *sh7785lcr_devices[] __initdata = {
	271	&heartbeat_device,
	272	&nor_flash_device,
	273	&r8a66597_usb_host_device,
	274	&sm501_device,
	275	&i2c_device,
	276	};
	277
	278	static struct i2c_board_info __initdata sh7785lcr_i2c_devices[] = {
	279	{
	280	I2C_BOARD_INFO("r2025sd", 0x32),
	281	},
	282	};
	283
	284	static int __init sh7785lcr_devices_setup(void)
	285	{
	286	i2c_register_board_info(0, sh7785lcr_i2c_devices,
	287	ARRAY_SIZE(sh7785lcr_i2c_devices));
	288
e79d5747	289	if (mach_is_sh7785lcr_pt()) {
d1af119a	290	i2c_device.resource = i2c_proto_resources;
e79d5747 YS	291	i2c_device.num_resources = ARRAY_SIZE(i2c_proto_resources);
	292	}
	293
df0d3234	294	gpiod_add_lookup_table(&i2c_gpio_table);
cbe9da02 YS	295	return platform_add_devices(sh7785lcr_devices,
	296	ARRAY_SIZE(sh7785lcr_devices));
	297	}
95d210ce	298	device_initcall(sh7785lcr_devices_setup);
cbe9da02 YS	299
	300	/* Initialize IRQ setting */
	301	void __init init_sh7785lcr_IRQ(void)
	302	{
	303	plat_irq_setup_pins(IRQ_MODE_IRQ7654);
	304	plat_irq_setup_pins(IRQ_MODE_IRQ3210);
	305	}
	306
a77b5ac0 PM	307	static int sh7785lcr_clk_init(void)
	308	{
	309	struct clk *clk;
	310	int ret;
	311
	312	clk = clk_get(NULL, "extal");
7912825d	313	if (IS_ERR(clk))
a77b5ac0 PM	314	return PTR_ERR(clk);
	315	ret = clk_set_rate(clk, 33333333);
	316	clk_put(clk);
	317
	318	return ret;
	319	}
	320
cbe9da02 YS	321	static void sh7785lcr_power_off(void)
cbe9da02 YS	322	{
df4d4f1a YS	323	unsigned char *p;
	324
	325	p = ioremap(PLD_POFCR, PLD_POFCR + 1);
	326	if (!p) {
	327	printk(KERN_ERR "%s: ioremap error.\n", __func__);
	328	return;
	329	}
	330	*p = 0x01;
	331	iounmap(p);
600fa578 MD	332	set_bl_bit();
	333	while (1)
	334	cpu_relax();
cbe9da02 YS	335	}
	336
	337	/* Initialize the board */
	338	static void __init sh7785lcr_setup(char **cmdline_p)
	339	{
	340	void __iomem *sm501_reg;
	341
	342	printk(KERN_INFO "Renesas Technology Corp. R0P7785LC0011RL support.\n");
	343
	344	pm_power_off = sh7785lcr_power_off;
	345
	346	/* sm501 DRAM configuration */
d57d6408	347	sm501_reg = ioremap_nocache(SM107_REG_ADDR, SM501_DRAM_CONTROL);
6f82b6eb MF	348	if (!sm501_reg) {
	349	printk(KERN_ERR "%s: ioremap error.\n", __func__);
	350	return;
	351	}
	352
	353	writel(0x000307c2, sm501_reg + SM501_DRAM_CONTROL);
d57d6408	354	iounmap(sm501_reg);
cbe9da02 YS	355	}
cbe9da02 YS	356
63d12e23 MD	357	/* Return the board specific boot mode pin configuration */
	358	static int sh7785lcr_mode_pins(void)
	359	{
	360	int value = 0;
	361
	362	/* These are the factory default settings of S1 and S2.
	363	* If you change these dip switches then you will need to
	364	* adjust the values below as well.
	365	*/
0d4fdbb6 MD	366	value \|= MODE_PIN4; /* Clock Mode 16 */
	367	value \|= MODE_PIN5; /* 32-bit Area0 bus width */
	368	value \|= MODE_PIN6; /* 32-bit Area0 bus width */
	369	value \|= MODE_PIN7; /* Area 0 SRAM interface [fixed] */
	370	value \|= MODE_PIN8; /* Little Endian */
	371	value \|= MODE_PIN9; /* Master Mode */
	372	value \|= MODE_PIN14; /* No PLL step-up */
63d12e23 MD	373
	374	return value;
	375	}
	376
cbe9da02 YS	377	/*
	378	* The Machine Vector
	379	*/
	380	static struct sh_machine_vector mv_sh7785lcr __initmv = {
	381	.mv_name = "SH7785LCR",
	382	.mv_setup = sh7785lcr_setup,
a77b5ac0	383	.mv_clk_init = sh7785lcr_clk_init,
cbe9da02	384	.mv_init_irq = init_sh7785lcr_IRQ,
63d12e23	385	.mv_mode_pins = sh7785lcr_mode_pins,
cbe9da02 YS	386	};
cbe9da02 YS	387