Commit | Line | Data |
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1 | menu "Processor features" |
2 | ||
3 | choice | |
4 | prompt "Endianess selection" | |
5 | default CPU_LITTLE_ENDIAN | |
6 | help | |
7 | Some SuperH machines can be configured for either little or big | |
8 | endian byte order. These modes require different kernels. | |
9 | ||
10 | config CPU_LITTLE_ENDIAN | |
11 | bool "Little Endian" | |
12 | ||
13 | config CPU_BIG_ENDIAN | |
14 | bool "Big Endian" | |
15 | ||
16 | endchoice | |
17 | ||
18 | config SH_FPU | |
19 | bool "FPU support" | |
20 | depends on CPU_HAS_FPU | |
21 | default y | |
22 | help | |
23 | Selecting this option will enable support for SH processors that | |
24 | have FPU units (ie, SH77xx). | |
25 | ||
26 | This option must be set in order to enable the FPU. | |
27 | ||
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28 | config SH64_FPU_DENORM_FLUSH |
29 | bool "Flush floating point denorms to zero" | |
30 | depends on SH_FPU && SUPERH64 | |
31 | ||
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32 | config SH_FPU_EMU |
33 | bool "FPU emulation support" | |
34 | depends on !SH_FPU && EXPERIMENTAL | |
35 | default n | |
36 | help | |
37 | Selecting this option will enable support for software FPU emulation. | |
38 | Most SH-3 users will want to say Y here, whereas most SH-4 users will | |
39 | want to say N. | |
40 | ||
41 | config SH_DSP | |
42 | bool "DSP support" | |
43 | depends on CPU_HAS_DSP | |
44 | default y | |
45 | help | |
46 | Selecting this option will enable support for SH processors that | |
47 | have DSP units (ie, SH2-DSP, SH3-DSP, and SH4AL-DSP). | |
48 | ||
49 | This option must be set in order to enable the DSP. | |
50 | ||
51 | config SH_ADC | |
52 | bool "ADC support" | |
53 | depends on CPU_SH3 | |
54 | default y | |
55 | help | |
56 | Selecting this option will allow the Linux kernel to use SH3 on-chip | |
57 | ADC module. | |
58 | ||
59 | If unsure, say N. | |
60 | ||
61 | config SH_STORE_QUEUES | |
62 | bool "Support for Store Queues" | |
63 | depends on CPU_SH4 | |
64 | help | |
65 | Selecting this option will enable an in-kernel API for manipulating | |
66 | the store queues integrated in the SH-4 processors. | |
67 | ||
68 | config SPECULATIVE_EXECUTION | |
69 | bool "Speculative subroutine return" | |
70 | depends on CPU_SUBTYPE_SH7780 && EXPERIMENTAL | |
71 | help | |
72 | This enables support for a speculative instruction fetch for | |
73 | subroutine return. There are various pitfalls associated with | |
74 | this, as outlined in the SH7780 hardware manual. | |
75 | ||
76 | If unsure, say N. | |
77 | ||
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78 | config SH64_USER_MISALIGNED_FIXUP |
79 | bool "Fixup misaligned loads/stores occurring in user mode" | |
80 | depends on SUPERH64 | |
81 | default y | |
82 | ||
83 | config SH64_ID2815_WORKAROUND | |
84 | bool "Include workaround for SH5-101 cut2 silicon defect ID2815" | |
85 | depends on CPU_SUBTYPE_SH5_101 | |
86 | ||
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87 | config CPU_HAS_INTEVT |
88 | bool | |
89 | ||
90 | config CPU_HAS_MASKREG_IRQ | |
91 | bool | |
92 | ||
93 | config CPU_HAS_IPR_IRQ | |
94 | bool | |
95 | ||
96 | config CPU_HAS_SR_RB | |
97 | bool | |
98 | help | |
99 | This will enable the use of SR.RB register bank usage. Processors | |
100 | that are lacking this bit must have another method in place for | |
101 | accomplishing what is taken care of by the banked registers. | |
102 | ||
103 | See <file:Documentation/sh/register-banks.txt> for further | |
104 | information on SR.RB and register banking in the kernel in general. | |
105 | ||
106 | config CPU_HAS_PTEA | |
107 | bool | |
108 | ||
109 | config CPU_HAS_DSP | |
110 | bool | |
111 | ||
112 | config CPU_HAS_FPU | |
113 | bool | |
114 | ||
115 | endmenu |