[linux-block.git] / arch / s390 / pci / pci_irq.c

// SPDX-License-Identifier: GPL-2.0
#define KMSG_COMPONENT "zpci"
#define pr_fmt(fmt) KMSG_COMPONENT ": " fmt

#include <linux/kernel.h>
#include <linux/irq.h>
#include <linux/kernel_stat.h>
#include <linux/pci.h>
#include <linux/msi.h>
#include <linux/smp.h>

#include <asm/isc.h>
#include <asm/airq.h>

static enum {FLOATING, DIRECTED} irq_delivery;

#define	SIC_IRQ_MODE_ALL		0
#define	SIC_IRQ_MODE_SINGLE		1
#define	SIC_IRQ_MODE_DIRECT		4
#define	SIC_IRQ_MODE_D_ALL		16
#define	SIC_IRQ_MODE_D_SINGLE		17
#define	SIC_IRQ_MODE_SET_CPU		18

/*
 * summary bit vector
 * FLOATING - summary bit per function
 * DIRECTED - summary bit per cpu (only used in fallback path)
 */
static struct airq_iv *zpci_sbv;

/*
 * interrupt bit vectors
 * FLOATING - interrupt bit vector per function
 * DIRECTED - interrupt bit vector per cpu
 */
static struct airq_iv **zpci_ibv;

/* Modify PCI: Register floating adapter interruptions */
static int zpci_set_airq(struct zpci_dev *zdev)
{
	u64 req = ZPCI_CREATE_REQ(zdev->fh, 0, ZPCI_MOD_FC_REG_INT);
	struct zpci_fib fib = {0};
	u8 status;

	fib.fmt0.isc = PCI_ISC;
	fib.fmt0.sum = 1;	/* enable summary notifications */
	fib.fmt0.noi = airq_iv_end(zdev->aibv);
	fib.fmt0.aibv = virt_to_phys(zdev->aibv->vector);
	fib.fmt0.aibvo = 0;	/* each zdev has its own interrupt vector */
	fib.fmt0.aisb = virt_to_phys(zpci_sbv->vector) + (zdev->aisb / 64) * 8;
	fib.fmt0.aisbo = zdev->aisb & 63;

	return zpci_mod_fc(req, &fib, &status) ? -EIO : 0;
}

/* Modify PCI: Unregister floating adapter interruptions */
static int zpci_clear_airq(struct zpci_dev *zdev)
{
	u64 req = ZPCI_CREATE_REQ(zdev->fh, 0, ZPCI_MOD_FC_DEREG_INT);
	struct zpci_fib fib = {0};
	u8 cc, status;

	cc = zpci_mod_fc(req, &fib, &status);
	if (cc == 3 || (cc == 1 && status == 24))
		/* Function already gone or IRQs already deregistered. */
		cc = 0;

	return cc ? -EIO : 0;
}

/* Modify PCI: Register CPU directed interruptions */
static int zpci_set_directed_irq(struct zpci_dev *zdev)
{
	u64 req = ZPCI_CREATE_REQ(zdev->fh, 0, ZPCI_MOD_FC_REG_INT_D);
	struct zpci_fib fib = {0};
	u8 status;

	fib.fmt = 1;
	fib.fmt1.noi = zdev->msi_nr_irqs;
	fib.fmt1.dibvo = zdev->msi_first_bit;

	return zpci_mod_fc(req, &fib, &status) ? -EIO : 0;
}

/* Modify PCI: Unregister CPU directed interruptions */
static int zpci_clear_directed_irq(struct zpci_dev *zdev)
{
	u64 req = ZPCI_CREATE_REQ(zdev->fh, 0, ZPCI_MOD_FC_DEREG_INT_D);
	struct zpci_fib fib = {0};
	u8 cc, status;

	fib.fmt = 1;
	cc = zpci_mod_fc(req, &fib, &status);
	if (cc == 3 || (cc == 1 && status == 24))
		/* Function already gone or IRQs already deregistered. */
		cc = 0;

	return cc ? -EIO : 0;
}

/* Register adapter interruptions */
static int zpci_set_irq(struct zpci_dev *zdev)
{
	int rc;

	if (irq_delivery == DIRECTED)
		rc = zpci_set_directed_irq(zdev);
	else
		rc = zpci_set_airq(zdev);

	if (!rc)
		zdev->irqs_registered = 1;

	return rc;
}

/* Clear adapter interruptions */
static int zpci_clear_irq(struct zpci_dev *zdev)
{
	int rc;

	if (irq_delivery == DIRECTED)
		rc = zpci_clear_directed_irq(zdev);
	else
		rc = zpci_clear_airq(zdev);

	if (!rc)
		zdev->irqs_registered = 0;

	return rc;
}

static int zpci_set_irq_affinity(struct irq_data *data, const struct cpumask *dest,
				 bool force)
{
	struct msi_desc *entry = irq_get_msi_desc(data->irq);
	struct msi_msg msg = entry->msg;
	int cpu_addr = smp_cpu_get_cpu_address(cpumask_first(dest));

	msg.address_lo &= 0xff0000ff;
	msg.address_lo |= (cpu_addr << 8);
	pci_write_msi_msg(data->irq, &msg);

	return IRQ_SET_MASK_OK;
}

static struct irq_chip zpci_irq_chip = {
	.name = "PCI-MSI",
	.irq_unmask = pci_msi_unmask_irq,
	.irq_mask = pci_msi_mask_irq,
};

static void zpci_handle_cpu_local_irq(bool rescan)
{
	struct airq_iv *dibv = zpci_ibv[smp_processor_id()];
	unsigned long bit;
	int irqs_on = 0;

	for (bit = 0;;) {
		/* Scan the directed IRQ bit vector */
		bit = airq_iv_scan(dibv, bit, airq_iv_end(dibv));
		if (bit == -1UL) {
			if (!rescan || irqs_on++)
				/* End of second scan with interrupts on. */
				break;
			/* First scan complete, reenable interrupts. */
			if (zpci_set_irq_ctrl(SIC_IRQ_MODE_D_SINGLE, PCI_ISC))
				break;
			bit = 0;
			continue;
		}
		inc_irq_stat(IRQIO_MSI);
		generic_handle_irq(airq_iv_get_data(dibv, bit));
	}
}

struct cpu_irq_data {
	call_single_data_t csd;
	atomic_t scheduled;
};
static DEFINE_PER_CPU_SHARED_ALIGNED(struct cpu_irq_data, irq_data);

static void zpci_handle_remote_irq(void *data)
{
	atomic_t *scheduled = data;

	do {
		zpci_handle_cpu_local_irq(false);
	} while (atomic_dec_return(scheduled));
}

static void zpci_handle_fallback_irq(void)
{
	struct cpu_irq_data *cpu_data;
	unsigned long cpu;
	int irqs_on = 0;

	for (cpu = 0;;) {
		cpu = airq_iv_scan(zpci_sbv, cpu, airq_iv_end(zpci_sbv));
		if (cpu == -1UL) {
			if (irqs_on++)
				/* End of second scan with interrupts on. */
				break;
			/* First scan complete, reenable interrupts. */
			if (zpci_set_irq_ctrl(SIC_IRQ_MODE_SINGLE, PCI_ISC))
				break;
			cpu = 0;
			continue;
		}
		cpu_data = &per_cpu(irq_data, cpu);
		if (atomic_inc_return(&cpu_data->scheduled) > 1)
			continue;

		INIT_CSD(&cpu_data->csd, zpci_handle_remote_irq, &cpu_data->scheduled);
		smp_call_function_single_async(cpu, &cpu_data->csd);
	}
}

static void zpci_directed_irq_handler(struct airq_struct *airq, bool floating)
{
	if (floating) {
		inc_irq_stat(IRQIO_PCF);
		zpci_handle_fallback_irq();
	} else {
		inc_irq_stat(IRQIO_PCD);
		zpci_handle_cpu_local_irq(true);
	}
}

static void zpci_floating_irq_handler(struct airq_struct *airq, bool floating)
{
	unsigned long si, ai;
	struct airq_iv *aibv;
	int irqs_on = 0;

	inc_irq_stat(IRQIO_PCF);
	for (si = 0;;) {
		/* Scan adapter summary indicator bit vector */
		si = airq_iv_scan(zpci_sbv, si, airq_iv_end(zpci_sbv));
		if (si == -1UL) {
			if (irqs_on++)
				/* End of second scan with interrupts on. */
				break;
			/* First scan complete, reenable interrupts. */
			if (zpci_set_irq_ctrl(SIC_IRQ_MODE_SINGLE, PCI_ISC))
				break;
			si = 0;
			continue;
		}

		/* Scan the adapter interrupt vector for this device. */
		aibv = zpci_ibv[si];
		for (ai = 0;;) {
			ai = airq_iv_scan(aibv, ai, airq_iv_end(aibv));
			if (ai == -1UL)
				break;
			inc_irq_stat(IRQIO_MSI);
			airq_iv_lock(aibv, ai);
			generic_handle_irq(airq_iv_get_data(aibv, ai));
			airq_iv_unlock(aibv, ai);
		}
	}
}

int arch_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type)
{
	struct zpci_dev *zdev = to_zpci(pdev);
	unsigned int hwirq, msi_vecs, cpu;
	unsigned long bit;
	struct msi_desc *msi;
	struct msi_msg msg;
	int cpu_addr;
	int rc, irq;

	zdev->aisb = -1UL;
	zdev->msi_first_bit = -1U;
	if (type == PCI_CAP_ID_MSI && nvec > 1)
		return 1;
	msi_vecs = min_t(unsigned int, nvec, zdev->max_msi);

	if (irq_delivery == DIRECTED) {
		/* Allocate cpu vector bits */
		bit = airq_iv_alloc(zpci_ibv[0], msi_vecs);
		if (bit == -1UL)
			return -EIO;
	} else {
		/* Allocate adapter summary indicator bit */
		bit = airq_iv_alloc_bit(zpci_sbv);
		if (bit == -1UL)
			return -EIO;
		zdev->aisb = bit;

		/* Create adapter interrupt vector */
		zdev->aibv = airq_iv_create(msi_vecs, AIRQ_IV_DATA | AIRQ_IV_BITLOCK);
		if (!zdev->aibv)
			return -ENOMEM;

		/* Wire up shortcut pointer */
		zpci_ibv[bit] = zdev->aibv;
		/* Each function has its own interrupt vector */
		bit = 0;
	}

	/* Request MSI interrupts */
	hwirq = bit;
	msi_for_each_desc(msi, &pdev->dev, MSI_DESC_NOTASSOCIATED) {
		rc = -EIO;
		if (hwirq - bit >= msi_vecs)
			break;
		irq = __irq_alloc_descs(-1, 0, 1, 0, THIS_MODULE,
				(irq_delivery == DIRECTED) ?
				msi->affinity : NULL);
		if (irq < 0)
			return -ENOMEM;
		rc = irq_set_msi_desc(irq, msi);
		if (rc)
			return rc;
		irq_set_chip_and_handler(irq, &zpci_irq_chip,
					 handle_percpu_irq);
		msg.data = hwirq - bit;
		if (irq_delivery == DIRECTED) {
			if (msi->affinity)
				cpu = cpumask_first(&msi->affinity->mask);
			else
				cpu = 0;
			cpu_addr = smp_cpu_get_cpu_address(cpu);

			msg.address_lo = zdev->msi_addr & 0xff0000ff;
			msg.address_lo |= (cpu_addr << 8);

			for_each_possible_cpu(cpu) {
				airq_iv_set_data(zpci_ibv[cpu], hwirq, irq);
			}
		} else {
			msg.address_lo = zdev->msi_addr & 0xffffffff;
			airq_iv_set_data(zdev->aibv, hwirq, irq);
		}
		msg.address_hi = zdev->msi_addr >> 32;
		pci_write_msi_msg(irq, &msg);
		hwirq++;
	}

	zdev->msi_first_bit = bit;
	zdev->msi_nr_irqs = msi_vecs;

	rc = zpci_set_irq(zdev);
	if (rc)
		return rc;

	return (msi_vecs == nvec) ? 0 : msi_vecs;
}

void arch_teardown_msi_irqs(struct pci_dev *pdev)
{
	struct zpci_dev *zdev = to_zpci(pdev);
	struct msi_desc *msi;
	int rc;

	/* Disable interrupts */
	rc = zpci_clear_irq(zdev);
	if (rc)
		return;

	/* Release MSI interrupts */
	msi_for_each_desc(msi, &pdev->dev, MSI_DESC_ASSOCIATED) {
		irq_set_msi_desc(msi->irq, NULL);
		irq_free_desc(msi->irq);
		msi->msg.address_lo = 0;
		msi->msg.address_hi = 0;
		msi->msg.data = 0;
		msi->irq = 0;
	}

	if (zdev->aisb != -1UL) {
		zpci_ibv[zdev->aisb] = NULL;
		airq_iv_free_bit(zpci_sbv, zdev->aisb);
		zdev->aisb = -1UL;
	}
	if (zdev->aibv) {
		airq_iv_release(zdev->aibv);
		zdev->aibv = NULL;
	}

	if ((irq_delivery == DIRECTED) && zdev->msi_first_bit != -1U)
		airq_iv_free(zpci_ibv[0], zdev->msi_first_bit, zdev->msi_nr_irqs);
}

bool arch_restore_msi_irqs(struct pci_dev *pdev)
{
	struct zpci_dev *zdev = to_zpci(pdev);

	if (!zdev->irqs_registered)
		zpci_set_irq(zdev);
	return true;
}

static struct airq_struct zpci_airq = {
	.handler = zpci_floating_irq_handler,
	.isc = PCI_ISC,
};

static void __init cpu_enable_directed_irq(void *unused)
{
	union zpci_sic_iib iib = {{0}};

	iib.cdiib.dibv_addr = (u64) zpci_ibv[smp_processor_id()]->vector;

	__zpci_set_irq_ctrl(SIC_IRQ_MODE_SET_CPU, 0, &iib);
	zpci_set_irq_ctrl(SIC_IRQ_MODE_D_SINGLE, PCI_ISC);
}

static int __init zpci_directed_irq_init(void)
{
	union zpci_sic_iib iib = {{0}};
	unsigned int cpu;

	zpci_sbv = airq_iv_create(num_possible_cpus(), 0);
	if (!zpci_sbv)
		return -ENOMEM;

	iib.diib.isc = PCI_ISC;
	iib.diib.nr_cpus = num_possible_cpus();
	iib.diib.disb_addr = virt_to_phys(zpci_sbv->vector);
	__zpci_set_irq_ctrl(SIC_IRQ_MODE_DIRECT, 0, &iib);

	zpci_ibv = kcalloc(num_possible_cpus(), sizeof(*zpci_ibv),
			   GFP_KERNEL);
	if (!zpci_ibv)
		return -ENOMEM;

	for_each_possible_cpu(cpu) {
		/*
		 * Per CPU IRQ vectors look the same but bit-allocation
		 * is only done on the first vector.
		 */
		zpci_ibv[cpu] = airq_iv_create(cache_line_size() * BITS_PER_BYTE,
					       AIRQ_IV_DATA |
					       AIRQ_IV_CACHELINE |
					       (!cpu ? AIRQ_IV_ALLOC : 0));
		if (!zpci_ibv[cpu])
			return -ENOMEM;
	}
	on_each_cpu(cpu_enable_directed_irq, NULL, 1);

	zpci_irq_chip.irq_set_affinity = zpci_set_irq_affinity;

	return 0;
}

static int __init zpci_floating_irq_init(void)
{
	zpci_ibv = kcalloc(ZPCI_NR_DEVICES, sizeof(*zpci_ibv), GFP_KERNEL);
	if (!zpci_ibv)
		return -ENOMEM;

	zpci_sbv = airq_iv_create(ZPCI_NR_DEVICES, AIRQ_IV_ALLOC);
	if (!zpci_sbv)
		goto out_free;

	return 0;

out_free:
	kfree(zpci_ibv);
	return -ENOMEM;
}

int __init zpci_irq_init(void)
{
	int rc;

	irq_delivery = sclp.has_dirq ? DIRECTED : FLOATING;
	if (s390_pci_force_floating)
		irq_delivery = FLOATING;

	if (irq_delivery == DIRECTED)
		zpci_airq.handler = zpci_directed_irq_handler;

	rc = register_adapter_interrupt(&zpci_airq);
	if (rc)
		goto out;
	/* Set summary to 1 to be called every time for the ISC. */
	*zpci_airq.lsi_ptr = 1;

	switch (irq_delivery) {
	case FLOATING:
		rc = zpci_floating_irq_init();
		break;
	case DIRECTED:
		rc = zpci_directed_irq_init();
		break;
	}

	if (rc)
		goto out_airq;

	/*
	 * Enable floating IRQs (with suppression after one IRQ). When using
	 * directed IRQs this enables the fallback path.
	 */
	zpci_set_irq_ctrl(SIC_IRQ_MODE_SINGLE, PCI_ISC);

	return 0;
out_airq:
	unregister_adapter_interrupt(&zpci_airq);
out:
	return rc;
}

void __init zpci_irq_exit(void)
{
	unsigned int cpu;

	if (irq_delivery == DIRECTED) {
		for_each_possible_cpu(cpu) {
			airq_iv_release(zpci_ibv[cpu]);
		}
	}
	kfree(zpci_ibv);
	if (zpci_sbv)
		airq_iv_release(zpci_sbv);
	unregister_adapter_interrupt(&zpci_airq);
}
Commit	Line	Data
c840927c SO	1	// SPDX-License-Identifier: GPL-2.0
	2	#define KMSG_COMPONENT "zpci"
	3	#define pr_fmt(fmt) KMSG_COMPONENT ": " fmt
	4
	5	#include <linux/kernel.h>
	6	#include <linux/irq.h>
	7	#include <linux/kernel_stat.h>
	8	#include <linux/pci.h>
	9	#include <linux/msi.h>
e979ce7b	10	#include <linux/smp.h>
c840927c SO	11
	12	#include <asm/isc.h>
	13	#include <asm/airq.h>
	14
e979ce7b SO	15	static enum {FLOATING, DIRECTED} irq_delivery;
e979ce7b SO	16
c840927c SO	17	#define SIC_IRQ_MODE_ALL 0
c840927c SO	18	#define SIC_IRQ_MODE_SINGLE 1
e979ce7b SO	19	#define SIC_IRQ_MODE_DIRECT 4
	20	#define SIC_IRQ_MODE_D_ALL 16
	21	#define SIC_IRQ_MODE_D_SINGLE 17
	22	#define SIC_IRQ_MODE_SET_CPU 18
c840927c	23
b1f54864	24	/*
e979ce7b SO	25	* summary bit vector
	26	* FLOATING - summary bit per function
	27	* DIRECTED - summary bit per cpu (only used in fallback path)
b1f54864 SO	28	*/
	29	static struct airq_iv *zpci_sbv;
	30
	31	/*
e979ce7b SO	32	* interrupt bit vectors
	33	* FLOATING - interrupt bit vector per function
	34	* DIRECTED - interrupt bit vector per cpu
b1f54864 SO	35	*/
b1f54864 SO	36	static struct airq_iv **zpci_ibv;
c840927c	37
c1e18c17	38	/* Modify PCI: Register floating adapter interruptions */
c840927c SO	39	static int zpci_set_airq(struct zpci_dev *zdev)
	40	{
	41	u64 req = ZPCI_CREATE_REQ(zdev->fh, 0, ZPCI_MOD_FC_REG_INT);
	42	struct zpci_fib fib = {0};
	43	u8 status;
	44
e979ce7b SO	45	fib.fmt0.isc = PCI_ISC;
	46	fib.fmt0.sum = 1; /* enable summary notifications */
	47	fib.fmt0.noi = airq_iv_end(zdev->aibv);
4e4dc65a	48	fib.fmt0.aibv = virt_to_phys(zdev->aibv->vector);
e979ce7b	49	fib.fmt0.aibvo = 0; /* each zdev has its own interrupt vector */
4e4dc65a	50	fib.fmt0.aisb = virt_to_phys(zpci_sbv->vector) + (zdev->aisb / 64) * 8;
e979ce7b	51	fib.fmt0.aisbo = zdev->aisb & 63;
c840927c SO	52
	53	return zpci_mod_fc(req, &fib, &status) ? -EIO : 0;
	54	}
	55
c1e18c17	56	/* Modify PCI: Unregister floating adapter interruptions */
c840927c SO	57	static int zpci_clear_airq(struct zpci_dev *zdev)
	58	{
	59	u64 req = ZPCI_CREATE_REQ(zdev->fh, 0, ZPCI_MOD_FC_DEREG_INT);
	60	struct zpci_fib fib = {0};
	61	u8 cc, status;
	62
	63	cc = zpci_mod_fc(req, &fib, &status);
	64	if (cc == 3 \|\| (cc == 1 && status == 24))
	65	/* Function already gone or IRQs already deregistered. */
	66	cc = 0;
	67
	68	return cc ? -EIO : 0;
	69	}
	70
e979ce7b SO	71	/* Modify PCI: Register CPU directed interruptions */
	72	static int zpci_set_directed_irq(struct zpci_dev *zdev)
	73	{
	74	u64 req = ZPCI_CREATE_REQ(zdev->fh, 0, ZPCI_MOD_FC_REG_INT_D);
	75	struct zpci_fib fib = {0};
	76	u8 status;
	77
	78	fib.fmt = 1;
	79	fib.fmt1.noi = zdev->msi_nr_irqs;
	80	fib.fmt1.dibvo = zdev->msi_first_bit;
	81
	82	return zpci_mod_fc(req, &fib, &status) ? -EIO : 0;
	83	}
	84
	85	/* Modify PCI: Unregister CPU directed interruptions */
	86	static int zpci_clear_directed_irq(struct zpci_dev *zdev)
	87	{
	88	u64 req = ZPCI_CREATE_REQ(zdev->fh, 0, ZPCI_MOD_FC_DEREG_INT_D);
	89	struct zpci_fib fib = {0};
	90	u8 cc, status;
	91
	92	fib.fmt = 1;
	93	cc = zpci_mod_fc(req, &fib, &status);
	94	if (cc == 3 \|\| (cc == 1 && status == 24))
	95	/* Function already gone or IRQs already deregistered. */
	96	cc = 0;
	97
	98	return cc ? -EIO : 0;
	99	}
	100
c1e18c17	101	/* Register adapter interruptions */
6c2797cd	102	static int zpci_set_irq(struct zpci_dev *zdev)
c1e18c17 NS	103	{
	104	int rc;
	105
	106	if (irq_delivery == DIRECTED)
	107	rc = zpci_set_directed_irq(zdev);
	108	else
	109	rc = zpci_set_airq(zdev);
	110
	111	if (!rc)
	112	zdev->irqs_registered = 1;
	113
	114	return rc;
	115	}
	116
	117	/* Clear adapter interruptions */
6c2797cd	118	static int zpci_clear_irq(struct zpci_dev *zdev)
c1e18c17 NS	119	{
	120	int rc;
	121
	122	if (irq_delivery == DIRECTED)
	123	rc = zpci_clear_directed_irq(zdev);
	124	else
	125	rc = zpci_clear_airq(zdev);
	126
	127	if (!rc)
	128	zdev->irqs_registered = 0;
	129
	130	return rc;
	131	}
	132
e979ce7b SO	133	static int zpci_set_irq_affinity(struct irq_data data, const struct cpumask dest,
	134	bool force)
	135	{
	136	struct msi_desc *entry = irq_get_msi_desc(data->irq);
	137	struct msi_msg msg = entry->msg;
a2bd4097	138	int cpu_addr = smp_cpu_get_cpu_address(cpumask_first(dest));
e979ce7b SO	139
e979ce7b SO	140	msg.address_lo &= 0xff0000ff;
a2bd4097	141	msg.address_lo \|= (cpu_addr << 8);
e979ce7b SO	142	pci_write_msi_msg(data->irq, &msg);
	143
	144	return IRQ_SET_MASK_OK;
	145	}
	146
c840927c	147	static struct irq_chip zpci_irq_chip = {
914b7dd0	148	.name = "PCI-MSI",
c840927c SO	149	.irq_unmask = pci_msi_unmask_irq,
	150	.irq_mask = pci_msi_mask_irq,
	151	};
	152
e979ce7b SO	153	static void zpci_handle_cpu_local_irq(bool rescan)
	154	{
	155	struct airq_iv *dibv = zpci_ibv[smp_processor_id()];
	156	unsigned long bit;
	157	int irqs_on = 0;
	158
	159	for (bit = 0;;) {
	160	/* Scan the directed IRQ bit vector */
	161	bit = airq_iv_scan(dibv, bit, airq_iv_end(dibv));
	162	if (bit == -1UL) {
	163	if (!rescan \|\| irqs_on++)
	164	/* End of second scan with interrupts on. */
	165	break;
	166	/* First scan complete, reenable interrupts. */
	167	if (zpci_set_irq_ctrl(SIC_IRQ_MODE_D_SINGLE, PCI_ISC))
	168	break;
	169	bit = 0;
	170	continue;
	171	}
	172	inc_irq_stat(IRQIO_MSI);
	173	generic_handle_irq(airq_iv_get_data(dibv, bit));
	174	}
	175	}
	176
	177	struct cpu_irq_data {
	178	call_single_data_t csd;
	179	atomic_t scheduled;
	180	};
	181	static DEFINE_PER_CPU_SHARED_ALIGNED(struct cpu_irq_data, irq_data);
	182
	183	static void zpci_handle_remote_irq(void *data)
	184	{
	185	atomic_t *scheduled = data;
	186
	187	do {
	188	zpci_handle_cpu_local_irq(false);
	189	} while (atomic_dec_return(scheduled));
	190	}
	191
	192	static void zpci_handle_fallback_irq(void)
	193	{
	194	struct cpu_irq_data *cpu_data;
	195	unsigned long cpu;
	196	int irqs_on = 0;
	197
	198	for (cpu = 0;;) {
	199	cpu = airq_iv_scan(zpci_sbv, cpu, airq_iv_end(zpci_sbv));
	200	if (cpu == -1UL) {
	201	if (irqs_on++)
	202	/* End of second scan with interrupts on. */
	203	break;
	204	/* First scan complete, reenable interrupts. */
	205	if (zpci_set_irq_ctrl(SIC_IRQ_MODE_SINGLE, PCI_ISC))
	206	break;
	207	cpu = 0;
	208	continue;
	209	}
	210	cpu_data = &per_cpu(irq_data, cpu);
	211	if (atomic_inc_return(&cpu_data->scheduled) > 1)
	212	continue;
	213
545b8c8d	214	INIT_CSD(&cpu_data->csd, zpci_handle_remote_irq, &cpu_data->scheduled);
e979ce7b SO	215	smp_call_function_single_async(cpu, &cpu_data->csd);
	216	}
	217	}
	218
	219	static void zpci_directed_irq_handler(struct airq_struct *airq, bool floating)
	220	{
07e3ec3a SO	221	if (floating) {
07e3ec3a SO	222	inc_irq_stat(IRQIO_PCF);
e979ce7b	223	zpci_handle_fallback_irq();
07e3ec3a SO	224	} else {
07e3ec3a SO	225	inc_irq_stat(IRQIO_PCD);
e979ce7b	226	zpci_handle_cpu_local_irq(true);
07e3ec3a	227	}
e979ce7b SO	228	}
	229
	230	static void zpci_floating_irq_handler(struct airq_struct *airq, bool floating)
c840927c SO	231	{
	232	unsigned long si, ai;
	233	struct airq_iv *aibv;
	234	int irqs_on = 0;
	235
07e3ec3a	236	inc_irq_stat(IRQIO_PCF);
c840927c SO	237	for (si = 0;;) {
c840927c SO	238	/* Scan adapter summary indicator bit vector */
b1f54864	239	si = airq_iv_scan(zpci_sbv, si, airq_iv_end(zpci_sbv));
c840927c SO	240	if (si == -1UL) {
	241	if (irqs_on++)
	242	/* End of second scan with interrupts on. */
	243	break;
	244	/* First scan complete, reenable interrupts. */
e979ce7b	245	if (zpci_set_irq_ctrl(SIC_IRQ_MODE_SINGLE, PCI_ISC))
c840927c SO	246	break;
	247	si = 0;
	248	continue;
	249	}
	250
	251	/* Scan the adapter interrupt vector for this device. */
b1f54864	252	aibv = zpci_ibv[si];
c840927c SO	253	for (ai = 0;;) {
	254	ai = airq_iv_scan(aibv, ai, airq_iv_end(aibv));
	255	if (ai == -1UL)
	256	break;
	257	inc_irq_stat(IRQIO_MSI);
	258	airq_iv_lock(aibv, ai);
	259	generic_handle_irq(airq_iv_get_data(aibv, ai));
	260	airq_iv_unlock(aibv, ai);
	261	}
	262	}
	263	}
	264
	265	int arch_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type)
	266	{
	267	struct zpci_dev *zdev = to_zpci(pdev);
e979ce7b SO	268	unsigned int hwirq, msi_vecs, cpu;
e979ce7b SO	269	unsigned long bit;
c840927c SO	270	struct msi_desc *msi;
c840927c SO	271	struct msi_msg msg;
a2bd4097	272	int cpu_addr;
c840927c SO	273	int rc, irq;
	274
	275	zdev->aisb = -1UL;
e979ce7b	276	zdev->msi_first_bit = -1U;
c840927c SO	277	if (type == PCI_CAP_ID_MSI && nvec > 1)
	278	return 1;
	279	msi_vecs = min_t(unsigned int, nvec, zdev->max_msi);
	280
e979ce7b SO	281	if (irq_delivery == DIRECTED) {
	282	/* Allocate cpu vector bits */
	283	bit = airq_iv_alloc(zpci_ibv[0], msi_vecs);
	284	if (bit == -1UL)
	285	return -EIO;
	286	} else {
	287	/* Allocate adapter summary indicator bit */
	288	bit = airq_iv_alloc_bit(zpci_sbv);
	289	if (bit == -1UL)
	290	return -EIO;
	291	zdev->aisb = bit;
	292
	293	/* Create adapter interrupt vector */
	294	zdev->aibv = airq_iv_create(msi_vecs, AIRQ_IV_DATA \| AIRQ_IV_BITLOCK);
	295	if (!zdev->aibv)
	296	return -ENOMEM;
c840927c	297
e979ce7b SO	298	/* Wire up shortcut pointer */
	299	zpci_ibv[bit] = zdev->aibv;
	300	/* Each function has its own interrupt vector */
	301	bit = 0;
	302	}
c840927c SO	303
c840927c SO	304	/* Request MSI interrupts */
e979ce7b	305	hwirq = bit;
2ca5e908	306	msi_for_each_desc(msi, &pdev->dev, MSI_DESC_NOTASSOCIATED) {
e979ce7b SO	307	rc = -EIO;
e979ce7b SO	308	if (hwirq - bit >= msi_vecs)
c840927c	309	break;
86dbf32d NS	310	irq = __irq_alloc_descs(-1, 0, 1, 0, THIS_MODULE,
	311	(irq_delivery == DIRECTED) ?
	312	msi->affinity : NULL);
c840927c SO	313	if (irq < 0)
	314	return -ENOMEM;
	315	rc = irq_set_msi_desc(irq, msi);
	316	if (rc)
	317	return rc;
	318	irq_set_chip_and_handler(irq, &zpci_irq_chip,
e979ce7b	319	handle_percpu_irq);
cf2c4a3f	320	msg.data = hwirq - bit;
e979ce7b	321	if (irq_delivery == DIRECTED) {
a2bd4097 AG	322	if (msi->affinity)
	323	cpu = cpumask_first(&msi->affinity->mask);
	324	else
	325	cpu = 0;
	326	cpu_addr = smp_cpu_get_cpu_address(cpu);
	327
e979ce7b	328	msg.address_lo = zdev->msi_addr & 0xff0000ff;
a2bd4097 AG	329	msg.address_lo \|= (cpu_addr << 8);
a2bd4097 AG	330
e979ce7b SO	331	for_each_possible_cpu(cpu) {
	332	airq_iv_set_data(zpci_ibv[cpu], hwirq, irq);
	333	}
	334	} else {
	335	msg.address_lo = zdev->msi_addr & 0xffffffff;
	336	airq_iv_set_data(zdev->aibv, hwirq, irq);
	337	}
c840927c SO	338	msg.address_hi = zdev->msi_addr >> 32;
c840927c SO	339	pci_write_msi_msg(irq, &msg);
c840927c SO	340	hwirq++;
	341	}
	342
e979ce7b SO	343	zdev->msi_first_bit = bit;
	344	zdev->msi_nr_irqs = msi_vecs;
	345
c1e18c17	346	rc = zpci_set_irq(zdev);
c840927c SO	347	if (rc)
	348	return rc;
	349
	350	return (msi_vecs == nvec) ? 0 : msi_vecs;
	351	}
	352
	353	void arch_teardown_msi_irqs(struct pci_dev *pdev)
	354	{
	355	struct zpci_dev *zdev = to_zpci(pdev);
	356	struct msi_desc *msi;
	357	int rc;
	358
e979ce7b	359	/* Disable interrupts */
c1e18c17	360	rc = zpci_clear_irq(zdev);
c840927c SO	361	if (rc)
	362	return;
	363
	364	/* Release MSI interrupts */
2ca5e908	365	msi_for_each_desc(msi, &pdev->dev, MSI_DESC_ASSOCIATED) {
c840927c SO	366	irq_set_msi_desc(msi->irq, NULL);
	367	irq_free_desc(msi->irq);
	368	msi->msg.address_lo = 0;
	369	msi->msg.address_hi = 0;
	370	msi->msg.data = 0;
	371	msi->irq = 0;
	372	}
	373
	374	if (zdev->aisb != -1UL) {
b1f54864 SO	375	zpci_ibv[zdev->aisb] = NULL;
b1f54864 SO	376	airq_iv_free_bit(zpci_sbv, zdev->aisb);
c840927c SO	377	zdev->aisb = -1UL;
	378	}
	379	if (zdev->aibv) {
	380	airq_iv_release(zdev->aibv);
	381	zdev->aibv = NULL;
	382	}
e979ce7b SO	383
	384	if ((irq_delivery == DIRECTED) && zdev->msi_first_bit != -1U)
	385	airq_iv_free(zpci_ibv[0], zdev->msi_first_bit, zdev->msi_nr_irqs);
c840927c SO	386	}
c840927c SO	387
ae72f315	388	bool arch_restore_msi_irqs(struct pci_dev *pdev)
da995d53 NS	389	{
	390	struct zpci_dev *zdev = to_zpci(pdev);
	391
	392	if (!zdev->irqs_registered)
	393	zpci_set_irq(zdev);
ae72f315	394	return true;
da995d53 NS	395	}
da995d53 NS	396
c840927c	397	static struct airq_struct zpci_airq = {
e979ce7b	398	.handler = zpci_floating_irq_handler,
c840927c SO	399	.isc = PCI_ISC,
	400	};
	401
e979ce7b	402	static void __init cpu_enable_directed_irq(void *unused)
c840927c	403	{
e979ce7b	404	union zpci_sic_iib iib = {{0}};
c840927c	405
e979ce7b SO	406	iib.cdiib.dibv_addr = (u64) zpci_ibv[smp_processor_id()]->vector;
	407
	408	__zpci_set_irq_ctrl(SIC_IRQ_MODE_SET_CPU, 0, &iib);
	409	zpci_set_irq_ctrl(SIC_IRQ_MODE_D_SINGLE, PCI_ISC);
	410	}
	411
	412	static int __init zpci_directed_irq_init(void)
	413	{
	414	union zpci_sic_iib iib = {{0}};
	415	unsigned int cpu;
	416
	417	zpci_sbv = airq_iv_create(num_possible_cpus(), 0);
	418	if (!zpci_sbv)
	419	return -ENOMEM;
	420
	421	iib.diib.isc = PCI_ISC;
	422	iib.diib.nr_cpus = num_possible_cpus();
4e4dc65a	423	iib.diib.disb_addr = virt_to_phys(zpci_sbv->vector);
e979ce7b SO	424	__zpci_set_irq_ctrl(SIC_IRQ_MODE_DIRECT, 0, &iib);
	425
	426	zpci_ibv = kcalloc(num_possible_cpus(), sizeof(*zpci_ibv),
	427	GFP_KERNEL);
	428	if (!zpci_ibv)
	429	return -ENOMEM;
	430
	431	for_each_possible_cpu(cpu) {
	432	/*
	433	* Per CPU IRQ vectors look the same but bit-allocation
	434	* is only done on the first vector.
	435	*/
	436	zpci_ibv[cpu] = airq_iv_create(cache_line_size() * BITS_PER_BYTE,
	437	AIRQ_IV_DATA \|
	438	AIRQ_IV_CACHELINE \|
	439	(!cpu ? AIRQ_IV_ALLOC : 0));
	440	if (!zpci_ibv[cpu])
	441	return -ENOMEM;
	442	}
	443	on_each_cpu(cpu_enable_directed_irq, NULL, 1);
c840927c	444
e979ce7b SO	445	zpci_irq_chip.irq_set_affinity = zpci_set_irq_affinity;
	446
	447	return 0;
	448	}
	449
	450	static int __init zpci_floating_irq_init(void)
	451	{
b1f54864 SO	452	zpci_ibv = kcalloc(ZPCI_NR_DEVICES, sizeof(*zpci_ibv), GFP_KERNEL);
b1f54864 SO	453	if (!zpci_ibv)
e979ce7b	454	return -ENOMEM;
c840927c	455
b1f54864 SO	456	zpci_sbv = airq_iv_create(ZPCI_NR_DEVICES, AIRQ_IV_ALLOC);
	457	if (!zpci_sbv)
	458	goto out_free;
	459
c840927c SO	460	return 0;
c840927c SO	461
b1f54864 SO	462	out_free:
b1f54864 SO	463	kfree(zpci_ibv);
e979ce7b SO	464	return -ENOMEM;
	465	}
	466
	467	int __init zpci_irq_init(void)
	468	{
	469	int rc;
	470
	471	irq_delivery = sclp.has_dirq ? DIRECTED : FLOATING;
fbfe07d4 SO	472	if (s390_pci_force_floating)
	473	irq_delivery = FLOATING;
	474
e979ce7b SO	475	if (irq_delivery == DIRECTED)
	476	zpci_airq.handler = zpci_directed_irq_handler;
	477
	478	rc = register_adapter_interrupt(&zpci_airq);
	479	if (rc)
	480	goto out;
	481	/* Set summary to 1 to be called every time for the ISC. */
	482	*zpci_airq.lsi_ptr = 1;
	483
	484	switch (irq_delivery) {
	485	case FLOATING:
	486	rc = zpci_floating_irq_init();
	487	break;
	488	case DIRECTED:
	489	rc = zpci_directed_irq_init();
	490	break;
	491	}
	492
	493	if (rc)
	494	goto out_airq;
	495
	496	/*
	497	* Enable floating IRQs (with suppression after one IRQ). When using
	498	* directed IRQs this enables the fallback path.
	499	*/
	500	zpci_set_irq_ctrl(SIC_IRQ_MODE_SINGLE, PCI_ISC);
	501
	502	return 0;
c840927c SO	503	out_airq:
	504	unregister_adapter_interrupt(&zpci_airq);
	505	out:
	506	return rc;
	507	}
	508
	509	void __init zpci_irq_exit(void)
	510	{
e979ce7b SO	511	unsigned int cpu;
	512
	513	if (irq_delivery == DIRECTED) {
	514	for_each_possible_cpu(cpu) {
	515	airq_iv_release(zpci_ibv[cpu]);
	516	}
	517	}
b1f54864	518	kfree(zpci_ibv);
e979ce7b SO	519	if (zpci_sbv)
e979ce7b SO	520	airq_iv_release(zpci_sbv);
c840927c SO	521	unregister_adapter_interrupt(&zpci_airq);
c840927c SO	522	}