Commit | Line | Data |
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d809aa23 | 1 | // SPDX-License-Identifier: GPL-2.0 |
453423dc | 2 | /* |
a53c8fab | 3 | * handling privileged instructions |
453423dc | 4 | * |
a37cb07a | 5 | * Copyright IBM Corp. 2008, 2018 |
453423dc | 6 | * |
453423dc CB |
7 | * Author(s): Carsten Otte <cotte@de.ibm.com> |
8 | * Christian Borntraeger <borntraeger@de.ibm.com> | |
9 | */ | |
10 | ||
11 | #include <linux/kvm.h> | |
5a0e3ad6 | 12 | #include <linux/gfp.h> |
453423dc | 13 | #include <linux/errno.h> |
b13b5dc7 | 14 | #include <linux/compat.h> |
589ee628 IM |
15 | #include <linux/mm_types.h> |
16 | ||
7c959e82 | 17 | #include <asm/asm-offsets.h> |
e769ece3 | 18 | #include <asm/facility.h> |
453423dc CB |
19 | #include <asm/current.h> |
20 | #include <asm/debug.h> | |
21 | #include <asm/ebcdic.h> | |
22 | #include <asm/sysinfo.h> | |
69d0d3a3 | 23 | #include <asm/pgtable.h> |
190df4a2 | 24 | #include <asm/page-states.h> |
69d0d3a3 | 25 | #include <asm/pgalloc.h> |
1e133ab2 | 26 | #include <asm/gmap.h> |
69d0d3a3 | 27 | #include <asm/io.h> |
48a3e950 CH |
28 | #include <asm/ptrace.h> |
29 | #include <asm/compat.h> | |
a7e19ab5 | 30 | #include <asm/sclp.h> |
453423dc CB |
31 | #include "gaccess.h" |
32 | #include "kvm-s390.h" | |
5786fffa | 33 | #include "trace.h" |
453423dc | 34 | |
80cd8763 FZ |
35 | static int handle_ri(struct kvm_vcpu *vcpu) |
36 | { | |
a37cb07a CB |
37 | vcpu->stat.instruction_ri++; |
38 | ||
80cd8763 | 39 | if (test_kvm_facility(vcpu->kvm, 64)) { |
4d5f2c04 | 40 | VCPU_EVENT(vcpu, 3, "%s", "ENABLE: RI (lazy)"); |
0c9d8683 | 41 | vcpu->arch.sie_block->ecb3 |= ECB3_RI; |
80cd8763 FZ |
42 | kvm_s390_retry_instr(vcpu); |
43 | return 0; | |
44 | } else | |
45 | return kvm_s390_inject_program_int(vcpu, PGM_OPERATION); | |
46 | } | |
47 | ||
48 | int kvm_s390_handle_aa(struct kvm_vcpu *vcpu) | |
49 | { | |
50 | if ((vcpu->arch.sie_block->ipa & 0xf) <= 4) | |
51 | return handle_ri(vcpu); | |
52 | else | |
53 | return -EOPNOTSUPP; | |
54 | } | |
55 | ||
4e0b1ab7 FZ |
56 | static int handle_gs(struct kvm_vcpu *vcpu) |
57 | { | |
a37cb07a CB |
58 | vcpu->stat.instruction_gs++; |
59 | ||
4e0b1ab7 FZ |
60 | if (test_kvm_facility(vcpu->kvm, 133)) { |
61 | VCPU_EVENT(vcpu, 3, "%s", "ENABLE: GS (lazy)"); | |
62 | preempt_disable(); | |
63 | __ctl_set_bit(2, 4); | |
64 | current->thread.gs_cb = (struct gs_cb *)&vcpu->run->s.regs.gscb; | |
65 | restore_gs_cb(current->thread.gs_cb); | |
66 | preempt_enable(); | |
67 | vcpu->arch.sie_block->ecb |= ECB_GS; | |
68 | vcpu->arch.sie_block->ecd |= ECD_HOSTREGMGMT; | |
69 | vcpu->arch.gs_enabled = 1; | |
70 | kvm_s390_retry_instr(vcpu); | |
71 | return 0; | |
72 | } else | |
73 | return kvm_s390_inject_program_int(vcpu, PGM_OPERATION); | |
74 | } | |
75 | ||
76 | int kvm_s390_handle_e3(struct kvm_vcpu *vcpu) | |
77 | { | |
78 | int code = vcpu->arch.sie_block->ipb & 0xff; | |
79 | ||
80 | if (code == 0x49 || code == 0x4d) | |
81 | return handle_gs(vcpu); | |
82 | else | |
83 | return -EOPNOTSUPP; | |
84 | } | |
6a3f95a6 TH |
85 | /* Handle SCK (SET CLOCK) interception */ |
86 | static int handle_set_clock(struct kvm_vcpu *vcpu) | |
87 | { | |
0e7def5f | 88 | struct kvm_s390_vm_tod_clock gtod = { 0 }; |
25ed1675 | 89 | int rc; |
27f67f87 | 90 | u8 ar; |
0e7def5f | 91 | u64 op2; |
6a3f95a6 | 92 | |
a37cb07a CB |
93 | vcpu->stat.instruction_sck++; |
94 | ||
6a3f95a6 TH |
95 | if (vcpu->arch.sie_block->gpsw.mask & PSW_MASK_PSTATE) |
96 | return kvm_s390_inject_program_int(vcpu, PGM_PRIVILEGED_OP); | |
97 | ||
8ae04b8f | 98 | op2 = kvm_s390_get_base_disp_s(vcpu, &ar); |
6a3f95a6 TH |
99 | if (op2 & 7) /* Operand must be on a doubleword boundary */ |
100 | return kvm_s390_inject_program_int(vcpu, PGM_SPECIFICATION); | |
0e7def5f | 101 | rc = read_guest(vcpu, op2, ar, >od.tod, sizeof(gtod.tod)); |
0e7a3f94 HC |
102 | if (rc) |
103 | return kvm_s390_inject_prog_cond(vcpu, rc); | |
6a3f95a6 | 104 | |
0e7def5f DH |
105 | VCPU_EVENT(vcpu, 3, "SCK: setting guest TOD to 0x%llx", gtod.tod); |
106 | kvm_s390_set_tod_clock(vcpu->kvm, >od); | |
6a3f95a6 TH |
107 | |
108 | kvm_s390_set_psw_cc(vcpu, 0); | |
109 | return 0; | |
110 | } | |
111 | ||
453423dc CB |
112 | static int handle_set_prefix(struct kvm_vcpu *vcpu) |
113 | { | |
453423dc | 114 | u64 operand2; |
665170cb HC |
115 | u32 address; |
116 | int rc; | |
27f67f87 | 117 | u8 ar; |
453423dc CB |
118 | |
119 | vcpu->stat.instruction_spx++; | |
120 | ||
5087dfa6 TH |
121 | if (vcpu->arch.sie_block->gpsw.mask & PSW_MASK_PSTATE) |
122 | return kvm_s390_inject_program_int(vcpu, PGM_PRIVILEGED_OP); | |
123 | ||
8ae04b8f | 124 | operand2 = kvm_s390_get_base_disp_s(vcpu, &ar); |
453423dc CB |
125 | |
126 | /* must be word boundary */ | |
db4a29cb HC |
127 | if (operand2 & 3) |
128 | return kvm_s390_inject_program_int(vcpu, PGM_SPECIFICATION); | |
453423dc CB |
129 | |
130 | /* get the value */ | |
8ae04b8f | 131 | rc = read_guest(vcpu, operand2, ar, &address, sizeof(address)); |
665170cb HC |
132 | if (rc) |
133 | return kvm_s390_inject_prog_cond(vcpu, rc); | |
134 | ||
135 | address &= 0x7fffe000u; | |
136 | ||
137 | /* | |
138 | * Make sure the new value is valid memory. We only need to check the | |
139 | * first page, since address is 8k aligned and memory pieces are always | |
140 | * at least 1MB aligned and have at least a size of 1MB. | |
141 | */ | |
142 | if (kvm_is_error_gpa(vcpu->kvm, address)) | |
db4a29cb | 143 | return kvm_s390_inject_program_int(vcpu, PGM_ADDRESSING); |
453423dc | 144 | |
8d26cf7b | 145 | kvm_s390_set_prefix(vcpu, address); |
5786fffa | 146 | trace_kvm_s390_handle_prefix(vcpu, 1, address); |
453423dc CB |
147 | return 0; |
148 | } | |
149 | ||
150 | static int handle_store_prefix(struct kvm_vcpu *vcpu) | |
151 | { | |
453423dc CB |
152 | u64 operand2; |
153 | u32 address; | |
f748f4a7 | 154 | int rc; |
27f67f87 | 155 | u8 ar; |
453423dc CB |
156 | |
157 | vcpu->stat.instruction_stpx++; | |
b1c571a5 | 158 | |
5087dfa6 TH |
159 | if (vcpu->arch.sie_block->gpsw.mask & PSW_MASK_PSTATE) |
160 | return kvm_s390_inject_program_int(vcpu, PGM_PRIVILEGED_OP); | |
161 | ||
8ae04b8f | 162 | operand2 = kvm_s390_get_base_disp_s(vcpu, &ar); |
453423dc CB |
163 | |
164 | /* must be word boundary */ | |
db4a29cb HC |
165 | if (operand2 & 3) |
166 | return kvm_s390_inject_program_int(vcpu, PGM_SPECIFICATION); | |
453423dc | 167 | |
fda902cb | 168 | address = kvm_s390_get_prefix(vcpu); |
453423dc CB |
169 | |
170 | /* get the value */ | |
8ae04b8f | 171 | rc = write_guest(vcpu, operand2, ar, &address, sizeof(address)); |
f748f4a7 HC |
172 | if (rc) |
173 | return kvm_s390_inject_prog_cond(vcpu, rc); | |
453423dc | 174 | |
7cbde76b | 175 | VCPU_EVENT(vcpu, 3, "STPX: storing prefix 0x%x into 0x%llx", address, operand2); |
5786fffa | 176 | trace_kvm_s390_handle_prefix(vcpu, 0, address); |
453423dc CB |
177 | return 0; |
178 | } | |
179 | ||
180 | static int handle_store_cpu_address(struct kvm_vcpu *vcpu) | |
181 | { | |
8b96de0e HC |
182 | u16 vcpu_id = vcpu->vcpu_id; |
183 | u64 ga; | |
184 | int rc; | |
27f67f87 | 185 | u8 ar; |
453423dc CB |
186 | |
187 | vcpu->stat.instruction_stap++; | |
b1c571a5 | 188 | |
5087dfa6 TH |
189 | if (vcpu->arch.sie_block->gpsw.mask & PSW_MASK_PSTATE) |
190 | return kvm_s390_inject_program_int(vcpu, PGM_PRIVILEGED_OP); | |
191 | ||
8ae04b8f | 192 | ga = kvm_s390_get_base_disp_s(vcpu, &ar); |
453423dc | 193 | |
8b96de0e | 194 | if (ga & 1) |
db4a29cb | 195 | return kvm_s390_inject_program_int(vcpu, PGM_SPECIFICATION); |
453423dc | 196 | |
8ae04b8f | 197 | rc = write_guest(vcpu, ga, ar, &vcpu_id, sizeof(vcpu_id)); |
8b96de0e HC |
198 | if (rc) |
199 | return kvm_s390_inject_prog_cond(vcpu, rc); | |
453423dc | 200 | |
7cbde76b | 201 | VCPU_EVENT(vcpu, 3, "STAP: storing cpu address (%u) to 0x%llx", vcpu_id, ga); |
8b96de0e | 202 | trace_kvm_s390_handle_stap(vcpu, ga); |
453423dc CB |
203 | return 0; |
204 | } | |
205 | ||
730cd632 | 206 | int kvm_s390_skey_check_enable(struct kvm_vcpu *vcpu) |
693ffc08 | 207 | { |
3ac8e380 | 208 | int rc = 0; |
730cd632 | 209 | struct kvm_s390_sie_block *sie_block = vcpu->arch.sie_block; |
11ddcd41 DH |
210 | |
211 | trace_kvm_s390_skey_related_inst(vcpu); | |
730cd632 | 212 | if (!(sie_block->ictl & (ICTL_ISKE | ICTL_SSKE | ICTL_RRBE)) && |
8d5fb0dc | 213 | !kvm_s390_test_cpuflags(vcpu, CPUSTAT_KSS)) |
3ac8e380 | 214 | return rc; |
693ffc08 | 215 | |
3ac8e380 | 216 | rc = s390_enable_skey(); |
11ddcd41 | 217 | VCPU_EVENT(vcpu, 3, "enabling storage keys for guest: %d", rc); |
730cd632 | 218 | if (!rc) { |
8d5fb0dc | 219 | if (kvm_s390_test_cpuflags(vcpu, CPUSTAT_KSS)) |
9daecfc6 | 220 | kvm_s390_clear_cpuflags(vcpu, CPUSTAT_KSS); |
730cd632 FA |
221 | else |
222 | sie_block->ictl &= ~(ICTL_ISKE | ICTL_SSKE | | |
223 | ICTL_RRBE); | |
224 | } | |
3ac8e380 | 225 | return rc; |
693ffc08 DD |
226 | } |
227 | ||
a7e19ab5 | 228 | static int try_handle_skey(struct kvm_vcpu *vcpu) |
453423dc | 229 | { |
11ddcd41 | 230 | int rc; |
693ffc08 | 231 | |
730cd632 | 232 | rc = kvm_s390_skey_check_enable(vcpu); |
3ac8e380 DD |
233 | if (rc) |
234 | return rc; | |
a7e19ab5 DH |
235 | if (sclp.has_skey) { |
236 | /* with storage-key facility, SIE interprets it for us */ | |
237 | kvm_s390_retry_instr(vcpu); | |
238 | VCPU_EVENT(vcpu, 4, "%s", "retrying storage key operation"); | |
239 | return -EAGAIN; | |
240 | } | |
a7e19ab5 DH |
241 | return 0; |
242 | } | |
5087dfa6 | 243 | |
a7e19ab5 DH |
244 | static int handle_iske(struct kvm_vcpu *vcpu) |
245 | { | |
246 | unsigned long addr; | |
247 | unsigned char key; | |
248 | int reg1, reg2; | |
249 | int rc; | |
250 | ||
a37cb07a CB |
251 | vcpu->stat.instruction_iske++; |
252 | ||
ca76ec9c JF |
253 | if (vcpu->arch.sie_block->gpsw.mask & PSW_MASK_PSTATE) |
254 | return kvm_s390_inject_program_int(vcpu, PGM_PRIVILEGED_OP); | |
255 | ||
a7e19ab5 DH |
256 | rc = try_handle_skey(vcpu); |
257 | if (rc) | |
258 | return rc != -EAGAIN ? rc : 0; | |
259 | ||
260 | kvm_s390_get_regs_rre(vcpu, ®1, ®2); | |
261 | ||
262 | addr = vcpu->run->s.regs.gprs[reg2] & PAGE_MASK; | |
263 | addr = kvm_s390_logical_to_effective(vcpu, addr); | |
264 | addr = kvm_s390_real_to_abs(vcpu, addr); | |
265 | addr = gfn_to_hva(vcpu->kvm, gpa_to_gfn(addr)); | |
266 | if (kvm_is_error_hva(addr)) | |
267 | return kvm_s390_inject_program_int(vcpu, PGM_ADDRESSING); | |
268 | ||
269 | down_read(¤t->mm->mmap_sem); | |
270 | rc = get_guest_storage_key(current->mm, addr, &key); | |
271 | up_read(¤t->mm->mmap_sem); | |
272 | if (rc) | |
273 | return kvm_s390_inject_program_int(vcpu, PGM_ADDRESSING); | |
274 | vcpu->run->s.regs.gprs[reg1] &= ~0xff; | |
275 | vcpu->run->s.regs.gprs[reg1] |= key; | |
276 | return 0; | |
277 | } | |
278 | ||
279 | static int handle_rrbe(struct kvm_vcpu *vcpu) | |
280 | { | |
281 | unsigned long addr; | |
282 | int reg1, reg2; | |
283 | int rc; | |
284 | ||
a37cb07a CB |
285 | vcpu->stat.instruction_rrbe++; |
286 | ||
ca76ec9c JF |
287 | if (vcpu->arch.sie_block->gpsw.mask & PSW_MASK_PSTATE) |
288 | return kvm_s390_inject_program_int(vcpu, PGM_PRIVILEGED_OP); | |
289 | ||
a7e19ab5 DH |
290 | rc = try_handle_skey(vcpu); |
291 | if (rc) | |
292 | return rc != -EAGAIN ? rc : 0; | |
293 | ||
294 | kvm_s390_get_regs_rre(vcpu, ®1, ®2); | |
295 | ||
296 | addr = vcpu->run->s.regs.gprs[reg2] & PAGE_MASK; | |
297 | addr = kvm_s390_logical_to_effective(vcpu, addr); | |
298 | addr = kvm_s390_real_to_abs(vcpu, addr); | |
299 | addr = gfn_to_hva(vcpu->kvm, gpa_to_gfn(addr)); | |
300 | if (kvm_is_error_hva(addr)) | |
301 | return kvm_s390_inject_program_int(vcpu, PGM_ADDRESSING); | |
302 | ||
303 | down_read(¤t->mm->mmap_sem); | |
304 | rc = reset_guest_reference_bit(current->mm, addr); | |
305 | up_read(¤t->mm->mmap_sem); | |
306 | if (rc < 0) | |
307 | return kvm_s390_inject_program_int(vcpu, PGM_ADDRESSING); | |
308 | ||
309 | kvm_s390_set_psw_cc(vcpu, rc); | |
310 | return 0; | |
311 | } | |
312 | ||
313 | #define SSKE_NQ 0x8 | |
314 | #define SSKE_MR 0x4 | |
315 | #define SSKE_MC 0x2 | |
316 | #define SSKE_MB 0x1 | |
317 | static int handle_sske(struct kvm_vcpu *vcpu) | |
318 | { | |
319 | unsigned char m3 = vcpu->arch.sie_block->ipb >> 28; | |
320 | unsigned long start, end; | |
321 | unsigned char key, oldkey; | |
322 | int reg1, reg2; | |
323 | int rc; | |
324 | ||
a37cb07a CB |
325 | vcpu->stat.instruction_sske++; |
326 | ||
ca76ec9c JF |
327 | if (vcpu->arch.sie_block->gpsw.mask & PSW_MASK_PSTATE) |
328 | return kvm_s390_inject_program_int(vcpu, PGM_PRIVILEGED_OP); | |
329 | ||
a7e19ab5 DH |
330 | rc = try_handle_skey(vcpu); |
331 | if (rc) | |
332 | return rc != -EAGAIN ? rc : 0; | |
333 | ||
334 | if (!test_kvm_facility(vcpu->kvm, 8)) | |
335 | m3 &= ~SSKE_MB; | |
336 | if (!test_kvm_facility(vcpu->kvm, 10)) | |
337 | m3 &= ~(SSKE_MC | SSKE_MR); | |
338 | if (!test_kvm_facility(vcpu->kvm, 14)) | |
339 | m3 &= ~SSKE_NQ; | |
340 | ||
341 | kvm_s390_get_regs_rre(vcpu, ®1, ®2); | |
342 | ||
343 | key = vcpu->run->s.regs.gprs[reg1] & 0xfe; | |
344 | start = vcpu->run->s.regs.gprs[reg2] & PAGE_MASK; | |
345 | start = kvm_s390_logical_to_effective(vcpu, start); | |
346 | if (m3 & SSKE_MB) { | |
347 | /* start already designates an absolute address */ | |
58cdf5eb | 348 | end = (start + _SEGMENT_SIZE) & ~(_SEGMENT_SIZE - 1); |
a7e19ab5 DH |
349 | } else { |
350 | start = kvm_s390_real_to_abs(vcpu, start); | |
351 | end = start + PAGE_SIZE; | |
352 | } | |
353 | ||
354 | while (start != end) { | |
355 | unsigned long addr = gfn_to_hva(vcpu->kvm, gpa_to_gfn(start)); | |
356 | ||
357 | if (kvm_is_error_hva(addr)) | |
358 | return kvm_s390_inject_program_int(vcpu, PGM_ADDRESSING); | |
359 | ||
360 | down_read(¤t->mm->mmap_sem); | |
361 | rc = cond_set_guest_storage_key(current->mm, addr, key, &oldkey, | |
362 | m3 & SSKE_NQ, m3 & SSKE_MR, | |
363 | m3 & SSKE_MC); | |
364 | up_read(¤t->mm->mmap_sem); | |
365 | if (rc < 0) | |
366 | return kvm_s390_inject_program_int(vcpu, PGM_ADDRESSING); | |
367 | start += PAGE_SIZE; | |
0b925159 | 368 | } |
a7e19ab5 DH |
369 | |
370 | if (m3 & (SSKE_MC | SSKE_MR)) { | |
371 | if (m3 & SSKE_MB) { | |
372 | /* skey in reg1 is unpredictable */ | |
373 | kvm_s390_set_psw_cc(vcpu, 3); | |
374 | } else { | |
375 | kvm_s390_set_psw_cc(vcpu, rc); | |
376 | vcpu->run->s.regs.gprs[reg1] &= ~0xff00UL; | |
377 | vcpu->run->s.regs.gprs[reg1] |= (u64) oldkey << 8; | |
378 | } | |
379 | } | |
380 | if (m3 & SSKE_MB) { | |
8bb3fdd6 | 381 | if (psw_bits(vcpu->arch.sie_block->gpsw).eaba == PSW_BITS_AMODE_64BIT) |
a7e19ab5 DH |
382 | vcpu->run->s.regs.gprs[reg2] &= ~PAGE_MASK; |
383 | else | |
384 | vcpu->run->s.regs.gprs[reg2] &= ~0xfffff000UL; | |
385 | end = kvm_s390_logical_to_effective(vcpu, end); | |
386 | vcpu->run->s.regs.gprs[reg2] |= end; | |
387 | } | |
453423dc CB |
388 | return 0; |
389 | } | |
390 | ||
8a242234 HC |
391 | static int handle_ipte_interlock(struct kvm_vcpu *vcpu) |
392 | { | |
8a242234 | 393 | vcpu->stat.instruction_ipte_interlock++; |
a7525982 | 394 | if (psw_bits(vcpu->arch.sie_block->gpsw).pstate) |
8a242234 HC |
395 | return kvm_s390_inject_program_int(vcpu, PGM_PRIVILEGED_OP); |
396 | wait_event(vcpu->kvm->arch.ipte_wq, !ipte_lock_held(vcpu)); | |
0e8bc06a | 397 | kvm_s390_retry_instr(vcpu); |
8a242234 HC |
398 | VCPU_EVENT(vcpu, 4, "%s", "retrying ipte interlock operation"); |
399 | return 0; | |
400 | } | |
401 | ||
aca84241 TH |
402 | static int handle_test_block(struct kvm_vcpu *vcpu) |
403 | { | |
aca84241 TH |
404 | gpa_t addr; |
405 | int reg2; | |
406 | ||
a37cb07a CB |
407 | vcpu->stat.instruction_tb++; |
408 | ||
aca84241 TH |
409 | if (vcpu->arch.sie_block->gpsw.mask & PSW_MASK_PSTATE) |
410 | return kvm_s390_inject_program_int(vcpu, PGM_PRIVILEGED_OP); | |
411 | ||
412 | kvm_s390_get_regs_rre(vcpu, NULL, ®2); | |
413 | addr = vcpu->run->s.regs.gprs[reg2] & PAGE_MASK; | |
e45efa28 | 414 | addr = kvm_s390_logical_to_effective(vcpu, addr); |
dd9e5b7b | 415 | if (kvm_s390_check_low_addr_prot_real(vcpu, addr)) |
e45efa28 | 416 | return kvm_s390_inject_prog_irq(vcpu, &vcpu->arch.pgm); |
aca84241 TH |
417 | addr = kvm_s390_real_to_abs(vcpu, addr); |
418 | ||
ef23e779 | 419 | if (kvm_is_error_gpa(vcpu->kvm, addr)) |
aca84241 TH |
420 | return kvm_s390_inject_program_int(vcpu, PGM_ADDRESSING); |
421 | /* | |
422 | * We don't expect errors on modern systems, and do not care | |
423 | * about storage keys (yet), so let's just clear the page. | |
424 | */ | |
ef23e779 | 425 | if (kvm_clear_guest(vcpu->kvm, addr, PAGE_SIZE)) |
aca84241 TH |
426 | return -EFAULT; |
427 | kvm_s390_set_psw_cc(vcpu, 0); | |
428 | vcpu->run->s.regs.gprs[0] = 0; | |
429 | return 0; | |
430 | } | |
431 | ||
fa6b7fe9 | 432 | static int handle_tpi(struct kvm_vcpu *vcpu) |
453423dc | 433 | { |
fa6b7fe9 | 434 | struct kvm_s390_interrupt_info *inti; |
4799b557 HC |
435 | unsigned long len; |
436 | u32 tpi_data[3]; | |
261520dc | 437 | int rc; |
7c959e82 | 438 | u64 addr; |
27f67f87 | 439 | u8 ar; |
fa6b7fe9 | 440 | |
a37cb07a CB |
441 | vcpu->stat.instruction_tpi++; |
442 | ||
8ae04b8f | 443 | addr = kvm_s390_get_base_disp_s(vcpu, &ar); |
db4a29cb HC |
444 | if (addr & 3) |
445 | return kvm_s390_inject_program_int(vcpu, PGM_SPECIFICATION); | |
261520dc | 446 | |
f092669e | 447 | inti = kvm_s390_get_io_int(vcpu->kvm, vcpu->arch.sie_block->gcr[6], 0); |
261520dc DH |
448 | if (!inti) { |
449 | kvm_s390_set_psw_cc(vcpu, 0); | |
450 | return 0; | |
451 | } | |
452 | ||
4799b557 HC |
453 | tpi_data[0] = inti->io.subchannel_id << 16 | inti->io.subchannel_nr; |
454 | tpi_data[1] = inti->io.io_int_parm; | |
455 | tpi_data[2] = inti->io.io_int_word; | |
7c959e82 HC |
456 | if (addr) { |
457 | /* | |
458 | * Store the two-word I/O interruption code into the | |
459 | * provided area. | |
460 | */ | |
4799b557 | 461 | len = sizeof(tpi_data) - 4; |
8ae04b8f | 462 | rc = write_guest(vcpu, addr, ar, &tpi_data, len); |
261520dc DH |
463 | if (rc) { |
464 | rc = kvm_s390_inject_prog_cond(vcpu, rc); | |
465 | goto reinject_interrupt; | |
466 | } | |
7c959e82 HC |
467 | } else { |
468 | /* | |
469 | * Store the three-word I/O interruption code into | |
470 | * the appropriate lowcore area. | |
471 | */ | |
4799b557 | 472 | len = sizeof(tpi_data); |
261520dc DH |
473 | if (write_guest_lc(vcpu, __LC_SUBCHANNEL_ID, &tpi_data, len)) { |
474 | /* failed writes to the low core are not recoverable */ | |
4799b557 | 475 | rc = -EFAULT; |
261520dc DH |
476 | goto reinject_interrupt; |
477 | } | |
7c959e82 | 478 | } |
261520dc DH |
479 | |
480 | /* irq was successfully handed to the guest */ | |
481 | kfree(inti); | |
482 | kvm_s390_set_psw_cc(vcpu, 1); | |
483 | return 0; | |
484 | reinject_interrupt: | |
2f32d4ea CH |
485 | /* |
486 | * If we encounter a problem storing the interruption code, the | |
487 | * instruction is suppressed from the guest's view: reinject the | |
488 | * interrupt. | |
489 | */ | |
15462e37 DH |
490 | if (kvm_s390_reinject_io_int(vcpu->kvm, inti)) { |
491 | kfree(inti); | |
492 | rc = -EFAULT; | |
493 | } | |
261520dc | 494 | /* don't set the cc, a pgm irq was injected or we drop to user space */ |
4799b557 | 495 | return rc ? -EFAULT : 0; |
453423dc CB |
496 | } |
497 | ||
fa6b7fe9 CH |
498 | static int handle_tsch(struct kvm_vcpu *vcpu) |
499 | { | |
6d3da241 JF |
500 | struct kvm_s390_interrupt_info *inti = NULL; |
501 | const u64 isc_mask = 0xffUL << 24; /* all iscs set */ | |
fa6b7fe9 | 502 | |
a37cb07a CB |
503 | vcpu->stat.instruction_tsch++; |
504 | ||
6d3da241 JF |
505 | /* a valid schid has at least one bit set */ |
506 | if (vcpu->run->s.regs.gprs[1]) | |
507 | inti = kvm_s390_get_io_int(vcpu->kvm, isc_mask, | |
508 | vcpu->run->s.regs.gprs[1]); | |
fa6b7fe9 CH |
509 | |
510 | /* | |
511 | * Prepare exit to userspace. | |
512 | * We indicate whether we dequeued a pending I/O interrupt | |
513 | * so that userspace can re-inject it if the instruction gets | |
514 | * a program check. While this may re-order the pending I/O | |
515 | * interrupts, this is no problem since the priority is kept | |
516 | * intact. | |
517 | */ | |
518 | vcpu->run->exit_reason = KVM_EXIT_S390_TSCH; | |
519 | vcpu->run->s390_tsch.dequeued = !!inti; | |
520 | if (inti) { | |
521 | vcpu->run->s390_tsch.subchannel_id = inti->io.subchannel_id; | |
522 | vcpu->run->s390_tsch.subchannel_nr = inti->io.subchannel_nr; | |
523 | vcpu->run->s390_tsch.io_int_parm = inti->io.io_int_parm; | |
524 | vcpu->run->s390_tsch.io_int_word = inti->io.io_int_word; | |
525 | } | |
526 | vcpu->run->s390_tsch.ipb = vcpu->arch.sie_block->ipb; | |
527 | kfree(inti); | |
528 | return -EREMOTE; | |
529 | } | |
530 | ||
531 | static int handle_io_inst(struct kvm_vcpu *vcpu) | |
532 | { | |
533 | VCPU_EVENT(vcpu, 4, "%s", "I/O instruction"); | |
534 | ||
5087dfa6 TH |
535 | if (vcpu->arch.sie_block->gpsw.mask & PSW_MASK_PSTATE) |
536 | return kvm_s390_inject_program_int(vcpu, PGM_PRIVILEGED_OP); | |
537 | ||
fa6b7fe9 CH |
538 | if (vcpu->kvm->arch.css_support) { |
539 | /* | |
540 | * Most I/O instructions will be handled by userspace. | |
541 | * Exceptions are tpi and the interrupt portion of tsch. | |
542 | */ | |
543 | if (vcpu->arch.sie_block->ipa == 0xb236) | |
544 | return handle_tpi(vcpu); | |
545 | if (vcpu->arch.sie_block->ipa == 0xb235) | |
546 | return handle_tsch(vcpu); | |
547 | /* Handle in userspace. */ | |
a37cb07a | 548 | vcpu->stat.instruction_io_other++; |
fa6b7fe9 CH |
549 | return -EOPNOTSUPP; |
550 | } else { | |
551 | /* | |
b4a96015 | 552 | * Set condition code 3 to stop the guest from issuing channel |
fa6b7fe9 CH |
553 | * I/O instructions. |
554 | */ | |
ea828ebf | 555 | kvm_s390_set_psw_cc(vcpu, 3); |
fa6b7fe9 CH |
556 | return 0; |
557 | } | |
558 | } | |
559 | ||
453423dc CB |
560 | static int handle_stfl(struct kvm_vcpu *vcpu) |
561 | { | |
453423dc | 562 | int rc; |
9d8d5786 | 563 | unsigned int fac; |
453423dc CB |
564 | |
565 | vcpu->stat.instruction_stfl++; | |
5087dfa6 TH |
566 | |
567 | if (vcpu->arch.sie_block->gpsw.mask & PSW_MASK_PSTATE) | |
568 | return kvm_s390_inject_program_int(vcpu, PGM_PRIVILEGED_OP); | |
569 | ||
9d8d5786 MM |
570 | /* |
571 | * We need to shift the lower 32 facility bits (bit 0-31) from a u64 | |
572 | * into a u32 memory representation. They will remain bits 0-31. | |
573 | */ | |
c54f0d6a | 574 | fac = *vcpu->kvm->arch.model.fac_list >> 32; |
c667aeac | 575 | rc = write_guest_lc(vcpu, offsetof(struct lowcore, stfl_fac_list), |
9d8d5786 | 576 | &fac, sizeof(fac)); |
dc5008b9 | 577 | if (rc) |
0f9701c6 | 578 | return rc; |
7cbde76b | 579 | VCPU_EVENT(vcpu, 3, "STFL: store facility list 0x%x", fac); |
9d8d5786 | 580 | trace_kvm_s390_handle_stfl(vcpu, fac); |
453423dc CB |
581 | return 0; |
582 | } | |
583 | ||
48a3e950 CH |
584 | #define PSW_MASK_ADDR_MODE (PSW_MASK_EA | PSW_MASK_BA) |
585 | #define PSW_MASK_UNASSIGNED 0xb80800fe7fffffffUL | |
d21683ea | 586 | #define PSW_ADDR_24 0x0000000000ffffffUL |
48a3e950 CH |
587 | #define PSW_ADDR_31 0x000000007fffffffUL |
588 | ||
a3fb577e TH |
589 | int is_valid_psw(psw_t *psw) |
590 | { | |
3736b874 HC |
591 | if (psw->mask & PSW_MASK_UNASSIGNED) |
592 | return 0; | |
593 | if ((psw->mask & PSW_MASK_ADDR_MODE) == PSW_MASK_BA) { | |
594 | if (psw->addr & ~PSW_ADDR_31) | |
595 | return 0; | |
596 | } | |
597 | if (!(psw->mask & PSW_MASK_ADDR_MODE) && (psw->addr & ~PSW_ADDR_24)) | |
598 | return 0; | |
599 | if ((psw->mask & PSW_MASK_ADDR_MODE) == PSW_MASK_EA) | |
600 | return 0; | |
a3fb577e TH |
601 | if (psw->addr & 1) |
602 | return 0; | |
3736b874 HC |
603 | return 1; |
604 | } | |
605 | ||
48a3e950 CH |
606 | int kvm_s390_handle_lpsw(struct kvm_vcpu *vcpu) |
607 | { | |
3736b874 | 608 | psw_t *gpsw = &vcpu->arch.sie_block->gpsw; |
48a3e950 | 609 | psw_compat_t new_psw; |
3736b874 | 610 | u64 addr; |
2d8bcaed | 611 | int rc; |
27f67f87 | 612 | u8 ar; |
48a3e950 | 613 | |
a37cb07a CB |
614 | vcpu->stat.instruction_lpsw++; |
615 | ||
3736b874 | 616 | if (gpsw->mask & PSW_MASK_PSTATE) |
208dd756 TH |
617 | return kvm_s390_inject_program_int(vcpu, PGM_PRIVILEGED_OP); |
618 | ||
8ae04b8f | 619 | addr = kvm_s390_get_base_disp_s(vcpu, &ar); |
6fd0fcc9 HC |
620 | if (addr & 7) |
621 | return kvm_s390_inject_program_int(vcpu, PGM_SPECIFICATION); | |
2d8bcaed | 622 | |
8ae04b8f | 623 | rc = read_guest(vcpu, addr, ar, &new_psw, sizeof(new_psw)); |
2d8bcaed HC |
624 | if (rc) |
625 | return kvm_s390_inject_prog_cond(vcpu, rc); | |
6fd0fcc9 HC |
626 | if (!(new_psw.mask & PSW32_MASK_BASE)) |
627 | return kvm_s390_inject_program_int(vcpu, PGM_SPECIFICATION); | |
3736b874 HC |
628 | gpsw->mask = (new_psw.mask & ~PSW32_MASK_BASE) << 32; |
629 | gpsw->mask |= new_psw.addr & PSW32_ADDR_AMODE; | |
630 | gpsw->addr = new_psw.addr & ~PSW32_ADDR_AMODE; | |
631 | if (!is_valid_psw(gpsw)) | |
6fd0fcc9 | 632 | return kvm_s390_inject_program_int(vcpu, PGM_SPECIFICATION); |
48a3e950 CH |
633 | return 0; |
634 | } | |
635 | ||
636 | static int handle_lpswe(struct kvm_vcpu *vcpu) | |
637 | { | |
48a3e950 | 638 | psw_t new_psw; |
3736b874 | 639 | u64 addr; |
2d8bcaed | 640 | int rc; |
27f67f87 | 641 | u8 ar; |
48a3e950 | 642 | |
a37cb07a CB |
643 | vcpu->stat.instruction_lpswe++; |
644 | ||
5087dfa6 TH |
645 | if (vcpu->arch.sie_block->gpsw.mask & PSW_MASK_PSTATE) |
646 | return kvm_s390_inject_program_int(vcpu, PGM_PRIVILEGED_OP); | |
647 | ||
8ae04b8f | 648 | addr = kvm_s390_get_base_disp_s(vcpu, &ar); |
6fd0fcc9 HC |
649 | if (addr & 7) |
650 | return kvm_s390_inject_program_int(vcpu, PGM_SPECIFICATION); | |
8ae04b8f | 651 | rc = read_guest(vcpu, addr, ar, &new_psw, sizeof(new_psw)); |
2d8bcaed HC |
652 | if (rc) |
653 | return kvm_s390_inject_prog_cond(vcpu, rc); | |
3736b874 HC |
654 | vcpu->arch.sie_block->gpsw = new_psw; |
655 | if (!is_valid_psw(&vcpu->arch.sie_block->gpsw)) | |
6fd0fcc9 | 656 | return kvm_s390_inject_program_int(vcpu, PGM_SPECIFICATION); |
48a3e950 CH |
657 | return 0; |
658 | } | |
659 | ||
453423dc CB |
660 | static int handle_stidp(struct kvm_vcpu *vcpu) |
661 | { | |
9bb0ec09 | 662 | u64 stidp_data = vcpu->kvm->arch.model.cpuid; |
453423dc | 663 | u64 operand2; |
7d777d78 | 664 | int rc; |
27f67f87 | 665 | u8 ar; |
453423dc CB |
666 | |
667 | vcpu->stat.instruction_stidp++; | |
b1c571a5 | 668 | |
5087dfa6 TH |
669 | if (vcpu->arch.sie_block->gpsw.mask & PSW_MASK_PSTATE) |
670 | return kvm_s390_inject_program_int(vcpu, PGM_PRIVILEGED_OP); | |
671 | ||
8ae04b8f | 672 | operand2 = kvm_s390_get_base_disp_s(vcpu, &ar); |
453423dc | 673 | |
db4a29cb HC |
674 | if (operand2 & 7) |
675 | return kvm_s390_inject_program_int(vcpu, PGM_SPECIFICATION); | |
453423dc | 676 | |
8ae04b8f | 677 | rc = write_guest(vcpu, operand2, ar, &stidp_data, sizeof(stidp_data)); |
7d777d78 HC |
678 | if (rc) |
679 | return kvm_s390_inject_prog_cond(vcpu, rc); | |
453423dc | 680 | |
7cbde76b | 681 | VCPU_EVENT(vcpu, 3, "STIDP: store cpu id 0x%llx", stidp_data); |
453423dc CB |
682 | return 0; |
683 | } | |
684 | ||
685 | static void handle_stsi_3_2_2(struct kvm_vcpu *vcpu, struct sysinfo_3_2_2 *mem) | |
686 | { | |
453423dc CB |
687 | int cpus = 0; |
688 | int n; | |
689 | ||
ff520a63 | 690 | cpus = atomic_read(&vcpu->kvm->online_vcpus); |
453423dc CB |
691 | |
692 | /* deal with other level 3 hypervisors */ | |
caf757c6 | 693 | if (stsi(mem, 3, 2, 2)) |
453423dc CB |
694 | mem->count = 0; |
695 | if (mem->count < 8) | |
696 | mem->count++; | |
697 | for (n = mem->count - 1; n > 0 ; n--) | |
698 | memcpy(&mem->vm[n], &mem->vm[n - 1], sizeof(mem->vm[0])); | |
699 | ||
b75f4c9a | 700 | memset(&mem->vm[0], 0, sizeof(mem->vm[0])); |
453423dc CB |
701 | mem->vm[0].cpus_total = cpus; |
702 | mem->vm[0].cpus_configured = cpus; | |
703 | mem->vm[0].cpus_standby = 0; | |
704 | mem->vm[0].cpus_reserved = 0; | |
705 | mem->vm[0].caf = 1000; | |
706 | memcpy(mem->vm[0].name, "KVMguest", 8); | |
707 | ASCEBC(mem->vm[0].name, 8); | |
708 | memcpy(mem->vm[0].cpi, "KVM/Linux ", 16); | |
709 | ASCEBC(mem->vm[0].cpi, 16); | |
710 | } | |
711 | ||
27f67f87 | 712 | static void insert_stsi_usr_data(struct kvm_vcpu *vcpu, u64 addr, u8 ar, |
e44fc8c9 ET |
713 | u8 fc, u8 sel1, u16 sel2) |
714 | { | |
715 | vcpu->run->exit_reason = KVM_EXIT_S390_STSI; | |
716 | vcpu->run->s390_stsi.addr = addr; | |
717 | vcpu->run->s390_stsi.ar = ar; | |
718 | vcpu->run->s390_stsi.fc = fc; | |
719 | vcpu->run->s390_stsi.sel1 = sel1; | |
720 | vcpu->run->s390_stsi.sel2 = sel2; | |
721 | } | |
722 | ||
453423dc CB |
723 | static int handle_stsi(struct kvm_vcpu *vcpu) |
724 | { | |
5a32c1af CB |
725 | int fc = (vcpu->run->s.regs.gprs[0] & 0xf0000000) >> 28; |
726 | int sel1 = vcpu->run->s.regs.gprs[0] & 0xff; | |
727 | int sel2 = vcpu->run->s.regs.gprs[1] & 0xffff; | |
c51f068c | 728 | unsigned long mem = 0; |
453423dc | 729 | u64 operand2; |
db4a29cb | 730 | int rc = 0; |
27f67f87 | 731 | u8 ar; |
453423dc CB |
732 | |
733 | vcpu->stat.instruction_stsi++; | |
7cbde76b | 734 | VCPU_EVENT(vcpu, 3, "STSI: fc: %u sel1: %u sel2: %u", fc, sel1, sel2); |
453423dc | 735 | |
5087dfa6 TH |
736 | if (vcpu->arch.sie_block->gpsw.mask & PSW_MASK_PSTATE) |
737 | return kvm_s390_inject_program_int(vcpu, PGM_PRIVILEGED_OP); | |
738 | ||
87d41fb4 | 739 | if (fc > 3) { |
ea828ebf | 740 | kvm_s390_set_psw_cc(vcpu, 3); |
87d41fb4 TH |
741 | return 0; |
742 | } | |
453423dc | 743 | |
87d41fb4 TH |
744 | if (vcpu->run->s.regs.gprs[0] & 0x0fffff00 |
745 | || vcpu->run->s.regs.gprs[1] & 0xffff0000) | |
453423dc CB |
746 | return kvm_s390_inject_program_int(vcpu, PGM_SPECIFICATION); |
747 | ||
87d41fb4 | 748 | if (fc == 0) { |
5a32c1af | 749 | vcpu->run->s.regs.gprs[0] = 3 << 28; |
ea828ebf | 750 | kvm_s390_set_psw_cc(vcpu, 0); |
453423dc | 751 | return 0; |
87d41fb4 TH |
752 | } |
753 | ||
8ae04b8f | 754 | operand2 = kvm_s390_get_base_disp_s(vcpu, &ar); |
87d41fb4 TH |
755 | |
756 | if (operand2 & 0xfff) | |
757 | return kvm_s390_inject_program_int(vcpu, PGM_SPECIFICATION); | |
758 | ||
759 | switch (fc) { | |
453423dc CB |
760 | case 1: /* same handling for 1 and 2 */ |
761 | case 2: | |
762 | mem = get_zeroed_page(GFP_KERNEL); | |
763 | if (!mem) | |
c51f068c | 764 | goto out_no_data; |
caf757c6 | 765 | if (stsi((void *) mem, fc, sel1, sel2)) |
c51f068c | 766 | goto out_no_data; |
453423dc CB |
767 | break; |
768 | case 3: | |
769 | if (sel1 != 2 || sel2 != 2) | |
c51f068c | 770 | goto out_no_data; |
453423dc CB |
771 | mem = get_zeroed_page(GFP_KERNEL); |
772 | if (!mem) | |
c51f068c | 773 | goto out_no_data; |
453423dc CB |
774 | handle_stsi_3_2_2(vcpu, (void *) mem); |
775 | break; | |
453423dc CB |
776 | } |
777 | ||
8ae04b8f | 778 | rc = write_guest(vcpu, operand2, ar, (void *)mem, PAGE_SIZE); |
645c5bc1 HC |
779 | if (rc) { |
780 | rc = kvm_s390_inject_prog_cond(vcpu, rc); | |
781 | goto out; | |
453423dc | 782 | } |
e44fc8c9 ET |
783 | if (vcpu->kvm->arch.user_stsi) { |
784 | insert_stsi_usr_data(vcpu, operand2, ar, fc, sel1, sel2); | |
785 | rc = -EREMOTE; | |
786 | } | |
5786fffa | 787 | trace_kvm_s390_handle_stsi(vcpu, fc, sel1, sel2, operand2); |
453423dc | 788 | free_page(mem); |
ea828ebf | 789 | kvm_s390_set_psw_cc(vcpu, 0); |
5a32c1af | 790 | vcpu->run->s.regs.gprs[0] = 0; |
e44fc8c9 | 791 | return rc; |
c51f068c | 792 | out_no_data: |
ea828ebf | 793 | kvm_s390_set_psw_cc(vcpu, 3); |
645c5bc1 | 794 | out: |
c51f068c | 795 | free_page(mem); |
db4a29cb | 796 | return rc; |
453423dc CB |
797 | } |
798 | ||
70455a36 | 799 | int kvm_s390_handle_b2(struct kvm_vcpu *vcpu) |
453423dc | 800 | { |
6db4263f CB |
801 | switch (vcpu->arch.sie_block->ipa & 0x00ff) { |
802 | case 0x02: | |
803 | return handle_stidp(vcpu); | |
804 | case 0x04: | |
805 | return handle_set_clock(vcpu); | |
806 | case 0x10: | |
807 | return handle_set_prefix(vcpu); | |
808 | case 0x11: | |
809 | return handle_store_prefix(vcpu); | |
810 | case 0x12: | |
811 | return handle_store_cpu_address(vcpu); | |
812 | case 0x14: | |
813 | return kvm_s390_handle_vsie(vcpu); | |
814 | case 0x21: | |
815 | case 0x50: | |
816 | return handle_ipte_interlock(vcpu); | |
817 | case 0x29: | |
818 | return handle_iske(vcpu); | |
819 | case 0x2a: | |
820 | return handle_rrbe(vcpu); | |
821 | case 0x2b: | |
822 | return handle_sske(vcpu); | |
823 | case 0x2c: | |
824 | return handle_test_block(vcpu); | |
825 | case 0x30: | |
826 | case 0x31: | |
827 | case 0x32: | |
828 | case 0x33: | |
829 | case 0x34: | |
830 | case 0x35: | |
831 | case 0x36: | |
832 | case 0x37: | |
833 | case 0x38: | |
834 | case 0x39: | |
835 | case 0x3a: | |
836 | case 0x3b: | |
837 | case 0x3c: | |
838 | case 0x5f: | |
839 | case 0x74: | |
840 | case 0x76: | |
841 | return handle_io_inst(vcpu); | |
842 | case 0x56: | |
843 | return handle_sthyi(vcpu); | |
844 | case 0x7d: | |
845 | return handle_stsi(vcpu); | |
846 | case 0xb1: | |
847 | return handle_stfl(vcpu); | |
848 | case 0xb2: | |
849 | return handle_lpswe(vcpu); | |
850 | default: | |
851 | return -EOPNOTSUPP; | |
852 | } | |
453423dc | 853 | } |
bb25b9ba | 854 | |
48a3e950 CH |
855 | static int handle_epsw(struct kvm_vcpu *vcpu) |
856 | { | |
857 | int reg1, reg2; | |
858 | ||
a37cb07a CB |
859 | vcpu->stat.instruction_epsw++; |
860 | ||
aeb87c3c | 861 | kvm_s390_get_regs_rre(vcpu, ®1, ®2); |
48a3e950 CH |
862 | |
863 | /* This basically extracts the mask half of the psw. */ | |
843200e7 | 864 | vcpu->run->s.regs.gprs[reg1] &= 0xffffffff00000000UL; |
48a3e950 CH |
865 | vcpu->run->s.regs.gprs[reg1] |= vcpu->arch.sie_block->gpsw.mask >> 32; |
866 | if (reg2) { | |
843200e7 | 867 | vcpu->run->s.regs.gprs[reg2] &= 0xffffffff00000000UL; |
48a3e950 | 868 | vcpu->run->s.regs.gprs[reg2] |= |
843200e7 | 869 | vcpu->arch.sie_block->gpsw.mask & 0x00000000ffffffffUL; |
48a3e950 CH |
870 | } |
871 | return 0; | |
872 | } | |
873 | ||
69d0d3a3 CB |
874 | #define PFMF_RESERVED 0xfffc0101UL |
875 | #define PFMF_SK 0x00020000UL | |
876 | #define PFMF_CF 0x00010000UL | |
877 | #define PFMF_UI 0x00008000UL | |
878 | #define PFMF_FSC 0x00007000UL | |
879 | #define PFMF_NQ 0x00000800UL | |
880 | #define PFMF_MR 0x00000400UL | |
881 | #define PFMF_MC 0x00000200UL | |
882 | #define PFMF_KEY 0x000000feUL | |
883 | ||
884 | static int handle_pfmf(struct kvm_vcpu *vcpu) | |
885 | { | |
1824c723 | 886 | bool mr = false, mc = false, nq; |
69d0d3a3 CB |
887 | int reg1, reg2; |
888 | unsigned long start, end; | |
1824c723 | 889 | unsigned char key; |
69d0d3a3 CB |
890 | |
891 | vcpu->stat.instruction_pfmf++; | |
892 | ||
893 | kvm_s390_get_regs_rre(vcpu, ®1, ®2); | |
894 | ||
03c02807 | 895 | if (!test_kvm_facility(vcpu->kvm, 8)) |
69d0d3a3 CB |
896 | return kvm_s390_inject_program_int(vcpu, PGM_OPERATION); |
897 | ||
898 | if (vcpu->arch.sie_block->gpsw.mask & PSW_MASK_PSTATE) | |
208dd756 | 899 | return kvm_s390_inject_program_int(vcpu, PGM_PRIVILEGED_OP); |
69d0d3a3 CB |
900 | |
901 | if (vcpu->run->s.regs.gprs[reg1] & PFMF_RESERVED) | |
902 | return kvm_s390_inject_program_int(vcpu, PGM_SPECIFICATION); | |
903 | ||
edc5b055 DH |
904 | /* Only provide non-quiescing support if enabled for the guest */ |
905 | if (vcpu->run->s.regs.gprs[reg1] & PFMF_NQ && | |
906 | !test_kvm_facility(vcpu->kvm, 14)) | |
69d0d3a3 CB |
907 | return kvm_s390_inject_program_int(vcpu, PGM_SPECIFICATION); |
908 | ||
1824c723 DH |
909 | /* Only provide conditional-SSKE support if enabled for the guest */ |
910 | if (vcpu->run->s.regs.gprs[reg1] & PFMF_SK && | |
911 | test_kvm_facility(vcpu->kvm, 10)) { | |
912 | mr = vcpu->run->s.regs.gprs[reg1] & PFMF_MR; | |
913 | mc = vcpu->run->s.regs.gprs[reg1] & PFMF_MC; | |
914 | } | |
915 | ||
916 | nq = vcpu->run->s.regs.gprs[reg1] & PFMF_NQ; | |
917 | key = vcpu->run->s.regs.gprs[reg1] & PFMF_KEY; | |
69d0d3a3 | 918 | start = vcpu->run->s.regs.gprs[reg2] & PAGE_MASK; |
a02689fe | 919 | start = kvm_s390_logical_to_effective(vcpu, start); |
fb34c603 | 920 | |
6164a2e9 DH |
921 | if (vcpu->run->s.regs.gprs[reg1] & PFMF_CF) { |
922 | if (kvm_s390_check_low_addr_prot_real(vcpu, start)) | |
923 | return kvm_s390_inject_prog_irq(vcpu, &vcpu->arch.pgm); | |
924 | } | |
925 | ||
69d0d3a3 CB |
926 | switch (vcpu->run->s.regs.gprs[reg1] & PFMF_FSC) { |
927 | case 0x00000000: | |
6164a2e9 DH |
928 | /* only 4k frames specify a real address */ |
929 | start = kvm_s390_real_to_abs(vcpu, start); | |
58cdf5eb | 930 | end = (start + PAGE_SIZE) & ~(PAGE_SIZE - 1); |
69d0d3a3 CB |
931 | break; |
932 | case 0x00001000: | |
58cdf5eb | 933 | end = (start + _SEGMENT_SIZE) & ~(_SEGMENT_SIZE - 1); |
69d0d3a3 | 934 | break; |
69d0d3a3 | 935 | case 0x00002000: |
53df84f8 GH |
936 | /* only support 2G frame size if EDAT2 is available and we are |
937 | not in 24-bit addressing mode */ | |
938 | if (!test_kvm_facility(vcpu->kvm, 78) || | |
8bb3fdd6 | 939 | psw_bits(vcpu->arch.sie_block->gpsw).eaba == PSW_BITS_AMODE_24BIT) |
53df84f8 | 940 | return kvm_s390_inject_program_int(vcpu, PGM_SPECIFICATION); |
58cdf5eb | 941 | end = (start + _REGION3_SIZE) & ~(_REGION3_SIZE - 1); |
53df84f8 | 942 | break; |
69d0d3a3 CB |
943 | default: |
944 | return kvm_s390_inject_program_int(vcpu, PGM_SPECIFICATION); | |
945 | } | |
a02689fe | 946 | |
695be0e7 | 947 | while (start != end) { |
6164a2e9 | 948 | unsigned long useraddr; |
fb34c603 TH |
949 | |
950 | /* Translate guest address to host address */ | |
6164a2e9 | 951 | useraddr = gfn_to_hva(vcpu->kvm, gpa_to_gfn(start)); |
fb34c603 | 952 | if (kvm_is_error_hva(useraddr)) |
69d0d3a3 CB |
953 | return kvm_s390_inject_program_int(vcpu, PGM_ADDRESSING); |
954 | ||
955 | if (vcpu->run->s.regs.gprs[reg1] & PFMF_CF) { | |
956 | if (clear_user((void __user *)useraddr, PAGE_SIZE)) | |
957 | return kvm_s390_inject_program_int(vcpu, PGM_ADDRESSING); | |
958 | } | |
959 | ||
960 | if (vcpu->run->s.regs.gprs[reg1] & PFMF_SK) { | |
730cd632 | 961 | int rc = kvm_s390_skey_check_enable(vcpu); |
3ac8e380 DD |
962 | |
963 | if (rc) | |
964 | return rc; | |
d3ed1cee | 965 | down_read(¤t->mm->mmap_sem); |
1824c723 DH |
966 | rc = cond_set_guest_storage_key(current->mm, useraddr, |
967 | key, NULL, nq, mr, mc); | |
d3ed1cee | 968 | up_read(¤t->mm->mmap_sem); |
1824c723 | 969 | if (rc < 0) |
69d0d3a3 CB |
970 | return kvm_s390_inject_program_int(vcpu, PGM_ADDRESSING); |
971 | } | |
972 | ||
973 | start += PAGE_SIZE; | |
974 | } | |
2c26d1d2 | 975 | if (vcpu->run->s.regs.gprs[reg1] & PFMF_FSC) { |
8bb3fdd6 | 976 | if (psw_bits(vcpu->arch.sie_block->gpsw).eaba == PSW_BITS_AMODE_64BIT) { |
2c26d1d2 DH |
977 | vcpu->run->s.regs.gprs[reg2] = end; |
978 | } else { | |
979 | vcpu->run->s.regs.gprs[reg2] &= ~0xffffffffUL; | |
980 | end = kvm_s390_logical_to_effective(vcpu, end); | |
981 | vcpu->run->s.regs.gprs[reg2] |= end; | |
982 | } | |
983 | } | |
69d0d3a3 CB |
984 | return 0; |
985 | } | |
986 | ||
190df4a2 CI |
987 | static inline int do_essa(struct kvm_vcpu *vcpu, const int orc) |
988 | { | |
989 | struct kvm_s390_migration_state *ms = vcpu->kvm->arch.migration_state; | |
990 | int r1, r2, nappended, entries; | |
991 | unsigned long gfn, hva, res, pgstev, ptev; | |
992 | unsigned long *cbrlo; | |
993 | ||
994 | /* | |
995 | * We don't need to set SD.FPF.SK to 1 here, because if we have a | |
996 | * machine check here we either handle it or crash | |
997 | */ | |
998 | ||
999 | kvm_s390_get_regs_rre(vcpu, &r1, &r2); | |
1000 | gfn = vcpu->run->s.regs.gprs[r2] >> PAGE_SHIFT; | |
1001 | hva = gfn_to_hva(vcpu->kvm, gfn); | |
1002 | entries = (vcpu->arch.sie_block->cbrlo & ~PAGE_MASK) >> 3; | |
1003 | ||
1004 | if (kvm_is_error_hva(hva)) | |
1005 | return kvm_s390_inject_program_int(vcpu, PGM_ADDRESSING); | |
1006 | ||
1007 | nappended = pgste_perform_essa(vcpu->kvm->mm, hva, orc, &ptev, &pgstev); | |
1008 | if (nappended < 0) { | |
1009 | res = orc ? 0x10 : 0; | |
1010 | vcpu->run->s.regs.gprs[r1] = res; /* Exception Indication */ | |
1011 | return 0; | |
1012 | } | |
1013 | res = (pgstev & _PGSTE_GPS_USAGE_MASK) >> 22; | |
1014 | /* | |
1015 | * Set the block-content state part of the result. 0 means resident, so | |
1016 | * nothing to do if the page is valid. 2 is for preserved pages | |
1017 | * (non-present and non-zero), and 3 for zero pages (non-present and | |
1018 | * zero). | |
1019 | */ | |
1020 | if (ptev & _PAGE_INVALID) { | |
1021 | res |= 2; | |
1022 | if (pgstev & _PGSTE_GPS_ZERO) | |
1023 | res |= 1; | |
1024 | } | |
1bab1c02 CI |
1025 | if (pgstev & _PGSTE_GPS_NODAT) |
1026 | res |= 0x20; | |
190df4a2 CI |
1027 | vcpu->run->s.regs.gprs[r1] = res; |
1028 | /* | |
1029 | * It is possible that all the normal 511 slots were full, in which case | |
1030 | * we will now write in the 512th slot, which is reserved for host use. | |
1031 | * In both cases we let the normal essa handling code process all the | |
1032 | * slots, including the reserved one, if needed. | |
1033 | */ | |
1034 | if (nappended > 0) { | |
1035 | cbrlo = phys_to_virt(vcpu->arch.sie_block->cbrlo & PAGE_MASK); | |
1036 | cbrlo[entries] = gfn << PAGE_SHIFT; | |
1037 | } | |
1038 | ||
c2cf265d | 1039 | if (orc && gfn < ms->bitmap_size) { |
190df4a2 CI |
1040 | /* increment only if we are really flipping the bit to 1 */ |
1041 | if (!test_and_set_bit(gfn, ms->pgste_bitmap)) | |
1042 | atomic64_inc(&ms->dirty_pages); | |
1043 | } | |
1044 | ||
1045 | return nappended; | |
1046 | } | |
1047 | ||
b31288fa KW |
1048 | static int handle_essa(struct kvm_vcpu *vcpu) |
1049 | { | |
1050 | /* entries expected to be 1FF */ | |
1051 | int entries = (vcpu->arch.sie_block->cbrlo & ~PAGE_MASK) >> 3; | |
4a5e7e38 | 1052 | unsigned long *cbrlo; |
b31288fa | 1053 | struct gmap *gmap; |
190df4a2 | 1054 | int i, orc; |
b31288fa | 1055 | |
7cbde76b | 1056 | VCPU_EVENT(vcpu, 4, "ESSA: release %d pages", entries); |
b31288fa KW |
1057 | gmap = vcpu->arch.gmap; |
1058 | vcpu->stat.instruction_essa++; | |
e6db1d61 | 1059 | if (!vcpu->kvm->arch.use_cmma) |
b31288fa KW |
1060 | return kvm_s390_inject_program_int(vcpu, PGM_OPERATION); |
1061 | ||
1062 | if (vcpu->arch.sie_block->gpsw.mask & PSW_MASK_PSTATE) | |
1063 | return kvm_s390_inject_program_int(vcpu, PGM_PRIVILEGED_OP); | |
190df4a2 CI |
1064 | /* Check for invalid operation request code */ |
1065 | orc = (vcpu->arch.sie_block->ipb & 0xf0000000) >> 28; | |
1bab1c02 CI |
1066 | /* ORCs 0-6 are always valid */ |
1067 | if (orc > (test_kvm_facility(vcpu->kvm, 147) ? ESSA_SET_STABLE_NODAT | |
1068 | : ESSA_SET_STABLE_IF_RESIDENT)) | |
b31288fa KW |
1069 | return kvm_s390_inject_program_int(vcpu, PGM_SPECIFICATION); |
1070 | ||
190df4a2 CI |
1071 | if (likely(!vcpu->kvm->arch.migration_state)) { |
1072 | /* | |
1073 | * CMMA is enabled in the KVM settings, but is disabled in | |
1074 | * the SIE block and in the mm_context, and we are not doing | |
1075 | * a migration. Enable CMMA in the mm_context. | |
1076 | * Since we need to take a write lock to write to the context | |
1077 | * to avoid races with storage keys handling, we check if the | |
1078 | * value really needs to be written to; if the value is | |
1079 | * already correct, we do nothing and avoid the lock. | |
1080 | */ | |
c9f0a2b8 | 1081 | if (vcpu->kvm->mm->context.uses_cmm == 0) { |
190df4a2 | 1082 | down_write(&vcpu->kvm->mm->mmap_sem); |
c9f0a2b8 | 1083 | vcpu->kvm->mm->context.uses_cmm = 1; |
190df4a2 CI |
1084 | up_write(&vcpu->kvm->mm->mmap_sem); |
1085 | } | |
1086 | /* | |
1087 | * If we are here, we are supposed to have CMMA enabled in | |
1088 | * the SIE block. Enabling CMMA works on a per-CPU basis, | |
1089 | * while the context use_cmma flag is per process. | |
1090 | * It's possible that the context flag is enabled and the | |
1091 | * SIE flag is not, so we set the flag always; if it was | |
1092 | * already set, nothing changes, otherwise we enable it | |
1093 | * on this CPU too. | |
1094 | */ | |
1095 | vcpu->arch.sie_block->ecb2 |= ECB2_CMMA; | |
1096 | /* Retry the ESSA instruction */ | |
1097 | kvm_s390_retry_instr(vcpu); | |
1098 | } else { | |
1099 | /* Account for the possible extra cbrl entry */ | |
1100 | i = do_essa(vcpu, orc); | |
1101 | if (i < 0) | |
1102 | return i; | |
1103 | entries += i; | |
1104 | } | |
b31288fa KW |
1105 | vcpu->arch.sie_block->cbrlo &= PAGE_MASK; /* reset nceo */ |
1106 | cbrlo = phys_to_virt(vcpu->arch.sie_block->cbrlo); | |
1107 | down_read(&gmap->mm->mmap_sem); | |
4a5e7e38 DH |
1108 | for (i = 0; i < entries; ++i) |
1109 | __gmap_zap(gmap, cbrlo[i]); | |
b31288fa | 1110 | up_read(&gmap->mm->mmap_sem); |
b31288fa KW |
1111 | return 0; |
1112 | } | |
1113 | ||
48a3e950 CH |
1114 | int kvm_s390_handle_b9(struct kvm_vcpu *vcpu) |
1115 | { | |
6db4263f CB |
1116 | switch (vcpu->arch.sie_block->ipa & 0x00ff) { |
1117 | case 0x8a: | |
1118 | case 0x8e: | |
1119 | case 0x8f: | |
1120 | return handle_ipte_interlock(vcpu); | |
1121 | case 0x8d: | |
1122 | return handle_epsw(vcpu); | |
1123 | case 0xab: | |
1124 | return handle_essa(vcpu); | |
1125 | case 0xaf: | |
1126 | return handle_pfmf(vcpu); | |
1127 | default: | |
1128 | return -EOPNOTSUPP; | |
1129 | } | |
48a3e950 CH |
1130 | } |
1131 | ||
953ed88d TH |
1132 | int kvm_s390_handle_lctl(struct kvm_vcpu *vcpu) |
1133 | { | |
1134 | int reg1 = (vcpu->arch.sie_block->ipa & 0x00f0) >> 4; | |
1135 | int reg3 = vcpu->arch.sie_block->ipa & 0x000f; | |
fc56eb66 HC |
1136 | int reg, rc, nr_regs; |
1137 | u32 ctl_array[16]; | |
f987a3ee | 1138 | u64 ga; |
27f67f87 | 1139 | u8 ar; |
953ed88d TH |
1140 | |
1141 | vcpu->stat.instruction_lctl++; | |
1142 | ||
1143 | if (vcpu->arch.sie_block->gpsw.mask & PSW_MASK_PSTATE) | |
1144 | return kvm_s390_inject_program_int(vcpu, PGM_PRIVILEGED_OP); | |
1145 | ||
8ae04b8f | 1146 | ga = kvm_s390_get_base_disp_rs(vcpu, &ar); |
953ed88d | 1147 | |
f987a3ee | 1148 | if (ga & 3) |
953ed88d TH |
1149 | return kvm_s390_inject_program_int(vcpu, PGM_SPECIFICATION); |
1150 | ||
7cbde76b | 1151 | VCPU_EVENT(vcpu, 4, "LCTL: r1:%d, r3:%d, addr: 0x%llx", reg1, reg3, ga); |
f987a3ee | 1152 | trace_kvm_s390_handle_lctl(vcpu, 0, reg1, reg3, ga); |
953ed88d | 1153 | |
fc56eb66 | 1154 | nr_regs = ((reg3 - reg1) & 0xf) + 1; |
8ae04b8f | 1155 | rc = read_guest(vcpu, ga, ar, ctl_array, nr_regs * sizeof(u32)); |
fc56eb66 HC |
1156 | if (rc) |
1157 | return kvm_s390_inject_prog_cond(vcpu, rc); | |
953ed88d | 1158 | reg = reg1; |
fc56eb66 | 1159 | nr_regs = 0; |
953ed88d | 1160 | do { |
953ed88d | 1161 | vcpu->arch.sie_block->gcr[reg] &= 0xffffffff00000000ul; |
fc56eb66 | 1162 | vcpu->arch.sie_block->gcr[reg] |= ctl_array[nr_regs++]; |
953ed88d TH |
1163 | if (reg == reg3) |
1164 | break; | |
1165 | reg = (reg + 1) % 16; | |
1166 | } while (1); | |
2dca485f | 1167 | kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu); |
953ed88d TH |
1168 | return 0; |
1169 | } | |
1170 | ||
aba07508 DH |
1171 | int kvm_s390_handle_stctl(struct kvm_vcpu *vcpu) |
1172 | { | |
1173 | int reg1 = (vcpu->arch.sie_block->ipa & 0x00f0) >> 4; | |
1174 | int reg3 = vcpu->arch.sie_block->ipa & 0x000f; | |
fc56eb66 HC |
1175 | int reg, rc, nr_regs; |
1176 | u32 ctl_array[16]; | |
aba07508 | 1177 | u64 ga; |
27f67f87 | 1178 | u8 ar; |
aba07508 DH |
1179 | |
1180 | vcpu->stat.instruction_stctl++; | |
1181 | ||
1182 | if (vcpu->arch.sie_block->gpsw.mask & PSW_MASK_PSTATE) | |
1183 | return kvm_s390_inject_program_int(vcpu, PGM_PRIVILEGED_OP); | |
1184 | ||
8ae04b8f | 1185 | ga = kvm_s390_get_base_disp_rs(vcpu, &ar); |
aba07508 DH |
1186 | |
1187 | if (ga & 3) | |
1188 | return kvm_s390_inject_program_int(vcpu, PGM_SPECIFICATION); | |
1189 | ||
7cbde76b | 1190 | VCPU_EVENT(vcpu, 4, "STCTL r1:%d, r3:%d, addr: 0x%llx", reg1, reg3, ga); |
aba07508 DH |
1191 | trace_kvm_s390_handle_stctl(vcpu, 0, reg1, reg3, ga); |
1192 | ||
1193 | reg = reg1; | |
fc56eb66 | 1194 | nr_regs = 0; |
aba07508 | 1195 | do { |
fc56eb66 | 1196 | ctl_array[nr_regs++] = vcpu->arch.sie_block->gcr[reg]; |
aba07508 DH |
1197 | if (reg == reg3) |
1198 | break; | |
1199 | reg = (reg + 1) % 16; | |
1200 | } while (1); | |
8ae04b8f | 1201 | rc = write_guest(vcpu, ga, ar, ctl_array, nr_regs * sizeof(u32)); |
fc56eb66 | 1202 | return rc ? kvm_s390_inject_prog_cond(vcpu, rc) : 0; |
aba07508 DH |
1203 | } |
1204 | ||
953ed88d TH |
1205 | static int handle_lctlg(struct kvm_vcpu *vcpu) |
1206 | { | |
1207 | int reg1 = (vcpu->arch.sie_block->ipa & 0x00f0) >> 4; | |
1208 | int reg3 = vcpu->arch.sie_block->ipa & 0x000f; | |
fc56eb66 HC |
1209 | int reg, rc, nr_regs; |
1210 | u64 ctl_array[16]; | |
1211 | u64 ga; | |
27f67f87 | 1212 | u8 ar; |
953ed88d TH |
1213 | |
1214 | vcpu->stat.instruction_lctlg++; | |
1215 | ||
1216 | if (vcpu->arch.sie_block->gpsw.mask & PSW_MASK_PSTATE) | |
1217 | return kvm_s390_inject_program_int(vcpu, PGM_PRIVILEGED_OP); | |
1218 | ||
8ae04b8f | 1219 | ga = kvm_s390_get_base_disp_rsy(vcpu, &ar); |
953ed88d | 1220 | |
f987a3ee | 1221 | if (ga & 7) |
953ed88d TH |
1222 | return kvm_s390_inject_program_int(vcpu, PGM_SPECIFICATION); |
1223 | ||
7cbde76b | 1224 | VCPU_EVENT(vcpu, 4, "LCTLG: r1:%d, r3:%d, addr: 0x%llx", reg1, reg3, ga); |
f987a3ee | 1225 | trace_kvm_s390_handle_lctl(vcpu, 1, reg1, reg3, ga); |
953ed88d | 1226 | |
fc56eb66 | 1227 | nr_regs = ((reg3 - reg1) & 0xf) + 1; |
8ae04b8f | 1228 | rc = read_guest(vcpu, ga, ar, ctl_array, nr_regs * sizeof(u64)); |
fc56eb66 HC |
1229 | if (rc) |
1230 | return kvm_s390_inject_prog_cond(vcpu, rc); | |
1231 | reg = reg1; | |
1232 | nr_regs = 0; | |
953ed88d | 1233 | do { |
fc56eb66 | 1234 | vcpu->arch.sie_block->gcr[reg] = ctl_array[nr_regs++]; |
953ed88d TH |
1235 | if (reg == reg3) |
1236 | break; | |
1237 | reg = (reg + 1) % 16; | |
1238 | } while (1); | |
2dca485f | 1239 | kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu); |
953ed88d TH |
1240 | return 0; |
1241 | } | |
1242 | ||
aba07508 DH |
1243 | static int handle_stctg(struct kvm_vcpu *vcpu) |
1244 | { | |
1245 | int reg1 = (vcpu->arch.sie_block->ipa & 0x00f0) >> 4; | |
1246 | int reg3 = vcpu->arch.sie_block->ipa & 0x000f; | |
fc56eb66 HC |
1247 | int reg, rc, nr_regs; |
1248 | u64 ctl_array[16]; | |
1249 | u64 ga; | |
27f67f87 | 1250 | u8 ar; |
aba07508 DH |
1251 | |
1252 | vcpu->stat.instruction_stctg++; | |
1253 | ||
1254 | if (vcpu->arch.sie_block->gpsw.mask & PSW_MASK_PSTATE) | |
1255 | return kvm_s390_inject_program_int(vcpu, PGM_PRIVILEGED_OP); | |
1256 | ||
8ae04b8f | 1257 | ga = kvm_s390_get_base_disp_rsy(vcpu, &ar); |
aba07508 DH |
1258 | |
1259 | if (ga & 7) | |
1260 | return kvm_s390_inject_program_int(vcpu, PGM_SPECIFICATION); | |
1261 | ||
7cbde76b | 1262 | VCPU_EVENT(vcpu, 4, "STCTG r1:%d, r3:%d, addr: 0x%llx", reg1, reg3, ga); |
aba07508 DH |
1263 | trace_kvm_s390_handle_stctl(vcpu, 1, reg1, reg3, ga); |
1264 | ||
fc56eb66 HC |
1265 | reg = reg1; |
1266 | nr_regs = 0; | |
aba07508 | 1267 | do { |
fc56eb66 | 1268 | ctl_array[nr_regs++] = vcpu->arch.sie_block->gcr[reg]; |
aba07508 DH |
1269 | if (reg == reg3) |
1270 | break; | |
1271 | reg = (reg + 1) % 16; | |
1272 | } while (1); | |
8ae04b8f | 1273 | rc = write_guest(vcpu, ga, ar, ctl_array, nr_regs * sizeof(u64)); |
fc56eb66 | 1274 | return rc ? kvm_s390_inject_prog_cond(vcpu, rc) : 0; |
aba07508 DH |
1275 | } |
1276 | ||
953ed88d | 1277 | int kvm_s390_handle_eb(struct kvm_vcpu *vcpu) |
f379aae5 | 1278 | { |
6db4263f CB |
1279 | switch (vcpu->arch.sie_block->ipb & 0x000000ff) { |
1280 | case 0x25: | |
1281 | return handle_stctg(vcpu); | |
1282 | case 0x2f: | |
1283 | return handle_lctlg(vcpu); | |
1284 | case 0x60: | |
1285 | case 0x61: | |
1286 | case 0x62: | |
1287 | return handle_ri(vcpu); | |
1288 | default: | |
1289 | return -EOPNOTSUPP; | |
1290 | } | |
f379aae5 CH |
1291 | } |
1292 | ||
bb25b9ba CB |
1293 | static int handle_tprot(struct kvm_vcpu *vcpu) |
1294 | { | |
b1c571a5 | 1295 | u64 address1, address2; |
a0465f9a TH |
1296 | unsigned long hva, gpa; |
1297 | int ret = 0, cc = 0; | |
1298 | bool writable; | |
27f67f87 | 1299 | u8 ar; |
bb25b9ba CB |
1300 | |
1301 | vcpu->stat.instruction_tprot++; | |
1302 | ||
f9f6bbc6 TH |
1303 | if (vcpu->arch.sie_block->gpsw.mask & PSW_MASK_PSTATE) |
1304 | return kvm_s390_inject_program_int(vcpu, PGM_PRIVILEGED_OP); | |
1305 | ||
8ae04b8f | 1306 | kvm_s390_get_base_disp_sse(vcpu, &address1, &address2, &ar, NULL); |
b1c571a5 | 1307 | |
bb25b9ba CB |
1308 | /* we only handle the Linux memory detection case: |
1309 | * access key == 0 | |
bb25b9ba CB |
1310 | * everything else goes to userspace. */ |
1311 | if (address2 & 0xf0) | |
1312 | return -EOPNOTSUPP; | |
1313 | if (vcpu->arch.sie_block->gpsw.mask & PSW_MASK_DAT) | |
a0465f9a | 1314 | ipte_lock(vcpu); |
92c96321 | 1315 | ret = guest_translate_address(vcpu, address1, ar, &gpa, GACC_STORE); |
a0465f9a TH |
1316 | if (ret == PGM_PROTECTION) { |
1317 | /* Write protected? Try again with read-only... */ | |
1318 | cc = 1; | |
92c96321 DH |
1319 | ret = guest_translate_address(vcpu, address1, ar, &gpa, |
1320 | GACC_FETCH); | |
a0465f9a TH |
1321 | } |
1322 | if (ret) { | |
1323 | if (ret == PGM_ADDRESSING || ret == PGM_TRANSLATION_SPEC) { | |
1324 | ret = kvm_s390_inject_program_int(vcpu, ret); | |
1325 | } else if (ret > 0) { | |
1326 | /* Translation not available */ | |
1327 | kvm_s390_set_psw_cc(vcpu, 3); | |
1328 | ret = 0; | |
1329 | } | |
1330 | goto out_unlock; | |
1331 | } | |
59a1fa2d | 1332 | |
a0465f9a TH |
1333 | hva = gfn_to_hva_prot(vcpu->kvm, gpa_to_gfn(gpa), &writable); |
1334 | if (kvm_is_error_hva(hva)) { | |
1335 | ret = kvm_s390_inject_program_int(vcpu, PGM_ADDRESSING); | |
1336 | } else { | |
1337 | if (!writable) | |
1338 | cc = 1; /* Write not permitted ==> read-only */ | |
1339 | kvm_s390_set_psw_cc(vcpu, cc); | |
1340 | /* Note: CC2 only occurs for storage keys (not supported yet) */ | |
1341 | } | |
1342 | out_unlock: | |
1343 | if (vcpu->arch.sie_block->gpsw.mask & PSW_MASK_DAT) | |
1344 | ipte_unlock(vcpu); | |
1345 | return ret; | |
bb25b9ba CB |
1346 | } |
1347 | ||
1348 | int kvm_s390_handle_e5(struct kvm_vcpu *vcpu) | |
1349 | { | |
6db4263f CB |
1350 | switch (vcpu->arch.sie_block->ipa & 0x00ff) { |
1351 | case 0x01: | |
bb25b9ba | 1352 | return handle_tprot(vcpu); |
6db4263f CB |
1353 | default: |
1354 | return -EOPNOTSUPP; | |
1355 | } | |
bb25b9ba CB |
1356 | } |
1357 | ||
8c3f61e2 CH |
1358 | static int handle_sckpf(struct kvm_vcpu *vcpu) |
1359 | { | |
1360 | u32 value; | |
1361 | ||
a37cb07a CB |
1362 | vcpu->stat.instruction_sckpf++; |
1363 | ||
8c3f61e2 | 1364 | if (vcpu->arch.sie_block->gpsw.mask & PSW_MASK_PSTATE) |
208dd756 | 1365 | return kvm_s390_inject_program_int(vcpu, PGM_PRIVILEGED_OP); |
8c3f61e2 CH |
1366 | |
1367 | if (vcpu->run->s.regs.gprs[0] & 0x00000000ffff0000) | |
1368 | return kvm_s390_inject_program_int(vcpu, | |
1369 | PGM_SPECIFICATION); | |
1370 | ||
1371 | value = vcpu->run->s.regs.gprs[0] & 0x000000000000ffff; | |
1372 | vcpu->arch.sie_block->todpr = value; | |
1373 | ||
1374 | return 0; | |
1375 | } | |
1376 | ||
9acc317b DH |
1377 | static int handle_ptff(struct kvm_vcpu *vcpu) |
1378 | { | |
a37cb07a CB |
1379 | vcpu->stat.instruction_ptff++; |
1380 | ||
9acc317b DH |
1381 | /* we don't emulate any control instructions yet */ |
1382 | kvm_s390_set_psw_cc(vcpu, 3); | |
1383 | return 0; | |
1384 | } | |
1385 | ||
8c3f61e2 CH |
1386 | int kvm_s390_handle_01(struct kvm_vcpu *vcpu) |
1387 | { | |
6db4263f CB |
1388 | switch (vcpu->arch.sie_block->ipa & 0x00ff) { |
1389 | case 0x04: | |
1390 | return handle_ptff(vcpu); | |
1391 | case 0x07: | |
1392 | return handle_sckpf(vcpu); | |
1393 | default: | |
1394 | return -EOPNOTSUPP; | |
1395 | } | |
8c3f61e2 | 1396 | } |