Commit | Line | Data |
---|---|---|
453423dc | 1 | /* |
a53c8fab | 2 | * handling privileged instructions |
453423dc | 3 | * |
69d0d3a3 | 4 | * Copyright IBM Corp. 2008, 2013 |
453423dc CB |
5 | * |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License (version 2 only) | |
8 | * as published by the Free Software Foundation. | |
9 | * | |
10 | * Author(s): Carsten Otte <cotte@de.ibm.com> | |
11 | * Christian Borntraeger <borntraeger@de.ibm.com> | |
12 | */ | |
13 | ||
14 | #include <linux/kvm.h> | |
5a0e3ad6 | 15 | #include <linux/gfp.h> |
453423dc | 16 | #include <linux/errno.h> |
b13b5dc7 | 17 | #include <linux/compat.h> |
7c959e82 | 18 | #include <asm/asm-offsets.h> |
e769ece3 | 19 | #include <asm/facility.h> |
453423dc CB |
20 | #include <asm/current.h> |
21 | #include <asm/debug.h> | |
22 | #include <asm/ebcdic.h> | |
23 | #include <asm/sysinfo.h> | |
69d0d3a3 CB |
24 | #include <asm/pgtable.h> |
25 | #include <asm/pgalloc.h> | |
26 | #include <asm/io.h> | |
48a3e950 CH |
27 | #include <asm/ptrace.h> |
28 | #include <asm/compat.h> | |
453423dc CB |
29 | #include "gaccess.h" |
30 | #include "kvm-s390.h" | |
5786fffa | 31 | #include "trace.h" |
453423dc | 32 | |
6a3f95a6 TH |
33 | /* Handle SCK (SET CLOCK) interception */ |
34 | static int handle_set_clock(struct kvm_vcpu *vcpu) | |
35 | { | |
36 | struct kvm_vcpu *cpup; | |
37 | s64 hostclk, val; | |
0e7a3f94 | 38 | int i, rc; |
8ae04b8f | 39 | ar_t ar; |
6a3f95a6 | 40 | u64 op2; |
6a3f95a6 TH |
41 | |
42 | if (vcpu->arch.sie_block->gpsw.mask & PSW_MASK_PSTATE) | |
43 | return kvm_s390_inject_program_int(vcpu, PGM_PRIVILEGED_OP); | |
44 | ||
8ae04b8f | 45 | op2 = kvm_s390_get_base_disp_s(vcpu, &ar); |
6a3f95a6 TH |
46 | if (op2 & 7) /* Operand must be on a doubleword boundary */ |
47 | return kvm_s390_inject_program_int(vcpu, PGM_SPECIFICATION); | |
8ae04b8f | 48 | rc = read_guest(vcpu, op2, ar, &val, sizeof(val)); |
0e7a3f94 HC |
49 | if (rc) |
50 | return kvm_s390_inject_prog_cond(vcpu, rc); | |
6a3f95a6 TH |
51 | |
52 | if (store_tod_clock(&hostclk)) { | |
53 | kvm_s390_set_psw_cc(vcpu, 3); | |
54 | return 0; | |
55 | } | |
7cbde76b | 56 | VCPU_EVENT(vcpu, 3, "SCK: setting guest TOD to 0x%llx", val); |
6a3f95a6 TH |
57 | val = (val - hostclk) & ~0x3fUL; |
58 | ||
59 | mutex_lock(&vcpu->kvm->lock); | |
60 | kvm_for_each_vcpu(i, cpup, vcpu->kvm) | |
61 | cpup->arch.sie_block->epoch = val; | |
62 | mutex_unlock(&vcpu->kvm->lock); | |
63 | ||
64 | kvm_s390_set_psw_cc(vcpu, 0); | |
65 | return 0; | |
66 | } | |
67 | ||
453423dc CB |
68 | static int handle_set_prefix(struct kvm_vcpu *vcpu) |
69 | { | |
453423dc | 70 | u64 operand2; |
665170cb HC |
71 | u32 address; |
72 | int rc; | |
8ae04b8f | 73 | ar_t ar; |
453423dc CB |
74 | |
75 | vcpu->stat.instruction_spx++; | |
76 | ||
5087dfa6 TH |
77 | if (vcpu->arch.sie_block->gpsw.mask & PSW_MASK_PSTATE) |
78 | return kvm_s390_inject_program_int(vcpu, PGM_PRIVILEGED_OP); | |
79 | ||
8ae04b8f | 80 | operand2 = kvm_s390_get_base_disp_s(vcpu, &ar); |
453423dc CB |
81 | |
82 | /* must be word boundary */ | |
db4a29cb HC |
83 | if (operand2 & 3) |
84 | return kvm_s390_inject_program_int(vcpu, PGM_SPECIFICATION); | |
453423dc CB |
85 | |
86 | /* get the value */ | |
8ae04b8f | 87 | rc = read_guest(vcpu, operand2, ar, &address, sizeof(address)); |
665170cb HC |
88 | if (rc) |
89 | return kvm_s390_inject_prog_cond(vcpu, rc); | |
90 | ||
91 | address &= 0x7fffe000u; | |
92 | ||
93 | /* | |
94 | * Make sure the new value is valid memory. We only need to check the | |
95 | * first page, since address is 8k aligned and memory pieces are always | |
96 | * at least 1MB aligned and have at least a size of 1MB. | |
97 | */ | |
98 | if (kvm_is_error_gpa(vcpu->kvm, address)) | |
db4a29cb | 99 | return kvm_s390_inject_program_int(vcpu, PGM_ADDRESSING); |
453423dc | 100 | |
8d26cf7b | 101 | kvm_s390_set_prefix(vcpu, address); |
5786fffa | 102 | trace_kvm_s390_handle_prefix(vcpu, 1, address); |
453423dc CB |
103 | return 0; |
104 | } | |
105 | ||
106 | static int handle_store_prefix(struct kvm_vcpu *vcpu) | |
107 | { | |
453423dc CB |
108 | u64 operand2; |
109 | u32 address; | |
f748f4a7 | 110 | int rc; |
8ae04b8f | 111 | ar_t ar; |
453423dc CB |
112 | |
113 | vcpu->stat.instruction_stpx++; | |
b1c571a5 | 114 | |
5087dfa6 TH |
115 | if (vcpu->arch.sie_block->gpsw.mask & PSW_MASK_PSTATE) |
116 | return kvm_s390_inject_program_int(vcpu, PGM_PRIVILEGED_OP); | |
117 | ||
8ae04b8f | 118 | operand2 = kvm_s390_get_base_disp_s(vcpu, &ar); |
453423dc CB |
119 | |
120 | /* must be word boundary */ | |
db4a29cb HC |
121 | if (operand2 & 3) |
122 | return kvm_s390_inject_program_int(vcpu, PGM_SPECIFICATION); | |
453423dc | 123 | |
fda902cb | 124 | address = kvm_s390_get_prefix(vcpu); |
453423dc CB |
125 | |
126 | /* get the value */ | |
8ae04b8f | 127 | rc = write_guest(vcpu, operand2, ar, &address, sizeof(address)); |
f748f4a7 HC |
128 | if (rc) |
129 | return kvm_s390_inject_prog_cond(vcpu, rc); | |
453423dc | 130 | |
7cbde76b | 131 | VCPU_EVENT(vcpu, 3, "STPX: storing prefix 0x%x into 0x%llx", address, operand2); |
5786fffa | 132 | trace_kvm_s390_handle_prefix(vcpu, 0, address); |
453423dc CB |
133 | return 0; |
134 | } | |
135 | ||
136 | static int handle_store_cpu_address(struct kvm_vcpu *vcpu) | |
137 | { | |
8b96de0e HC |
138 | u16 vcpu_id = vcpu->vcpu_id; |
139 | u64 ga; | |
140 | int rc; | |
8ae04b8f | 141 | ar_t ar; |
453423dc CB |
142 | |
143 | vcpu->stat.instruction_stap++; | |
b1c571a5 | 144 | |
5087dfa6 TH |
145 | if (vcpu->arch.sie_block->gpsw.mask & PSW_MASK_PSTATE) |
146 | return kvm_s390_inject_program_int(vcpu, PGM_PRIVILEGED_OP); | |
147 | ||
8ae04b8f | 148 | ga = kvm_s390_get_base_disp_s(vcpu, &ar); |
453423dc | 149 | |
8b96de0e | 150 | if (ga & 1) |
db4a29cb | 151 | return kvm_s390_inject_program_int(vcpu, PGM_SPECIFICATION); |
453423dc | 152 | |
8ae04b8f | 153 | rc = write_guest(vcpu, ga, ar, &vcpu_id, sizeof(vcpu_id)); |
8b96de0e HC |
154 | if (rc) |
155 | return kvm_s390_inject_prog_cond(vcpu, rc); | |
453423dc | 156 | |
7cbde76b | 157 | VCPU_EVENT(vcpu, 3, "STAP: storing cpu address (%u) to 0x%llx", vcpu_id, ga); |
8b96de0e | 158 | trace_kvm_s390_handle_stap(vcpu, ga); |
453423dc CB |
159 | return 0; |
160 | } | |
161 | ||
3ac8e380 | 162 | static int __skey_check_enable(struct kvm_vcpu *vcpu) |
693ffc08 | 163 | { |
3ac8e380 | 164 | int rc = 0; |
693ffc08 | 165 | if (!(vcpu->arch.sie_block->ictl & (ICTL_ISKE | ICTL_SSKE | ICTL_RRBE))) |
3ac8e380 | 166 | return rc; |
693ffc08 | 167 | |
3ac8e380 | 168 | rc = s390_enable_skey(); |
7cbde76b | 169 | VCPU_EVENT(vcpu, 3, "%s", "enabling storage keys for guest"); |
693ffc08 DD |
170 | trace_kvm_s390_skey_related_inst(vcpu); |
171 | vcpu->arch.sie_block->ictl &= ~(ICTL_ISKE | ICTL_SSKE | ICTL_RRBE); | |
3ac8e380 | 172 | return rc; |
693ffc08 DD |
173 | } |
174 | ||
175 | ||
453423dc CB |
176 | static int handle_skey(struct kvm_vcpu *vcpu) |
177 | { | |
3ac8e380 | 178 | int rc = __skey_check_enable(vcpu); |
693ffc08 | 179 | |
3ac8e380 DD |
180 | if (rc) |
181 | return rc; | |
453423dc | 182 | vcpu->stat.instruction_storage_key++; |
5087dfa6 TH |
183 | |
184 | if (vcpu->arch.sie_block->gpsw.mask & PSW_MASK_PSTATE) | |
185 | return kvm_s390_inject_program_int(vcpu, PGM_PRIVILEGED_OP); | |
186 | ||
04b41acd | 187 | kvm_s390_rewind_psw(vcpu, 4); |
453423dc CB |
188 | VCPU_EVENT(vcpu, 4, "%s", "retrying storage key operation"); |
189 | return 0; | |
190 | } | |
191 | ||
8a242234 HC |
192 | static int handle_ipte_interlock(struct kvm_vcpu *vcpu) |
193 | { | |
8a242234 | 194 | vcpu->stat.instruction_ipte_interlock++; |
04b41acd | 195 | if (psw_bits(vcpu->arch.sie_block->gpsw).p) |
8a242234 HC |
196 | return kvm_s390_inject_program_int(vcpu, PGM_PRIVILEGED_OP); |
197 | wait_event(vcpu->kvm->arch.ipte_wq, !ipte_lock_held(vcpu)); | |
04b41acd | 198 | kvm_s390_rewind_psw(vcpu, 4); |
8a242234 HC |
199 | VCPU_EVENT(vcpu, 4, "%s", "retrying ipte interlock operation"); |
200 | return 0; | |
201 | } | |
202 | ||
aca84241 TH |
203 | static int handle_test_block(struct kvm_vcpu *vcpu) |
204 | { | |
aca84241 TH |
205 | gpa_t addr; |
206 | int reg2; | |
207 | ||
208 | if (vcpu->arch.sie_block->gpsw.mask & PSW_MASK_PSTATE) | |
209 | return kvm_s390_inject_program_int(vcpu, PGM_PRIVILEGED_OP); | |
210 | ||
211 | kvm_s390_get_regs_rre(vcpu, NULL, ®2); | |
212 | addr = vcpu->run->s.regs.gprs[reg2] & PAGE_MASK; | |
e45efa28 | 213 | addr = kvm_s390_logical_to_effective(vcpu, addr); |
dd9e5b7b | 214 | if (kvm_s390_check_low_addr_prot_real(vcpu, addr)) |
e45efa28 | 215 | return kvm_s390_inject_prog_irq(vcpu, &vcpu->arch.pgm); |
aca84241 TH |
216 | addr = kvm_s390_real_to_abs(vcpu, addr); |
217 | ||
ef23e779 | 218 | if (kvm_is_error_gpa(vcpu->kvm, addr)) |
aca84241 TH |
219 | return kvm_s390_inject_program_int(vcpu, PGM_ADDRESSING); |
220 | /* | |
221 | * We don't expect errors on modern systems, and do not care | |
222 | * about storage keys (yet), so let's just clear the page. | |
223 | */ | |
ef23e779 | 224 | if (kvm_clear_guest(vcpu->kvm, addr, PAGE_SIZE)) |
aca84241 TH |
225 | return -EFAULT; |
226 | kvm_s390_set_psw_cc(vcpu, 0); | |
227 | vcpu->run->s.regs.gprs[0] = 0; | |
228 | return 0; | |
229 | } | |
230 | ||
fa6b7fe9 | 231 | static int handle_tpi(struct kvm_vcpu *vcpu) |
453423dc | 232 | { |
fa6b7fe9 | 233 | struct kvm_s390_interrupt_info *inti; |
4799b557 HC |
234 | unsigned long len; |
235 | u32 tpi_data[3]; | |
261520dc | 236 | int rc; |
7c959e82 | 237 | u64 addr; |
8ae04b8f | 238 | ar_t ar; |
fa6b7fe9 | 239 | |
8ae04b8f | 240 | addr = kvm_s390_get_base_disp_s(vcpu, &ar); |
db4a29cb HC |
241 | if (addr & 3) |
242 | return kvm_s390_inject_program_int(vcpu, PGM_SPECIFICATION); | |
261520dc | 243 | |
f092669e | 244 | inti = kvm_s390_get_io_int(vcpu->kvm, vcpu->arch.sie_block->gcr[6], 0); |
261520dc DH |
245 | if (!inti) { |
246 | kvm_s390_set_psw_cc(vcpu, 0); | |
247 | return 0; | |
248 | } | |
249 | ||
4799b557 HC |
250 | tpi_data[0] = inti->io.subchannel_id << 16 | inti->io.subchannel_nr; |
251 | tpi_data[1] = inti->io.io_int_parm; | |
252 | tpi_data[2] = inti->io.io_int_word; | |
7c959e82 HC |
253 | if (addr) { |
254 | /* | |
255 | * Store the two-word I/O interruption code into the | |
256 | * provided area. | |
257 | */ | |
4799b557 | 258 | len = sizeof(tpi_data) - 4; |
8ae04b8f | 259 | rc = write_guest(vcpu, addr, ar, &tpi_data, len); |
261520dc DH |
260 | if (rc) { |
261 | rc = kvm_s390_inject_prog_cond(vcpu, rc); | |
262 | goto reinject_interrupt; | |
263 | } | |
7c959e82 HC |
264 | } else { |
265 | /* | |
266 | * Store the three-word I/O interruption code into | |
267 | * the appropriate lowcore area. | |
268 | */ | |
4799b557 | 269 | len = sizeof(tpi_data); |
261520dc DH |
270 | if (write_guest_lc(vcpu, __LC_SUBCHANNEL_ID, &tpi_data, len)) { |
271 | /* failed writes to the low core are not recoverable */ | |
4799b557 | 272 | rc = -EFAULT; |
261520dc DH |
273 | goto reinject_interrupt; |
274 | } | |
7c959e82 | 275 | } |
261520dc DH |
276 | |
277 | /* irq was successfully handed to the guest */ | |
278 | kfree(inti); | |
279 | kvm_s390_set_psw_cc(vcpu, 1); | |
280 | return 0; | |
281 | reinject_interrupt: | |
2f32d4ea CH |
282 | /* |
283 | * If we encounter a problem storing the interruption code, the | |
284 | * instruction is suppressed from the guest's view: reinject the | |
285 | * interrupt. | |
286 | */ | |
15462e37 DH |
287 | if (kvm_s390_reinject_io_int(vcpu->kvm, inti)) { |
288 | kfree(inti); | |
289 | rc = -EFAULT; | |
290 | } | |
261520dc | 291 | /* don't set the cc, a pgm irq was injected or we drop to user space */ |
4799b557 | 292 | return rc ? -EFAULT : 0; |
453423dc CB |
293 | } |
294 | ||
fa6b7fe9 CH |
295 | static int handle_tsch(struct kvm_vcpu *vcpu) |
296 | { | |
6d3da241 JF |
297 | struct kvm_s390_interrupt_info *inti = NULL; |
298 | const u64 isc_mask = 0xffUL << 24; /* all iscs set */ | |
fa6b7fe9 | 299 | |
6d3da241 JF |
300 | /* a valid schid has at least one bit set */ |
301 | if (vcpu->run->s.regs.gprs[1]) | |
302 | inti = kvm_s390_get_io_int(vcpu->kvm, isc_mask, | |
303 | vcpu->run->s.regs.gprs[1]); | |
fa6b7fe9 CH |
304 | |
305 | /* | |
306 | * Prepare exit to userspace. | |
307 | * We indicate whether we dequeued a pending I/O interrupt | |
308 | * so that userspace can re-inject it if the instruction gets | |
309 | * a program check. While this may re-order the pending I/O | |
310 | * interrupts, this is no problem since the priority is kept | |
311 | * intact. | |
312 | */ | |
313 | vcpu->run->exit_reason = KVM_EXIT_S390_TSCH; | |
314 | vcpu->run->s390_tsch.dequeued = !!inti; | |
315 | if (inti) { | |
316 | vcpu->run->s390_tsch.subchannel_id = inti->io.subchannel_id; | |
317 | vcpu->run->s390_tsch.subchannel_nr = inti->io.subchannel_nr; | |
318 | vcpu->run->s390_tsch.io_int_parm = inti->io.io_int_parm; | |
319 | vcpu->run->s390_tsch.io_int_word = inti->io.io_int_word; | |
320 | } | |
321 | vcpu->run->s390_tsch.ipb = vcpu->arch.sie_block->ipb; | |
322 | kfree(inti); | |
323 | return -EREMOTE; | |
324 | } | |
325 | ||
326 | static int handle_io_inst(struct kvm_vcpu *vcpu) | |
327 | { | |
328 | VCPU_EVENT(vcpu, 4, "%s", "I/O instruction"); | |
329 | ||
5087dfa6 TH |
330 | if (vcpu->arch.sie_block->gpsw.mask & PSW_MASK_PSTATE) |
331 | return kvm_s390_inject_program_int(vcpu, PGM_PRIVILEGED_OP); | |
332 | ||
fa6b7fe9 CH |
333 | if (vcpu->kvm->arch.css_support) { |
334 | /* | |
335 | * Most I/O instructions will be handled by userspace. | |
336 | * Exceptions are tpi and the interrupt portion of tsch. | |
337 | */ | |
338 | if (vcpu->arch.sie_block->ipa == 0xb236) | |
339 | return handle_tpi(vcpu); | |
340 | if (vcpu->arch.sie_block->ipa == 0xb235) | |
341 | return handle_tsch(vcpu); | |
342 | /* Handle in userspace. */ | |
343 | return -EOPNOTSUPP; | |
344 | } else { | |
345 | /* | |
b4a96015 | 346 | * Set condition code 3 to stop the guest from issuing channel |
fa6b7fe9 CH |
347 | * I/O instructions. |
348 | */ | |
ea828ebf | 349 | kvm_s390_set_psw_cc(vcpu, 3); |
fa6b7fe9 CH |
350 | return 0; |
351 | } | |
352 | } | |
353 | ||
453423dc CB |
354 | static int handle_stfl(struct kvm_vcpu *vcpu) |
355 | { | |
453423dc | 356 | int rc; |
9d8d5786 | 357 | unsigned int fac; |
453423dc CB |
358 | |
359 | vcpu->stat.instruction_stfl++; | |
5087dfa6 TH |
360 | |
361 | if (vcpu->arch.sie_block->gpsw.mask & PSW_MASK_PSTATE) | |
362 | return kvm_s390_inject_program_int(vcpu, PGM_PRIVILEGED_OP); | |
363 | ||
9d8d5786 MM |
364 | /* |
365 | * We need to shift the lower 32 facility bits (bit 0-31) from a u64 | |
366 | * into a u32 memory representation. They will remain bits 0-31. | |
367 | */ | |
981467c9 | 368 | fac = *vcpu->kvm->arch.model.fac->list >> 32; |
0f9701c6 | 369 | rc = write_guest_lc(vcpu, offsetof(struct _lowcore, stfl_fac_list), |
9d8d5786 | 370 | &fac, sizeof(fac)); |
dc5008b9 | 371 | if (rc) |
0f9701c6 | 372 | return rc; |
7cbde76b | 373 | VCPU_EVENT(vcpu, 3, "STFL: store facility list 0x%x", fac); |
9d8d5786 | 374 | trace_kvm_s390_handle_stfl(vcpu, fac); |
453423dc CB |
375 | return 0; |
376 | } | |
377 | ||
48a3e950 CH |
378 | #define PSW_MASK_ADDR_MODE (PSW_MASK_EA | PSW_MASK_BA) |
379 | #define PSW_MASK_UNASSIGNED 0xb80800fe7fffffffUL | |
d21683ea | 380 | #define PSW_ADDR_24 0x0000000000ffffffUL |
48a3e950 CH |
381 | #define PSW_ADDR_31 0x000000007fffffffUL |
382 | ||
a3fb577e TH |
383 | int is_valid_psw(psw_t *psw) |
384 | { | |
3736b874 HC |
385 | if (psw->mask & PSW_MASK_UNASSIGNED) |
386 | return 0; | |
387 | if ((psw->mask & PSW_MASK_ADDR_MODE) == PSW_MASK_BA) { | |
388 | if (psw->addr & ~PSW_ADDR_31) | |
389 | return 0; | |
390 | } | |
391 | if (!(psw->mask & PSW_MASK_ADDR_MODE) && (psw->addr & ~PSW_ADDR_24)) | |
392 | return 0; | |
393 | if ((psw->mask & PSW_MASK_ADDR_MODE) == PSW_MASK_EA) | |
394 | return 0; | |
a3fb577e TH |
395 | if (psw->addr & 1) |
396 | return 0; | |
3736b874 HC |
397 | return 1; |
398 | } | |
399 | ||
48a3e950 CH |
400 | int kvm_s390_handle_lpsw(struct kvm_vcpu *vcpu) |
401 | { | |
3736b874 | 402 | psw_t *gpsw = &vcpu->arch.sie_block->gpsw; |
48a3e950 | 403 | psw_compat_t new_psw; |
3736b874 | 404 | u64 addr; |
2d8bcaed | 405 | int rc; |
8ae04b8f | 406 | ar_t ar; |
48a3e950 | 407 | |
3736b874 | 408 | if (gpsw->mask & PSW_MASK_PSTATE) |
208dd756 TH |
409 | return kvm_s390_inject_program_int(vcpu, PGM_PRIVILEGED_OP); |
410 | ||
8ae04b8f | 411 | addr = kvm_s390_get_base_disp_s(vcpu, &ar); |
6fd0fcc9 HC |
412 | if (addr & 7) |
413 | return kvm_s390_inject_program_int(vcpu, PGM_SPECIFICATION); | |
2d8bcaed | 414 | |
8ae04b8f | 415 | rc = read_guest(vcpu, addr, ar, &new_psw, sizeof(new_psw)); |
2d8bcaed HC |
416 | if (rc) |
417 | return kvm_s390_inject_prog_cond(vcpu, rc); | |
6fd0fcc9 HC |
418 | if (!(new_psw.mask & PSW32_MASK_BASE)) |
419 | return kvm_s390_inject_program_int(vcpu, PGM_SPECIFICATION); | |
3736b874 HC |
420 | gpsw->mask = (new_psw.mask & ~PSW32_MASK_BASE) << 32; |
421 | gpsw->mask |= new_psw.addr & PSW32_ADDR_AMODE; | |
422 | gpsw->addr = new_psw.addr & ~PSW32_ADDR_AMODE; | |
423 | if (!is_valid_psw(gpsw)) | |
6fd0fcc9 | 424 | return kvm_s390_inject_program_int(vcpu, PGM_SPECIFICATION); |
48a3e950 CH |
425 | return 0; |
426 | } | |
427 | ||
428 | static int handle_lpswe(struct kvm_vcpu *vcpu) | |
429 | { | |
48a3e950 | 430 | psw_t new_psw; |
3736b874 | 431 | u64 addr; |
2d8bcaed | 432 | int rc; |
8ae04b8f | 433 | ar_t ar; |
48a3e950 | 434 | |
5087dfa6 TH |
435 | if (vcpu->arch.sie_block->gpsw.mask & PSW_MASK_PSTATE) |
436 | return kvm_s390_inject_program_int(vcpu, PGM_PRIVILEGED_OP); | |
437 | ||
8ae04b8f | 438 | addr = kvm_s390_get_base_disp_s(vcpu, &ar); |
6fd0fcc9 HC |
439 | if (addr & 7) |
440 | return kvm_s390_inject_program_int(vcpu, PGM_SPECIFICATION); | |
8ae04b8f | 441 | rc = read_guest(vcpu, addr, ar, &new_psw, sizeof(new_psw)); |
2d8bcaed HC |
442 | if (rc) |
443 | return kvm_s390_inject_prog_cond(vcpu, rc); | |
3736b874 HC |
444 | vcpu->arch.sie_block->gpsw = new_psw; |
445 | if (!is_valid_psw(&vcpu->arch.sie_block->gpsw)) | |
6fd0fcc9 | 446 | return kvm_s390_inject_program_int(vcpu, PGM_SPECIFICATION); |
48a3e950 CH |
447 | return 0; |
448 | } | |
449 | ||
453423dc CB |
450 | static int handle_stidp(struct kvm_vcpu *vcpu) |
451 | { | |
7d777d78 | 452 | u64 stidp_data = vcpu->arch.stidp_data; |
453423dc | 453 | u64 operand2; |
7d777d78 | 454 | int rc; |
8ae04b8f | 455 | ar_t ar; |
453423dc CB |
456 | |
457 | vcpu->stat.instruction_stidp++; | |
b1c571a5 | 458 | |
5087dfa6 TH |
459 | if (vcpu->arch.sie_block->gpsw.mask & PSW_MASK_PSTATE) |
460 | return kvm_s390_inject_program_int(vcpu, PGM_PRIVILEGED_OP); | |
461 | ||
8ae04b8f | 462 | operand2 = kvm_s390_get_base_disp_s(vcpu, &ar); |
453423dc | 463 | |
db4a29cb HC |
464 | if (operand2 & 7) |
465 | return kvm_s390_inject_program_int(vcpu, PGM_SPECIFICATION); | |
453423dc | 466 | |
8ae04b8f | 467 | rc = write_guest(vcpu, operand2, ar, &stidp_data, sizeof(stidp_data)); |
7d777d78 HC |
468 | if (rc) |
469 | return kvm_s390_inject_prog_cond(vcpu, rc); | |
453423dc | 470 | |
7cbde76b | 471 | VCPU_EVENT(vcpu, 3, "STIDP: store cpu id 0x%llx", stidp_data); |
453423dc CB |
472 | return 0; |
473 | } | |
474 | ||
475 | static void handle_stsi_3_2_2(struct kvm_vcpu *vcpu, struct sysinfo_3_2_2 *mem) | |
476 | { | |
453423dc CB |
477 | int cpus = 0; |
478 | int n; | |
479 | ||
ff520a63 | 480 | cpus = atomic_read(&vcpu->kvm->online_vcpus); |
453423dc CB |
481 | |
482 | /* deal with other level 3 hypervisors */ | |
caf757c6 | 483 | if (stsi(mem, 3, 2, 2)) |
453423dc CB |
484 | mem->count = 0; |
485 | if (mem->count < 8) | |
486 | mem->count++; | |
487 | for (n = mem->count - 1; n > 0 ; n--) | |
488 | memcpy(&mem->vm[n], &mem->vm[n - 1], sizeof(mem->vm[0])); | |
489 | ||
b75f4c9a | 490 | memset(&mem->vm[0], 0, sizeof(mem->vm[0])); |
453423dc CB |
491 | mem->vm[0].cpus_total = cpus; |
492 | mem->vm[0].cpus_configured = cpus; | |
493 | mem->vm[0].cpus_standby = 0; | |
494 | mem->vm[0].cpus_reserved = 0; | |
495 | mem->vm[0].caf = 1000; | |
496 | memcpy(mem->vm[0].name, "KVMguest", 8); | |
497 | ASCEBC(mem->vm[0].name, 8); | |
498 | memcpy(mem->vm[0].cpi, "KVM/Linux ", 16); | |
499 | ASCEBC(mem->vm[0].cpi, 16); | |
500 | } | |
501 | ||
e44fc8c9 ET |
502 | static void insert_stsi_usr_data(struct kvm_vcpu *vcpu, u64 addr, ar_t ar, |
503 | u8 fc, u8 sel1, u16 sel2) | |
504 | { | |
505 | vcpu->run->exit_reason = KVM_EXIT_S390_STSI; | |
506 | vcpu->run->s390_stsi.addr = addr; | |
507 | vcpu->run->s390_stsi.ar = ar; | |
508 | vcpu->run->s390_stsi.fc = fc; | |
509 | vcpu->run->s390_stsi.sel1 = sel1; | |
510 | vcpu->run->s390_stsi.sel2 = sel2; | |
511 | } | |
512 | ||
453423dc CB |
513 | static int handle_stsi(struct kvm_vcpu *vcpu) |
514 | { | |
5a32c1af CB |
515 | int fc = (vcpu->run->s.regs.gprs[0] & 0xf0000000) >> 28; |
516 | int sel1 = vcpu->run->s.regs.gprs[0] & 0xff; | |
517 | int sel2 = vcpu->run->s.regs.gprs[1] & 0xffff; | |
c51f068c | 518 | unsigned long mem = 0; |
453423dc | 519 | u64 operand2; |
db4a29cb | 520 | int rc = 0; |
8ae04b8f | 521 | ar_t ar; |
453423dc CB |
522 | |
523 | vcpu->stat.instruction_stsi++; | |
7cbde76b | 524 | VCPU_EVENT(vcpu, 3, "STSI: fc: %u sel1: %u sel2: %u", fc, sel1, sel2); |
453423dc | 525 | |
5087dfa6 TH |
526 | if (vcpu->arch.sie_block->gpsw.mask & PSW_MASK_PSTATE) |
527 | return kvm_s390_inject_program_int(vcpu, PGM_PRIVILEGED_OP); | |
528 | ||
87d41fb4 | 529 | if (fc > 3) { |
ea828ebf | 530 | kvm_s390_set_psw_cc(vcpu, 3); |
87d41fb4 TH |
531 | return 0; |
532 | } | |
453423dc | 533 | |
87d41fb4 TH |
534 | if (vcpu->run->s.regs.gprs[0] & 0x0fffff00 |
535 | || vcpu->run->s.regs.gprs[1] & 0xffff0000) | |
453423dc CB |
536 | return kvm_s390_inject_program_int(vcpu, PGM_SPECIFICATION); |
537 | ||
87d41fb4 | 538 | if (fc == 0) { |
5a32c1af | 539 | vcpu->run->s.regs.gprs[0] = 3 << 28; |
ea828ebf | 540 | kvm_s390_set_psw_cc(vcpu, 0); |
453423dc | 541 | return 0; |
87d41fb4 TH |
542 | } |
543 | ||
8ae04b8f | 544 | operand2 = kvm_s390_get_base_disp_s(vcpu, &ar); |
87d41fb4 TH |
545 | |
546 | if (operand2 & 0xfff) | |
547 | return kvm_s390_inject_program_int(vcpu, PGM_SPECIFICATION); | |
548 | ||
549 | switch (fc) { | |
453423dc CB |
550 | case 1: /* same handling for 1 and 2 */ |
551 | case 2: | |
552 | mem = get_zeroed_page(GFP_KERNEL); | |
553 | if (!mem) | |
c51f068c | 554 | goto out_no_data; |
caf757c6 | 555 | if (stsi((void *) mem, fc, sel1, sel2)) |
c51f068c | 556 | goto out_no_data; |
453423dc CB |
557 | break; |
558 | case 3: | |
559 | if (sel1 != 2 || sel2 != 2) | |
c51f068c | 560 | goto out_no_data; |
453423dc CB |
561 | mem = get_zeroed_page(GFP_KERNEL); |
562 | if (!mem) | |
c51f068c | 563 | goto out_no_data; |
453423dc CB |
564 | handle_stsi_3_2_2(vcpu, (void *) mem); |
565 | break; | |
453423dc CB |
566 | } |
567 | ||
8ae04b8f | 568 | rc = write_guest(vcpu, operand2, ar, (void *)mem, PAGE_SIZE); |
645c5bc1 HC |
569 | if (rc) { |
570 | rc = kvm_s390_inject_prog_cond(vcpu, rc); | |
571 | goto out; | |
453423dc | 572 | } |
e44fc8c9 ET |
573 | if (vcpu->kvm->arch.user_stsi) { |
574 | insert_stsi_usr_data(vcpu, operand2, ar, fc, sel1, sel2); | |
575 | rc = -EREMOTE; | |
576 | } | |
5786fffa | 577 | trace_kvm_s390_handle_stsi(vcpu, fc, sel1, sel2, operand2); |
453423dc | 578 | free_page(mem); |
ea828ebf | 579 | kvm_s390_set_psw_cc(vcpu, 0); |
5a32c1af | 580 | vcpu->run->s.regs.gprs[0] = 0; |
e44fc8c9 | 581 | return rc; |
c51f068c | 582 | out_no_data: |
ea828ebf | 583 | kvm_s390_set_psw_cc(vcpu, 3); |
645c5bc1 | 584 | out: |
c51f068c | 585 | free_page(mem); |
db4a29cb | 586 | return rc; |
453423dc CB |
587 | } |
588 | ||
f379aae5 | 589 | static const intercept_handler_t b2_handlers[256] = { |
453423dc | 590 | [0x02] = handle_stidp, |
6a3f95a6 | 591 | [0x04] = handle_set_clock, |
453423dc CB |
592 | [0x10] = handle_set_prefix, |
593 | [0x11] = handle_store_prefix, | |
594 | [0x12] = handle_store_cpu_address, | |
8a242234 | 595 | [0x21] = handle_ipte_interlock, |
453423dc CB |
596 | [0x29] = handle_skey, |
597 | [0x2a] = handle_skey, | |
598 | [0x2b] = handle_skey, | |
aca84241 | 599 | [0x2c] = handle_test_block, |
f379aae5 CH |
600 | [0x30] = handle_io_inst, |
601 | [0x31] = handle_io_inst, | |
602 | [0x32] = handle_io_inst, | |
603 | [0x33] = handle_io_inst, | |
604 | [0x34] = handle_io_inst, | |
605 | [0x35] = handle_io_inst, | |
606 | [0x36] = handle_io_inst, | |
607 | [0x37] = handle_io_inst, | |
608 | [0x38] = handle_io_inst, | |
609 | [0x39] = handle_io_inst, | |
610 | [0x3a] = handle_io_inst, | |
611 | [0x3b] = handle_io_inst, | |
612 | [0x3c] = handle_io_inst, | |
8a242234 | 613 | [0x50] = handle_ipte_interlock, |
f379aae5 CH |
614 | [0x5f] = handle_io_inst, |
615 | [0x74] = handle_io_inst, | |
616 | [0x76] = handle_io_inst, | |
453423dc CB |
617 | [0x7d] = handle_stsi, |
618 | [0xb1] = handle_stfl, | |
48a3e950 | 619 | [0xb2] = handle_lpswe, |
453423dc CB |
620 | }; |
621 | ||
70455a36 | 622 | int kvm_s390_handle_b2(struct kvm_vcpu *vcpu) |
453423dc CB |
623 | { |
624 | intercept_handler_t handler; | |
625 | ||
70455a36 | 626 | /* |
5087dfa6 TH |
627 | * A lot of B2 instructions are priviledged. Here we check for |
628 | * the privileged ones, that we can handle in the kernel. | |
629 | * Anything else goes to userspace. | |
630 | */ | |
f379aae5 | 631 | handler = b2_handlers[vcpu->arch.sie_block->ipa & 0x00ff]; |
5087dfa6 TH |
632 | if (handler) |
633 | return handler(vcpu); | |
634 | ||
b8e660b8 | 635 | return -EOPNOTSUPP; |
453423dc | 636 | } |
bb25b9ba | 637 | |
48a3e950 CH |
638 | static int handle_epsw(struct kvm_vcpu *vcpu) |
639 | { | |
640 | int reg1, reg2; | |
641 | ||
aeb87c3c | 642 | kvm_s390_get_regs_rre(vcpu, ®1, ®2); |
48a3e950 CH |
643 | |
644 | /* This basically extracts the mask half of the psw. */ | |
843200e7 | 645 | vcpu->run->s.regs.gprs[reg1] &= 0xffffffff00000000UL; |
48a3e950 CH |
646 | vcpu->run->s.regs.gprs[reg1] |= vcpu->arch.sie_block->gpsw.mask >> 32; |
647 | if (reg2) { | |
843200e7 | 648 | vcpu->run->s.regs.gprs[reg2] &= 0xffffffff00000000UL; |
48a3e950 | 649 | vcpu->run->s.regs.gprs[reg2] |= |
843200e7 | 650 | vcpu->arch.sie_block->gpsw.mask & 0x00000000ffffffffUL; |
48a3e950 CH |
651 | } |
652 | return 0; | |
653 | } | |
654 | ||
69d0d3a3 CB |
655 | #define PFMF_RESERVED 0xfffc0101UL |
656 | #define PFMF_SK 0x00020000UL | |
657 | #define PFMF_CF 0x00010000UL | |
658 | #define PFMF_UI 0x00008000UL | |
659 | #define PFMF_FSC 0x00007000UL | |
660 | #define PFMF_NQ 0x00000800UL | |
661 | #define PFMF_MR 0x00000400UL | |
662 | #define PFMF_MC 0x00000200UL | |
663 | #define PFMF_KEY 0x000000feUL | |
664 | ||
665 | static int handle_pfmf(struct kvm_vcpu *vcpu) | |
666 | { | |
667 | int reg1, reg2; | |
668 | unsigned long start, end; | |
669 | ||
670 | vcpu->stat.instruction_pfmf++; | |
671 | ||
672 | kvm_s390_get_regs_rre(vcpu, ®1, ®2); | |
673 | ||
674 | if (!MACHINE_HAS_PFMF) | |
675 | return kvm_s390_inject_program_int(vcpu, PGM_OPERATION); | |
676 | ||
677 | if (vcpu->arch.sie_block->gpsw.mask & PSW_MASK_PSTATE) | |
208dd756 | 678 | return kvm_s390_inject_program_int(vcpu, PGM_PRIVILEGED_OP); |
69d0d3a3 CB |
679 | |
680 | if (vcpu->run->s.regs.gprs[reg1] & PFMF_RESERVED) | |
681 | return kvm_s390_inject_program_int(vcpu, PGM_SPECIFICATION); | |
682 | ||
683 | /* Only provide non-quiescing support if the host supports it */ | |
e769ece3 | 684 | if (vcpu->run->s.regs.gprs[reg1] & PFMF_NQ && !test_facility(14)) |
69d0d3a3 CB |
685 | return kvm_s390_inject_program_int(vcpu, PGM_SPECIFICATION); |
686 | ||
687 | /* No support for conditional-SSKE */ | |
688 | if (vcpu->run->s.regs.gprs[reg1] & (PFMF_MR | PFMF_MC)) | |
689 | return kvm_s390_inject_program_int(vcpu, PGM_SPECIFICATION); | |
690 | ||
691 | start = vcpu->run->s.regs.gprs[reg2] & PAGE_MASK; | |
a02689fe | 692 | start = kvm_s390_logical_to_effective(vcpu, start); |
fb34c603 | 693 | |
69d0d3a3 CB |
694 | switch (vcpu->run->s.regs.gprs[reg1] & PFMF_FSC) { |
695 | case 0x00000000: | |
696 | end = (start + (1UL << 12)) & ~((1UL << 12) - 1); | |
697 | break; | |
698 | case 0x00001000: | |
699 | end = (start + (1UL << 20)) & ~((1UL << 20) - 1); | |
700 | break; | |
69d0d3a3 | 701 | case 0x00002000: |
53df84f8 GH |
702 | /* only support 2G frame size if EDAT2 is available and we are |
703 | not in 24-bit addressing mode */ | |
704 | if (!test_kvm_facility(vcpu->kvm, 78) || | |
705 | psw_bits(vcpu->arch.sie_block->gpsw).eaba == PSW_AMODE_24BIT) | |
706 | return kvm_s390_inject_program_int(vcpu, PGM_SPECIFICATION); | |
69d0d3a3 | 707 | end = (start + (1UL << 31)) & ~((1UL << 31) - 1); |
53df84f8 | 708 | break; |
69d0d3a3 CB |
709 | default: |
710 | return kvm_s390_inject_program_int(vcpu, PGM_SPECIFICATION); | |
711 | } | |
a02689fe TH |
712 | |
713 | if (vcpu->run->s.regs.gprs[reg1] & PFMF_CF) { | |
dd9e5b7b | 714 | if (kvm_s390_check_low_addr_prot_real(vcpu, start)) |
a02689fe TH |
715 | return kvm_s390_inject_prog_irq(vcpu, &vcpu->arch.pgm); |
716 | } | |
717 | ||
69d0d3a3 | 718 | while (start < end) { |
fb34c603 TH |
719 | unsigned long useraddr, abs_addr; |
720 | ||
721 | /* Translate guest address to host address */ | |
722 | if ((vcpu->run->s.regs.gprs[reg1] & PFMF_FSC) == 0) | |
723 | abs_addr = kvm_s390_real_to_abs(vcpu, start); | |
724 | else | |
725 | abs_addr = start; | |
726 | useraddr = gfn_to_hva(vcpu->kvm, gpa_to_gfn(abs_addr)); | |
727 | if (kvm_is_error_hva(useraddr)) | |
69d0d3a3 CB |
728 | return kvm_s390_inject_program_int(vcpu, PGM_ADDRESSING); |
729 | ||
730 | if (vcpu->run->s.regs.gprs[reg1] & PFMF_CF) { | |
731 | if (clear_user((void __user *)useraddr, PAGE_SIZE)) | |
732 | return kvm_s390_inject_program_int(vcpu, PGM_ADDRESSING); | |
733 | } | |
734 | ||
735 | if (vcpu->run->s.regs.gprs[reg1] & PFMF_SK) { | |
3ac8e380 DD |
736 | int rc = __skey_check_enable(vcpu); |
737 | ||
738 | if (rc) | |
739 | return rc; | |
69d0d3a3 CB |
740 | if (set_guest_storage_key(current->mm, useraddr, |
741 | vcpu->run->s.regs.gprs[reg1] & PFMF_KEY, | |
742 | vcpu->run->s.regs.gprs[reg1] & PFMF_NQ)) | |
743 | return kvm_s390_inject_program_int(vcpu, PGM_ADDRESSING); | |
744 | } | |
745 | ||
746 | start += PAGE_SIZE; | |
747 | } | |
748 | if (vcpu->run->s.regs.gprs[reg1] & PFMF_FSC) | |
749 | vcpu->run->s.regs.gprs[reg2] = end; | |
750 | return 0; | |
751 | } | |
752 | ||
b31288fa KW |
753 | static int handle_essa(struct kvm_vcpu *vcpu) |
754 | { | |
755 | /* entries expected to be 1FF */ | |
756 | int entries = (vcpu->arch.sie_block->cbrlo & ~PAGE_MASK) >> 3; | |
757 | unsigned long *cbrlo, cbrle; | |
758 | struct gmap *gmap; | |
759 | int i; | |
760 | ||
7cbde76b | 761 | VCPU_EVENT(vcpu, 4, "ESSA: release %d pages", entries); |
b31288fa KW |
762 | gmap = vcpu->arch.gmap; |
763 | vcpu->stat.instruction_essa++; | |
e6db1d61 | 764 | if (!vcpu->kvm->arch.use_cmma) |
b31288fa KW |
765 | return kvm_s390_inject_program_int(vcpu, PGM_OPERATION); |
766 | ||
767 | if (vcpu->arch.sie_block->gpsw.mask & PSW_MASK_PSTATE) | |
768 | return kvm_s390_inject_program_int(vcpu, PGM_PRIVILEGED_OP); | |
769 | ||
770 | if (((vcpu->arch.sie_block->ipb & 0xf0000000) >> 28) > 6) | |
771 | return kvm_s390_inject_program_int(vcpu, PGM_SPECIFICATION); | |
772 | ||
773 | /* Rewind PSW to repeat the ESSA instruction */ | |
04b41acd | 774 | kvm_s390_rewind_psw(vcpu, 4); |
b31288fa KW |
775 | vcpu->arch.sie_block->cbrlo &= PAGE_MASK; /* reset nceo */ |
776 | cbrlo = phys_to_virt(vcpu->arch.sie_block->cbrlo); | |
777 | down_read(&gmap->mm->mmap_sem); | |
778 | for (i = 0; i < entries; ++i) { | |
779 | cbrle = cbrlo[i]; | |
780 | if (unlikely(cbrle & ~PAGE_MASK || cbrle < 2 * PAGE_SIZE)) | |
781 | /* invalid entry */ | |
782 | break; | |
783 | /* try to free backing */ | |
6e0a0431 | 784 | __gmap_zap(gmap, cbrle); |
b31288fa KW |
785 | } |
786 | up_read(&gmap->mm->mmap_sem); | |
787 | if (i < entries) | |
788 | return kvm_s390_inject_program_int(vcpu, PGM_SPECIFICATION); | |
789 | return 0; | |
790 | } | |
791 | ||
48a3e950 | 792 | static const intercept_handler_t b9_handlers[256] = { |
8a242234 | 793 | [0x8a] = handle_ipte_interlock, |
48a3e950 | 794 | [0x8d] = handle_epsw, |
8a242234 HC |
795 | [0x8e] = handle_ipte_interlock, |
796 | [0x8f] = handle_ipte_interlock, | |
b31288fa | 797 | [0xab] = handle_essa, |
69d0d3a3 | 798 | [0xaf] = handle_pfmf, |
48a3e950 CH |
799 | }; |
800 | ||
801 | int kvm_s390_handle_b9(struct kvm_vcpu *vcpu) | |
802 | { | |
803 | intercept_handler_t handler; | |
804 | ||
805 | /* This is handled just as for the B2 instructions. */ | |
806 | handler = b9_handlers[vcpu->arch.sie_block->ipa & 0x00ff]; | |
5087dfa6 TH |
807 | if (handler) |
808 | return handler(vcpu); | |
809 | ||
48a3e950 CH |
810 | return -EOPNOTSUPP; |
811 | } | |
812 | ||
953ed88d TH |
813 | int kvm_s390_handle_lctl(struct kvm_vcpu *vcpu) |
814 | { | |
815 | int reg1 = (vcpu->arch.sie_block->ipa & 0x00f0) >> 4; | |
816 | int reg3 = vcpu->arch.sie_block->ipa & 0x000f; | |
fc56eb66 HC |
817 | int reg, rc, nr_regs; |
818 | u32 ctl_array[16]; | |
f987a3ee | 819 | u64 ga; |
8ae04b8f | 820 | ar_t ar; |
953ed88d TH |
821 | |
822 | vcpu->stat.instruction_lctl++; | |
823 | ||
824 | if (vcpu->arch.sie_block->gpsw.mask & PSW_MASK_PSTATE) | |
825 | return kvm_s390_inject_program_int(vcpu, PGM_PRIVILEGED_OP); | |
826 | ||
8ae04b8f | 827 | ga = kvm_s390_get_base_disp_rs(vcpu, &ar); |
953ed88d | 828 | |
f987a3ee | 829 | if (ga & 3) |
953ed88d TH |
830 | return kvm_s390_inject_program_int(vcpu, PGM_SPECIFICATION); |
831 | ||
7cbde76b | 832 | VCPU_EVENT(vcpu, 4, "LCTL: r1:%d, r3:%d, addr: 0x%llx", reg1, reg3, ga); |
f987a3ee | 833 | trace_kvm_s390_handle_lctl(vcpu, 0, reg1, reg3, ga); |
953ed88d | 834 | |
fc56eb66 | 835 | nr_regs = ((reg3 - reg1) & 0xf) + 1; |
8ae04b8f | 836 | rc = read_guest(vcpu, ga, ar, ctl_array, nr_regs * sizeof(u32)); |
fc56eb66 HC |
837 | if (rc) |
838 | return kvm_s390_inject_prog_cond(vcpu, rc); | |
953ed88d | 839 | reg = reg1; |
fc56eb66 | 840 | nr_regs = 0; |
953ed88d | 841 | do { |
953ed88d | 842 | vcpu->arch.sie_block->gcr[reg] &= 0xffffffff00000000ul; |
fc56eb66 | 843 | vcpu->arch.sie_block->gcr[reg] |= ctl_array[nr_regs++]; |
953ed88d TH |
844 | if (reg == reg3) |
845 | break; | |
846 | reg = (reg + 1) % 16; | |
847 | } while (1); | |
2dca485f | 848 | kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu); |
953ed88d TH |
849 | return 0; |
850 | } | |
851 | ||
aba07508 DH |
852 | int kvm_s390_handle_stctl(struct kvm_vcpu *vcpu) |
853 | { | |
854 | int reg1 = (vcpu->arch.sie_block->ipa & 0x00f0) >> 4; | |
855 | int reg3 = vcpu->arch.sie_block->ipa & 0x000f; | |
fc56eb66 HC |
856 | int reg, rc, nr_regs; |
857 | u32 ctl_array[16]; | |
aba07508 | 858 | u64 ga; |
8ae04b8f | 859 | ar_t ar; |
aba07508 DH |
860 | |
861 | vcpu->stat.instruction_stctl++; | |
862 | ||
863 | if (vcpu->arch.sie_block->gpsw.mask & PSW_MASK_PSTATE) | |
864 | return kvm_s390_inject_program_int(vcpu, PGM_PRIVILEGED_OP); | |
865 | ||
8ae04b8f | 866 | ga = kvm_s390_get_base_disp_rs(vcpu, &ar); |
aba07508 DH |
867 | |
868 | if (ga & 3) | |
869 | return kvm_s390_inject_program_int(vcpu, PGM_SPECIFICATION); | |
870 | ||
7cbde76b | 871 | VCPU_EVENT(vcpu, 4, "STCTL r1:%d, r3:%d, addr: 0x%llx", reg1, reg3, ga); |
aba07508 DH |
872 | trace_kvm_s390_handle_stctl(vcpu, 0, reg1, reg3, ga); |
873 | ||
874 | reg = reg1; | |
fc56eb66 | 875 | nr_regs = 0; |
aba07508 | 876 | do { |
fc56eb66 | 877 | ctl_array[nr_regs++] = vcpu->arch.sie_block->gcr[reg]; |
aba07508 DH |
878 | if (reg == reg3) |
879 | break; | |
880 | reg = (reg + 1) % 16; | |
881 | } while (1); | |
8ae04b8f | 882 | rc = write_guest(vcpu, ga, ar, ctl_array, nr_regs * sizeof(u32)); |
fc56eb66 | 883 | return rc ? kvm_s390_inject_prog_cond(vcpu, rc) : 0; |
aba07508 DH |
884 | } |
885 | ||
953ed88d TH |
886 | static int handle_lctlg(struct kvm_vcpu *vcpu) |
887 | { | |
888 | int reg1 = (vcpu->arch.sie_block->ipa & 0x00f0) >> 4; | |
889 | int reg3 = vcpu->arch.sie_block->ipa & 0x000f; | |
fc56eb66 HC |
890 | int reg, rc, nr_regs; |
891 | u64 ctl_array[16]; | |
892 | u64 ga; | |
8ae04b8f | 893 | ar_t ar; |
953ed88d TH |
894 | |
895 | vcpu->stat.instruction_lctlg++; | |
896 | ||
897 | if (vcpu->arch.sie_block->gpsw.mask & PSW_MASK_PSTATE) | |
898 | return kvm_s390_inject_program_int(vcpu, PGM_PRIVILEGED_OP); | |
899 | ||
8ae04b8f | 900 | ga = kvm_s390_get_base_disp_rsy(vcpu, &ar); |
953ed88d | 901 | |
f987a3ee | 902 | if (ga & 7) |
953ed88d TH |
903 | return kvm_s390_inject_program_int(vcpu, PGM_SPECIFICATION); |
904 | ||
7cbde76b | 905 | VCPU_EVENT(vcpu, 4, "LCTLG: r1:%d, r3:%d, addr: 0x%llx", reg1, reg3, ga); |
f987a3ee | 906 | trace_kvm_s390_handle_lctl(vcpu, 1, reg1, reg3, ga); |
953ed88d | 907 | |
fc56eb66 | 908 | nr_regs = ((reg3 - reg1) & 0xf) + 1; |
8ae04b8f | 909 | rc = read_guest(vcpu, ga, ar, ctl_array, nr_regs * sizeof(u64)); |
fc56eb66 HC |
910 | if (rc) |
911 | return kvm_s390_inject_prog_cond(vcpu, rc); | |
912 | reg = reg1; | |
913 | nr_regs = 0; | |
953ed88d | 914 | do { |
fc56eb66 | 915 | vcpu->arch.sie_block->gcr[reg] = ctl_array[nr_regs++]; |
953ed88d TH |
916 | if (reg == reg3) |
917 | break; | |
918 | reg = (reg + 1) % 16; | |
919 | } while (1); | |
2dca485f | 920 | kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu); |
953ed88d TH |
921 | return 0; |
922 | } | |
923 | ||
aba07508 DH |
924 | static int handle_stctg(struct kvm_vcpu *vcpu) |
925 | { | |
926 | int reg1 = (vcpu->arch.sie_block->ipa & 0x00f0) >> 4; | |
927 | int reg3 = vcpu->arch.sie_block->ipa & 0x000f; | |
fc56eb66 HC |
928 | int reg, rc, nr_regs; |
929 | u64 ctl_array[16]; | |
930 | u64 ga; | |
8ae04b8f | 931 | ar_t ar; |
aba07508 DH |
932 | |
933 | vcpu->stat.instruction_stctg++; | |
934 | ||
935 | if (vcpu->arch.sie_block->gpsw.mask & PSW_MASK_PSTATE) | |
936 | return kvm_s390_inject_program_int(vcpu, PGM_PRIVILEGED_OP); | |
937 | ||
8ae04b8f | 938 | ga = kvm_s390_get_base_disp_rsy(vcpu, &ar); |
aba07508 DH |
939 | |
940 | if (ga & 7) | |
941 | return kvm_s390_inject_program_int(vcpu, PGM_SPECIFICATION); | |
942 | ||
7cbde76b | 943 | VCPU_EVENT(vcpu, 4, "STCTG r1:%d, r3:%d, addr: 0x%llx", reg1, reg3, ga); |
aba07508 DH |
944 | trace_kvm_s390_handle_stctl(vcpu, 1, reg1, reg3, ga); |
945 | ||
fc56eb66 HC |
946 | reg = reg1; |
947 | nr_regs = 0; | |
aba07508 | 948 | do { |
fc56eb66 | 949 | ctl_array[nr_regs++] = vcpu->arch.sie_block->gcr[reg]; |
aba07508 DH |
950 | if (reg == reg3) |
951 | break; | |
952 | reg = (reg + 1) % 16; | |
953 | } while (1); | |
8ae04b8f | 954 | rc = write_guest(vcpu, ga, ar, ctl_array, nr_regs * sizeof(u64)); |
fc56eb66 | 955 | return rc ? kvm_s390_inject_prog_cond(vcpu, rc) : 0; |
aba07508 DH |
956 | } |
957 | ||
f379aae5 | 958 | static const intercept_handler_t eb_handlers[256] = { |
953ed88d | 959 | [0x2f] = handle_lctlg, |
aba07508 | 960 | [0x25] = handle_stctg, |
f379aae5 CH |
961 | }; |
962 | ||
953ed88d | 963 | int kvm_s390_handle_eb(struct kvm_vcpu *vcpu) |
f379aae5 CH |
964 | { |
965 | intercept_handler_t handler; | |
966 | ||
f379aae5 CH |
967 | handler = eb_handlers[vcpu->arch.sie_block->ipb & 0xff]; |
968 | if (handler) | |
969 | return handler(vcpu); | |
970 | return -EOPNOTSUPP; | |
971 | } | |
972 | ||
bb25b9ba CB |
973 | static int handle_tprot(struct kvm_vcpu *vcpu) |
974 | { | |
b1c571a5 | 975 | u64 address1, address2; |
a0465f9a TH |
976 | unsigned long hva, gpa; |
977 | int ret = 0, cc = 0; | |
978 | bool writable; | |
8ae04b8f | 979 | ar_t ar; |
bb25b9ba CB |
980 | |
981 | vcpu->stat.instruction_tprot++; | |
982 | ||
f9f6bbc6 TH |
983 | if (vcpu->arch.sie_block->gpsw.mask & PSW_MASK_PSTATE) |
984 | return kvm_s390_inject_program_int(vcpu, PGM_PRIVILEGED_OP); | |
985 | ||
8ae04b8f | 986 | kvm_s390_get_base_disp_sse(vcpu, &address1, &address2, &ar, NULL); |
b1c571a5 | 987 | |
bb25b9ba CB |
988 | /* we only handle the Linux memory detection case: |
989 | * access key == 0 | |
bb25b9ba CB |
990 | * everything else goes to userspace. */ |
991 | if (address2 & 0xf0) | |
992 | return -EOPNOTSUPP; | |
993 | if (vcpu->arch.sie_block->gpsw.mask & PSW_MASK_DAT) | |
a0465f9a | 994 | ipte_lock(vcpu); |
8ae04b8f | 995 | ret = guest_translate_address(vcpu, address1, ar, &gpa, 1); |
a0465f9a TH |
996 | if (ret == PGM_PROTECTION) { |
997 | /* Write protected? Try again with read-only... */ | |
998 | cc = 1; | |
8ae04b8f | 999 | ret = guest_translate_address(vcpu, address1, ar, &gpa, 0); |
a0465f9a TH |
1000 | } |
1001 | if (ret) { | |
1002 | if (ret == PGM_ADDRESSING || ret == PGM_TRANSLATION_SPEC) { | |
1003 | ret = kvm_s390_inject_program_int(vcpu, ret); | |
1004 | } else if (ret > 0) { | |
1005 | /* Translation not available */ | |
1006 | kvm_s390_set_psw_cc(vcpu, 3); | |
1007 | ret = 0; | |
1008 | } | |
1009 | goto out_unlock; | |
1010 | } | |
59a1fa2d | 1011 | |
a0465f9a TH |
1012 | hva = gfn_to_hva_prot(vcpu->kvm, gpa_to_gfn(gpa), &writable); |
1013 | if (kvm_is_error_hva(hva)) { | |
1014 | ret = kvm_s390_inject_program_int(vcpu, PGM_ADDRESSING); | |
1015 | } else { | |
1016 | if (!writable) | |
1017 | cc = 1; /* Write not permitted ==> read-only */ | |
1018 | kvm_s390_set_psw_cc(vcpu, cc); | |
1019 | /* Note: CC2 only occurs for storage keys (not supported yet) */ | |
1020 | } | |
1021 | out_unlock: | |
1022 | if (vcpu->arch.sie_block->gpsw.mask & PSW_MASK_DAT) | |
1023 | ipte_unlock(vcpu); | |
1024 | return ret; | |
bb25b9ba CB |
1025 | } |
1026 | ||
1027 | int kvm_s390_handle_e5(struct kvm_vcpu *vcpu) | |
1028 | { | |
1029 | /* For e5xx... instructions we only handle TPROT */ | |
1030 | if ((vcpu->arch.sie_block->ipa & 0x00ff) == 0x01) | |
1031 | return handle_tprot(vcpu); | |
1032 | return -EOPNOTSUPP; | |
1033 | } | |
1034 | ||
8c3f61e2 CH |
1035 | static int handle_sckpf(struct kvm_vcpu *vcpu) |
1036 | { | |
1037 | u32 value; | |
1038 | ||
1039 | if (vcpu->arch.sie_block->gpsw.mask & PSW_MASK_PSTATE) | |
208dd756 | 1040 | return kvm_s390_inject_program_int(vcpu, PGM_PRIVILEGED_OP); |
8c3f61e2 CH |
1041 | |
1042 | if (vcpu->run->s.regs.gprs[0] & 0x00000000ffff0000) | |
1043 | return kvm_s390_inject_program_int(vcpu, | |
1044 | PGM_SPECIFICATION); | |
1045 | ||
1046 | value = vcpu->run->s.regs.gprs[0] & 0x000000000000ffff; | |
1047 | vcpu->arch.sie_block->todpr = value; | |
1048 | ||
1049 | return 0; | |
1050 | } | |
1051 | ||
77975357 | 1052 | static const intercept_handler_t x01_handlers[256] = { |
8c3f61e2 CH |
1053 | [0x07] = handle_sckpf, |
1054 | }; | |
1055 | ||
1056 | int kvm_s390_handle_01(struct kvm_vcpu *vcpu) | |
1057 | { | |
1058 | intercept_handler_t handler; | |
1059 | ||
1060 | handler = x01_handlers[vcpu->arch.sie_block->ipa & 0x00ff]; | |
1061 | if (handler) | |
1062 | return handler(vcpu); | |
1063 | return -EOPNOTSUPP; | |
1064 | } |