Commit | Line | Data |
---|---|---|
dbd70fb4 | 1 | /* |
dbd70fb4 HC |
2 | * Copyright IBM Corp. 2007 |
3 | * Author(s): Heiko Carstens <heiko.carstens@de.ibm.com> | |
4 | */ | |
5 | ||
395d31d4 MS |
6 | #define KMSG_COMPONENT "cpu" |
7 | #define pr_fmt(fmt) KMSG_COMPONENT ": " fmt | |
8 | ||
dbd70fb4 HC |
9 | #include <linux/kernel.h> |
10 | #include <linux/mm.h> | |
11 | #include <linux/init.h> | |
12 | #include <linux/device.h> | |
13 | #include <linux/bootmem.h> | |
14 | #include <linux/sched.h> | |
15 | #include <linux/workqueue.h> | |
16 | #include <linux/cpu.h> | |
17 | #include <linux/smp.h> | |
f414f5f1 | 18 | #include <linux/cpuset.h> |
dbd70fb4 HC |
19 | #include <asm/delay.h> |
20 | #include <asm/s390_ext.h> | |
dbd70fb4 | 21 | |
c10fde0d HC |
22 | #define PTF_HORIZONTAL (0UL) |
23 | #define PTF_VERTICAL (1UL) | |
24 | #define PTF_CHECK (2UL) | |
dbd70fb4 | 25 | |
4cb14bc8 HC |
26 | struct mask_info { |
27 | struct mask_info *next; | |
10d38589 | 28 | unsigned char id; |
dbd70fb4 HC |
29 | cpumask_t mask; |
30 | }; | |
31 | ||
c9af3fa9 | 32 | static int topology_enabled = 1; |
dbd70fb4 | 33 | static void topology_work_fn(struct work_struct *work); |
c30f91b6 | 34 | static struct sysinfo_15_1_x *tl_info; |
dbd70fb4 HC |
35 | static struct timer_list topology_timer; |
36 | static void set_topology_timer(void); | |
37 | static DECLARE_WORK(topology_work, topology_work_fn); | |
74af2831 HC |
38 | /* topology_lock protects the core linked list */ |
39 | static DEFINE_SPINLOCK(topology_lock); | |
dbd70fb4 | 40 | |
4cb14bc8 | 41 | static struct mask_info core_info; |
d00aa4e7 | 42 | cpumask_t cpu_core_map[NR_CPUS]; |
10d38589 | 43 | unsigned char cpu_core_id[NR_CPUS]; |
d00aa4e7 | 44 | |
4cb14bc8 HC |
45 | #ifdef CONFIG_SCHED_BOOK |
46 | static struct mask_info book_info; | |
47 | cpumask_t cpu_book_map[NR_CPUS]; | |
48 | unsigned char cpu_book_id[NR_CPUS]; | |
49 | #endif | |
50 | ||
51 | static cpumask_t cpu_group_map(struct mask_info *info, unsigned int cpu) | |
dbd70fb4 | 52 | { |
dbd70fb4 HC |
53 | cpumask_t mask; |
54 | ||
55 | cpus_clear(mask); | |
9186d7a9 | 56 | if (!topology_enabled || !MACHINE_HAS_TOPOLOGY) |
5439050f | 57 | return cpu_possible_map; |
4cb14bc8 HC |
58 | while (info) { |
59 | if (cpu_isset(cpu, info->mask)) { | |
60 | mask = info->mask; | |
dbd70fb4 HC |
61 | break; |
62 | } | |
4cb14bc8 | 63 | info = info->next; |
dbd70fb4 | 64 | } |
dbd70fb4 HC |
65 | if (cpus_empty(mask)) |
66 | mask = cpumask_of_cpu(cpu); | |
67 | return mask; | |
68 | } | |
69 | ||
c30f91b6 HC |
70 | static void add_cpus_to_mask(struct topology_cpu *tl_cpu, |
71 | struct mask_info *book, struct mask_info *core) | |
dbd70fb4 HC |
72 | { |
73 | unsigned int cpu; | |
74 | ||
c30f91b6 HC |
75 | for (cpu = find_first_bit(&tl_cpu->mask[0], TOPOLOGY_CPU_BITS); |
76 | cpu < TOPOLOGY_CPU_BITS; | |
77 | cpu = find_next_bit(&tl_cpu->mask[0], TOPOLOGY_CPU_BITS, cpu + 1)) | |
dbd70fb4 HC |
78 | { |
79 | unsigned int rcpu, lcpu; | |
80 | ||
c30f91b6 | 81 | rcpu = TOPOLOGY_CPU_BITS - 1 - cpu + tl_cpu->origin; |
dbd70fb4 | 82 | for_each_present_cpu(lcpu) { |
4cb14bc8 HC |
83 | if (cpu_logical_map(lcpu) != rcpu) |
84 | continue; | |
85 | #ifdef CONFIG_SCHED_BOOK | |
86 | cpu_set(lcpu, book->mask); | |
87 | cpu_book_id[lcpu] = book->id; | |
88 | #endif | |
89 | cpu_set(lcpu, core->mask); | |
90 | cpu_core_id[lcpu] = core->id; | |
91 | smp_cpu_polarization[lcpu] = tl_cpu->pp; | |
dbd70fb4 HC |
92 | } |
93 | } | |
94 | } | |
95 | ||
4cb14bc8 | 96 | static void clear_masks(void) |
dbd70fb4 | 97 | { |
4cb14bc8 | 98 | struct mask_info *info; |
dbd70fb4 | 99 | |
4cb14bc8 HC |
100 | info = &core_info; |
101 | while (info) { | |
102 | cpus_clear(info->mask); | |
103 | info = info->next; | |
104 | } | |
105 | #ifdef CONFIG_SCHED_BOOK | |
106 | info = &book_info; | |
107 | while (info) { | |
108 | cpus_clear(info->mask); | |
109 | info = info->next; | |
dbd70fb4 | 110 | } |
4cb14bc8 | 111 | #endif |
dbd70fb4 HC |
112 | } |
113 | ||
c30f91b6 | 114 | static union topology_entry *next_tle(union topology_entry *tle) |
dbd70fb4 | 115 | { |
c30f91b6 HC |
116 | if (!tle->nl) |
117 | return (union topology_entry *)((struct topology_cpu *)tle + 1); | |
118 | return (union topology_entry *)((struct topology_container *)tle + 1); | |
dbd70fb4 HC |
119 | } |
120 | ||
c30f91b6 | 121 | static void tl_to_cores(struct sysinfo_15_1_x *info) |
dbd70fb4 | 122 | { |
4cb14bc8 HC |
123 | #ifdef CONFIG_SCHED_BOOK |
124 | struct mask_info *book = &book_info; | |
125 | #else | |
126 | struct mask_info *book = NULL; | |
127 | #endif | |
128 | struct mask_info *core = &core_info; | |
c30f91b6 | 129 | union topology_entry *tle, *end; |
4cb14bc8 | 130 | |
dbd70fb4 | 131 | |
74af2831 | 132 | spin_lock_irq(&topology_lock); |
4cb14bc8 | 133 | clear_masks(); |
c10fde0d | 134 | tle = info->tle; |
c30f91b6 | 135 | end = (union topology_entry *)((unsigned long)info + info->length); |
dbd70fb4 HC |
136 | while (tle < end) { |
137 | switch (tle->nl) { | |
4cb14bc8 | 138 | #ifdef CONFIG_SCHED_BOOK |
dbd70fb4 | 139 | case 2: |
4cb14bc8 HC |
140 | book = book->next; |
141 | book->id = tle->container.id; | |
dbd70fb4 | 142 | break; |
4cb14bc8 | 143 | #endif |
dbd70fb4 HC |
144 | case 1: |
145 | core = core->next; | |
10d38589 | 146 | core->id = tle->container.id; |
dbd70fb4 HC |
147 | break; |
148 | case 0: | |
4cb14bc8 | 149 | add_cpus_to_mask(&tle->cpu, book, core); |
dbd70fb4 HC |
150 | break; |
151 | default: | |
4cb14bc8 | 152 | clear_masks(); |
d7015c12 | 153 | goto out; |
dbd70fb4 HC |
154 | } |
155 | tle = next_tle(tle); | |
156 | } | |
d7015c12 | 157 | out: |
74af2831 | 158 | spin_unlock_irq(&topology_lock); |
dbd70fb4 HC |
159 | } |
160 | ||
c10fde0d HC |
161 | static void topology_update_polarization_simple(void) |
162 | { | |
163 | int cpu; | |
164 | ||
165 | mutex_lock(&smp_cpu_state_mutex); | |
5439050f | 166 | for_each_possible_cpu(cpu) |
c10fde0d HC |
167 | smp_cpu_polarization[cpu] = POLARIZATION_HRZ; |
168 | mutex_unlock(&smp_cpu_state_mutex); | |
169 | } | |
170 | ||
171 | static int ptf(unsigned long fc) | |
dbd70fb4 HC |
172 | { |
173 | int rc; | |
174 | ||
175 | asm volatile( | |
176 | " .insn rre,0xb9a20000,%1,%1\n" | |
177 | " ipm %0\n" | |
178 | " srl %0,28\n" | |
179 | : "=d" (rc) | |
c10fde0d HC |
180 | : "d" (fc) : "cc"); |
181 | return rc; | |
182 | } | |
183 | ||
184 | int topology_set_cpu_management(int fc) | |
185 | { | |
186 | int cpu; | |
187 | int rc; | |
188 | ||
9186d7a9 | 189 | if (!MACHINE_HAS_TOPOLOGY) |
c10fde0d HC |
190 | return -EOPNOTSUPP; |
191 | if (fc) | |
192 | rc = ptf(PTF_VERTICAL); | |
193 | else | |
194 | rc = ptf(PTF_HORIZONTAL); | |
195 | if (rc) | |
196 | return -EBUSY; | |
5439050f | 197 | for_each_possible_cpu(cpu) |
c10fde0d | 198 | smp_cpu_polarization[cpu] = POLARIZATION_UNKNWN; |
dbd70fb4 HC |
199 | return rc; |
200 | } | |
201 | ||
d00aa4e7 HC |
202 | static void update_cpu_core_map(void) |
203 | { | |
4cb14bc8 | 204 | unsigned long flags; |
d00aa4e7 HC |
205 | int cpu; |
206 | ||
4cb14bc8 HC |
207 | spin_lock_irqsave(&topology_lock, flags); |
208 | for_each_possible_cpu(cpu) { | |
209 | cpu_core_map[cpu] = cpu_group_map(&core_info, cpu); | |
210 | #ifdef CONFIG_SCHED_BOOK | |
211 | cpu_book_map[cpu] = cpu_group_map(&book_info, cpu); | |
212 | #endif | |
213 | } | |
214 | spin_unlock_irqrestore(&topology_lock, flags); | |
215 | } | |
216 | ||
96f4a70d | 217 | void store_topology(struct sysinfo_15_1_x *info) |
4cb14bc8 HC |
218 | { |
219 | #ifdef CONFIG_SCHED_BOOK | |
220 | int rc; | |
221 | ||
222 | rc = stsi(info, 15, 1, 3); | |
223 | if (rc != -ENOSYS) | |
224 | return; | |
225 | #endif | |
226 | stsi(info, 15, 1, 2); | |
d00aa4e7 HC |
227 | } |
228 | ||
ee79d1bd | 229 | int arch_update_cpu_topology(void) |
dbd70fb4 | 230 | { |
c30f91b6 | 231 | struct sysinfo_15_1_x *info = tl_info; |
dbd70fb4 HC |
232 | struct sys_device *sysdev; |
233 | int cpu; | |
234 | ||
9186d7a9 | 235 | if (!MACHINE_HAS_TOPOLOGY) { |
d00aa4e7 | 236 | update_cpu_core_map(); |
c10fde0d | 237 | topology_update_polarization_simple(); |
ee79d1bd | 238 | return 0; |
c10fde0d | 239 | } |
4cb14bc8 | 240 | store_topology(info); |
dbd70fb4 | 241 | tl_to_cores(info); |
d00aa4e7 | 242 | update_cpu_core_map(); |
dbd70fb4 HC |
243 | for_each_online_cpu(cpu) { |
244 | sysdev = get_cpu_sysdev(cpu); | |
245 | kobject_uevent(&sysdev->kobj, KOBJ_CHANGE); | |
246 | } | |
ee79d1bd | 247 | return 1; |
dbd70fb4 HC |
248 | } |
249 | ||
fd781fa2 HC |
250 | static void topology_work_fn(struct work_struct *work) |
251 | { | |
f414f5f1 | 252 | rebuild_sched_domains(); |
dbd70fb4 HC |
253 | } |
254 | ||
c10fde0d HC |
255 | void topology_schedule_update(void) |
256 | { | |
257 | schedule_work(&topology_work); | |
258 | } | |
259 | ||
dbd70fb4 HC |
260 | static void topology_timer_fn(unsigned long ignored) |
261 | { | |
c10fde0d HC |
262 | if (ptf(PTF_CHECK)) |
263 | topology_schedule_update(); | |
dbd70fb4 HC |
264 | set_topology_timer(); |
265 | } | |
266 | ||
267 | static void set_topology_timer(void) | |
268 | { | |
269 | topology_timer.function = topology_timer_fn; | |
270 | topology_timer.data = 0; | |
271 | topology_timer.expires = jiffies + 60 * HZ; | |
272 | add_timer(&topology_timer); | |
273 | } | |
274 | ||
2b1a61f0 | 275 | static int __init early_parse_topology(char *p) |
dbd70fb4 | 276 | { |
c9af3fa9 | 277 | if (strncmp(p, "off", 3)) |
2b1a61f0 | 278 | return 0; |
c9af3fa9 | 279 | topology_enabled = 0; |
2b1a61f0 | 280 | return 0; |
dbd70fb4 | 281 | } |
2b1a61f0 | 282 | early_param("topology", early_parse_topology); |
dbd70fb4 HC |
283 | |
284 | static int __init init_topology_update(void) | |
285 | { | |
286 | int rc; | |
287 | ||
d00aa4e7 | 288 | rc = 0; |
9186d7a9 | 289 | if (!MACHINE_HAS_TOPOLOGY) { |
c10fde0d | 290 | topology_update_polarization_simple(); |
d00aa4e7 | 291 | goto out; |
c10fde0d HC |
292 | } |
293 | init_timer_deferrable(&topology_timer); | |
349f1b67 | 294 | set_topology_timer(); |
d00aa4e7 HC |
295 | out: |
296 | update_cpu_core_map(); | |
297 | return rc; | |
dbd70fb4 HC |
298 | } |
299 | __initcall(init_topology_update); | |
300 | ||
c30f91b6 HC |
301 | static void alloc_masks(struct sysinfo_15_1_x *info, struct mask_info *mask, |
302 | int offset) | |
4cb14bc8 HC |
303 | { |
304 | int i, nr_masks; | |
305 | ||
c30f91b6 | 306 | nr_masks = info->mag[TOPOLOGY_NR_MAG - offset]; |
4cb14bc8 | 307 | for (i = 0; i < info->mnest - offset; i++) |
c30f91b6 | 308 | nr_masks *= info->mag[TOPOLOGY_NR_MAG - offset - 1 - i]; |
4cb14bc8 HC |
309 | nr_masks = max(nr_masks, 1); |
310 | for (i = 0; i < nr_masks; i++) { | |
311 | mask->next = alloc_bootmem(sizeof(struct mask_info)); | |
312 | mask = mask->next; | |
313 | } | |
314 | } | |
315 | ||
dbd70fb4 HC |
316 | void __init s390_init_cpu_topology(void) |
317 | { | |
c30f91b6 | 318 | struct sysinfo_15_1_x *info; |
dbd70fb4 HC |
319 | int i; |
320 | ||
9186d7a9 | 321 | if (!MACHINE_HAS_TOPOLOGY) |
dbd70fb4 | 322 | return; |
dbd70fb4 | 323 | tl_info = alloc_bootmem_pages(PAGE_SIZE); |
dbd70fb4 | 324 | info = tl_info; |
4cb14bc8 | 325 | store_topology(info); |
395d31d4 | 326 | pr_info("The CPU configuration topology of the machine is:"); |
c30f91b6 | 327 | for (i = 0; i < TOPOLOGY_NR_MAG; i++) |
dbd70fb4 HC |
328 | printk(" %d", info->mag[i]); |
329 | printk(" / %d\n", info->mnest); | |
4cb14bc8 HC |
330 | alloc_masks(info, &core_info, 2); |
331 | #ifdef CONFIG_SCHED_BOOK | |
332 | alloc_masks(info, &book_info, 3); | |
333 | #endif | |
dbd70fb4 | 334 | } |