Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * arch/s390/kernel/time.c | |
3 | * Time of day based timer functions. | |
4 | * | |
5 | * S390 version | |
d2fec595 | 6 | * Copyright IBM Corp. 1999, 2008 |
1da177e4 LT |
7 | * Author(s): Hartmut Penner (hp@de.ibm.com), |
8 | * Martin Schwidefsky (schwidefsky@de.ibm.com), | |
9 | * Denis Joseph Barrow (djbarrow@de.ibm.com,barrow_dj@yahoo.com) | |
10 | * | |
11 | * Derived from "arch/i386/kernel/time.c" | |
12 | * Copyright (C) 1991, 1992, 1995 Linus Torvalds | |
13 | */ | |
14 | ||
feab6501 MS |
15 | #define KMSG_COMPONENT "time" |
16 | #define pr_fmt(fmt) KMSG_COMPONENT ": " fmt | |
17 | ||
1da177e4 LT |
18 | #include <linux/errno.h> |
19 | #include <linux/module.h> | |
20 | #include <linux/sched.h> | |
21 | #include <linux/kernel.h> | |
22 | #include <linux/param.h> | |
23 | #include <linux/string.h> | |
24 | #include <linux/mm.h> | |
25 | #include <linux/interrupt.h> | |
750887de HC |
26 | #include <linux/cpu.h> |
27 | #include <linux/stop_machine.h> | |
1da177e4 | 28 | #include <linux/time.h> |
3367b994 | 29 | #include <linux/sysdev.h> |
1da177e4 LT |
30 | #include <linux/delay.h> |
31 | #include <linux/init.h> | |
32 | #include <linux/smp.h> | |
33 | #include <linux/types.h> | |
34 | #include <linux/profile.h> | |
35 | #include <linux/timex.h> | |
36 | #include <linux/notifier.h> | |
dc64bef5 | 37 | #include <linux/clocksource.h> |
5a62b192 | 38 | #include <linux/clockchips.h> |
1da177e4 LT |
39 | #include <asm/uaccess.h> |
40 | #include <asm/delay.h> | |
41 | #include <asm/s390_ext.h> | |
42 | #include <asm/div64.h> | |
b020632e | 43 | #include <asm/vdso.h> |
1da177e4 | 44 | #include <asm/irq.h> |
5a489b98 | 45 | #include <asm/irq_regs.h> |
1da177e4 | 46 | #include <asm/timer.h> |
d54853ef | 47 | #include <asm/etr.h> |
a806170e | 48 | #include <asm/cio.h> |
1da177e4 LT |
49 | |
50 | /* change this if you have some constant time drift */ | |
51 | #define USECS_PER_JIFFY ((unsigned long) 1000000/HZ) | |
52 | #define CLK_TICKS_PER_JIFFY ((unsigned long) USECS_PER_JIFFY << 12) | |
53 | ||
54 | /* | |
55 | * Create a small time difference between the timer interrupts | |
56 | * on the different cpus to avoid lock contention. | |
57 | */ | |
58 | #define CPU_DEVIATION (smp_processor_id() << 12) | |
59 | ||
60 | #define TICK_SIZE tick | |
61 | ||
b6112ccb | 62 | u64 sched_clock_base_cc = -1; /* Force to data section. */ |
05e7ff7d | 63 | EXPORT_SYMBOL_GPL(sched_clock_base_cc); |
b6112ccb | 64 | |
5a62b192 | 65 | static DEFINE_PER_CPU(struct clock_event_device, comparators); |
1da177e4 | 66 | |
1da177e4 LT |
67 | /* |
68 | * Scheduler clock - returns current time in nanosec units. | |
69 | */ | |
88dbd203 | 70 | unsigned long long notrace sched_clock(void) |
1da177e4 | 71 | { |
05e7ff7d | 72 | return (get_clock_monotonic() * 125) >> 9; |
1da177e4 LT |
73 | } |
74 | ||
32f65f27 JG |
75 | /* |
76 | * Monotonic_clock - returns # of nanoseconds passed since time_init() | |
77 | */ | |
78 | unsigned long long monotonic_clock(void) | |
79 | { | |
80 | return sched_clock(); | |
81 | } | |
82 | EXPORT_SYMBOL(monotonic_clock); | |
83 | ||
1da177e4 LT |
84 | void tod_to_timeval(__u64 todval, struct timespec *xtime) |
85 | { | |
86 | unsigned long long sec; | |
87 | ||
88 | sec = todval >> 12; | |
89 | do_div(sec, 1000000); | |
90 | xtime->tv_sec = sec; | |
91 | todval -= (sec * 1000000) << 12; | |
92 | xtime->tv_nsec = ((todval * 1000) >> 12); | |
93 | } | |
94 | ||
5a62b192 | 95 | void clock_comparator_work(void) |
1da177e4 | 96 | { |
5a62b192 | 97 | struct clock_event_device *cd; |
1da177e4 | 98 | |
5a62b192 HC |
99 | S390_lowcore.clock_comparator = -1ULL; |
100 | set_clock_comparator(S390_lowcore.clock_comparator); | |
101 | cd = &__get_cpu_var(comparators); | |
102 | cd->event_handler(cd); | |
1da177e4 LT |
103 | } |
104 | ||
1da177e4 | 105 | /* |
5a62b192 | 106 | * Fixup the clock comparator. |
1da177e4 | 107 | */ |
5a62b192 | 108 | static void fixup_clock_comparator(unsigned long long delta) |
1da177e4 | 109 | { |
5a62b192 HC |
110 | /* If nobody is waiting there's nothing to fix. */ |
111 | if (S390_lowcore.clock_comparator == -1ULL) | |
1da177e4 | 112 | return; |
5a62b192 HC |
113 | S390_lowcore.clock_comparator += delta; |
114 | set_clock_comparator(S390_lowcore.clock_comparator); | |
1da177e4 LT |
115 | } |
116 | ||
5a62b192 HC |
117 | static int s390_next_event(unsigned long delta, |
118 | struct clock_event_device *evt) | |
1da177e4 | 119 | { |
5a62b192 HC |
120 | S390_lowcore.clock_comparator = get_clock() + delta; |
121 | set_clock_comparator(S390_lowcore.clock_comparator); | |
122 | return 0; | |
1da177e4 LT |
123 | } |
124 | ||
5a62b192 HC |
125 | static void s390_set_mode(enum clock_event_mode mode, |
126 | struct clock_event_device *evt) | |
1da177e4 | 127 | { |
d54853ef MS |
128 | } |
129 | ||
130 | /* | |
131 | * Set up lowcore and control register of the current cpu to | |
132 | * enable TOD clock and clock comparator interrupts. | |
1da177e4 LT |
133 | */ |
134 | void init_cpu_timer(void) | |
135 | { | |
5a62b192 HC |
136 | struct clock_event_device *cd; |
137 | int cpu; | |
138 | ||
139 | S390_lowcore.clock_comparator = -1ULL; | |
140 | set_clock_comparator(S390_lowcore.clock_comparator); | |
141 | ||
142 | cpu = smp_processor_id(); | |
143 | cd = &per_cpu(comparators, cpu); | |
144 | cd->name = "comparator"; | |
145 | cd->features = CLOCK_EVT_FEAT_ONESHOT; | |
146 | cd->mult = 16777; | |
147 | cd->shift = 12; | |
148 | cd->min_delta_ns = 1; | |
149 | cd->max_delta_ns = LONG_MAX; | |
150 | cd->rating = 400; | |
320ab2b0 | 151 | cd->cpumask = cpumask_of(cpu); |
5a62b192 HC |
152 | cd->set_next_event = s390_next_event; |
153 | cd->set_mode = s390_set_mode; | |
154 | ||
155 | clockevents_register_device(cd); | |
d54853ef MS |
156 | |
157 | /* Enable clock comparator timer interrupt. */ | |
158 | __ctl_set_bit(0,11); | |
159 | ||
d2fec595 | 160 | /* Always allow the timing alert external interrupt. */ |
d54853ef MS |
161 | __ctl_set_bit(0, 4); |
162 | } | |
163 | ||
164 | static void clock_comparator_interrupt(__u16 code) | |
165 | { | |
d3d238c7 HC |
166 | if (S390_lowcore.clock_comparator == -1ULL) |
167 | set_clock_comparator(S390_lowcore.clock_comparator); | |
d54853ef MS |
168 | } |
169 | ||
d2fec595 MS |
170 | static void etr_timing_alert(struct etr_irq_parm *); |
171 | static void stp_timing_alert(struct stp_irq_parm *); | |
172 | ||
173 | static void timing_alert_interrupt(__u16 code) | |
174 | { | |
175 | if (S390_lowcore.ext_params & 0x00c40000) | |
176 | etr_timing_alert((struct etr_irq_parm *) | |
177 | &S390_lowcore.ext_params); | |
178 | if (S390_lowcore.ext_params & 0x00038000) | |
179 | stp_timing_alert((struct stp_irq_parm *) | |
180 | &S390_lowcore.ext_params); | |
181 | } | |
182 | ||
d54853ef | 183 | static void etr_reset(void); |
d2fec595 | 184 | static void stp_reset(void); |
d54853ef | 185 | |
b6112ccb | 186 | unsigned long read_persistent_clock(void) |
d54853ef | 187 | { |
b6112ccb | 188 | struct timespec ts; |
d54853ef | 189 | |
b6112ccb MS |
190 | tod_to_timeval(get_clock() - TOD_UNIX_EPOCH, &ts); |
191 | return ts.tv_sec; | |
1da177e4 LT |
192 | } |
193 | ||
8e19608e | 194 | static cycle_t read_tod_clock(struct clocksource *cs) |
dc64bef5 MS |
195 | { |
196 | return get_clock(); | |
197 | } | |
198 | ||
199 | static struct clocksource clocksource_tod = { | |
200 | .name = "tod", | |
d2cb0e6e | 201 | .rating = 400, |
dc64bef5 MS |
202 | .read = read_tod_clock, |
203 | .mask = -1ULL, | |
204 | .mult = 1000, | |
205 | .shift = 12, | |
cc02d809 | 206 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, |
dc64bef5 MS |
207 | }; |
208 | ||
209 | ||
b020632e MS |
210 | void update_vsyscall(struct timespec *wall_time, struct clocksource *clock) |
211 | { | |
212 | if (clock != &clocksource_tod) | |
213 | return; | |
214 | ||
215 | /* Make userspace gettimeofday spin until we're done. */ | |
216 | ++vdso_data->tb_update_count; | |
217 | smp_wmb(); | |
218 | vdso_data->xtime_tod_stamp = clock->cycle_last; | |
219 | vdso_data->xtime_clock_sec = xtime.tv_sec; | |
220 | vdso_data->xtime_clock_nsec = xtime.tv_nsec; | |
221 | vdso_data->wtom_clock_sec = wall_to_monotonic.tv_sec; | |
222 | vdso_data->wtom_clock_nsec = wall_to_monotonic.tv_nsec; | |
223 | smp_wmb(); | |
224 | ++vdso_data->tb_update_count; | |
225 | } | |
226 | ||
227 | extern struct timezone sys_tz; | |
228 | ||
229 | void update_vsyscall_tz(void) | |
230 | { | |
231 | /* Make userspace gettimeofday spin until we're done. */ | |
232 | ++vdso_data->tb_update_count; | |
233 | smp_wmb(); | |
234 | vdso_data->tz_minuteswest = sys_tz.tz_minuteswest; | |
235 | vdso_data->tz_dsttime = sys_tz.tz_dsttime; | |
236 | smp_wmb(); | |
237 | ++vdso_data->tb_update_count; | |
238 | } | |
239 | ||
1da177e4 LT |
240 | /* |
241 | * Initialize the TOD clock and the CPU timer of | |
242 | * the boot cpu. | |
243 | */ | |
244 | void __init time_init(void) | |
245 | { | |
ab96e798 MS |
246 | struct timespec ts; |
247 | unsigned long flags; | |
248 | cycle_t now; | |
249 | ||
b6112ccb MS |
250 | /* Reset time synchronization interfaces. */ |
251 | etr_reset(); | |
252 | stp_reset(); | |
1da177e4 | 253 | |
1da177e4 | 254 | /* request the clock comparator external interrupt */ |
d7d1104f | 255 | if (register_external_interrupt(0x1004, clock_comparator_interrupt)) |
1da177e4 LT |
256 | panic("Couldn't request external interrupt 0x1004"); |
257 | ||
d2fec595 | 258 | /* request the timing alert external interrupt */ |
d7d1104f | 259 | if (register_external_interrupt(0x1406, timing_alert_interrupt)) |
d54853ef MS |
260 | panic("Couldn't request external interrupt 0x1406"); |
261 | ||
ab96e798 MS |
262 | if (clocksource_register(&clocksource_tod) != 0) |
263 | panic("Could not register TOD clock source"); | |
264 | ||
265 | /* | |
266 | * The TOD clock is an accurate clock. The xtime should be | |
267 | * initialized in a way that the difference between TOD and | |
268 | * xtime is reasonably small. Too bad that timekeeping_init | |
269 | * sets xtime.tv_nsec to zero. In addition the clock source | |
270 | * change from the jiffies clock source to the TOD clock | |
271 | * source add another error of up to 1/HZ second. The same | |
272 | * function sets wall_to_monotonic to a value that is too | |
273 | * small for /proc/uptime to be accurate. | |
274 | * Reset xtime and wall_to_monotonic to sane values. | |
275 | */ | |
276 | write_seqlock_irqsave(&xtime_lock, flags); | |
277 | now = get_clock(); | |
278 | tod_to_timeval(now - TOD_UNIX_EPOCH, &xtime); | |
279 | clocksource_tod.cycle_last = now; | |
280 | clocksource_tod.raw_time = xtime; | |
281 | tod_to_timeval(sched_clock_base_cc - TOD_UNIX_EPOCH, &ts); | |
282 | set_normalized_timespec(&wall_to_monotonic, -ts.tv_sec, -ts.tv_nsec); | |
283 | write_sequnlock_irqrestore(&xtime_lock, flags); | |
284 | ||
d54853ef MS |
285 | /* Enable TOD clock interrupts on the boot cpu. */ |
286 | init_cpu_timer(); | |
ab96e798 | 287 | |
c185b783 | 288 | /* Enable cpu timer interrupts on the boot cpu. */ |
1da177e4 | 289 | vtime_init(); |
d54853ef MS |
290 | } |
291 | ||
d2fec595 MS |
292 | /* |
293 | * The time is "clock". old is what we think the time is. | |
294 | * Adjust the value by a multiple of jiffies and add the delta to ntp. | |
295 | * "delay" is an approximation how long the synchronization took. If | |
296 | * the time correction is positive, then "delay" is subtracted from | |
297 | * the time difference and only the remaining part is passed to ntp. | |
298 | */ | |
299 | static unsigned long long adjust_time(unsigned long long old, | |
300 | unsigned long long clock, | |
301 | unsigned long long delay) | |
302 | { | |
303 | unsigned long long delta, ticks; | |
304 | struct timex adjust; | |
305 | ||
306 | if (clock > old) { | |
307 | /* It is later than we thought. */ | |
308 | delta = ticks = clock - old; | |
309 | delta = ticks = (delta < delay) ? 0 : delta - delay; | |
310 | delta -= do_div(ticks, CLK_TICKS_PER_JIFFY); | |
311 | adjust.offset = ticks * (1000000 / HZ); | |
312 | } else { | |
313 | /* It is earlier than we thought. */ | |
314 | delta = ticks = old - clock; | |
315 | delta -= do_div(ticks, CLK_TICKS_PER_JIFFY); | |
316 | delta = -delta; | |
317 | adjust.offset = -ticks * (1000000 / HZ); | |
318 | } | |
8107d829 | 319 | sched_clock_base_cc += delta; |
d2fec595 | 320 | if (adjust.offset != 0) { |
feab6501 MS |
321 | pr_notice("The ETR interface has adjusted the clock " |
322 | "by %li microseconds\n", adjust.offset); | |
d2fec595 MS |
323 | adjust.modes = ADJ_OFFSET_SINGLESHOT; |
324 | do_adjtimex(&adjust); | |
325 | } | |
326 | return delta; | |
327 | } | |
328 | ||
329 | static DEFINE_PER_CPU(atomic_t, clock_sync_word); | |
8283cb43 | 330 | static DEFINE_MUTEX(clock_sync_mutex); |
d2fec595 MS |
331 | static unsigned long clock_sync_flags; |
332 | ||
333 | #define CLOCK_SYNC_HAS_ETR 0 | |
334 | #define CLOCK_SYNC_HAS_STP 1 | |
335 | #define CLOCK_SYNC_ETR 2 | |
336 | #define CLOCK_SYNC_STP 3 | |
337 | ||
338 | /* | |
339 | * The synchronous get_clock function. It will write the current clock | |
340 | * value to the clock pointer and return 0 if the clock is in sync with | |
341 | * the external time source. If the clock mode is local it will return | |
342 | * -ENOSYS and -EAGAIN if the clock is not in sync with the external | |
343 | * reference. | |
344 | */ | |
345 | int get_sync_clock(unsigned long long *clock) | |
346 | { | |
347 | atomic_t *sw_ptr; | |
348 | unsigned int sw0, sw1; | |
349 | ||
350 | sw_ptr = &get_cpu_var(clock_sync_word); | |
351 | sw0 = atomic_read(sw_ptr); | |
352 | *clock = get_clock(); | |
353 | sw1 = atomic_read(sw_ptr); | |
354 | put_cpu_var(clock_sync_sync); | |
355 | if (sw0 == sw1 && (sw0 & 0x80000000U)) | |
356 | /* Success: time is in sync. */ | |
357 | return 0; | |
358 | if (!test_bit(CLOCK_SYNC_HAS_ETR, &clock_sync_flags) && | |
359 | !test_bit(CLOCK_SYNC_HAS_STP, &clock_sync_flags)) | |
360 | return -ENOSYS; | |
361 | if (!test_bit(CLOCK_SYNC_ETR, &clock_sync_flags) && | |
362 | !test_bit(CLOCK_SYNC_STP, &clock_sync_flags)) | |
363 | return -EACCES; | |
364 | return -EAGAIN; | |
365 | } | |
366 | EXPORT_SYMBOL(get_sync_clock); | |
367 | ||
368 | /* | |
369 | * Make get_sync_clock return -EAGAIN. | |
370 | */ | |
371 | static void disable_sync_clock(void *dummy) | |
372 | { | |
373 | atomic_t *sw_ptr = &__get_cpu_var(clock_sync_word); | |
374 | /* | |
375 | * Clear the in-sync bit 2^31. All get_sync_clock calls will | |
376 | * fail until the sync bit is turned back on. In addition | |
377 | * increase the "sequence" counter to avoid the race of an | |
378 | * etr event and the complete recovery against get_sync_clock. | |
379 | */ | |
380 | atomic_clear_mask(0x80000000, sw_ptr); | |
381 | atomic_inc(sw_ptr); | |
382 | } | |
383 | ||
384 | /* | |
385 | * Make get_sync_clock return 0 again. | |
386 | * Needs to be called from a context disabled for preemption. | |
387 | */ | |
388 | static void enable_sync_clock(void) | |
389 | { | |
390 | atomic_t *sw_ptr = &__get_cpu_var(clock_sync_word); | |
391 | atomic_set_mask(0x80000000, sw_ptr); | |
392 | } | |
393 | ||
8283cb43 MS |
394 | /* |
395 | * Function to check if the clock is in sync. | |
396 | */ | |
397 | static inline int check_sync_clock(void) | |
398 | { | |
399 | atomic_t *sw_ptr; | |
400 | int rc; | |
401 | ||
402 | sw_ptr = &get_cpu_var(clock_sync_word); | |
403 | rc = (atomic_read(sw_ptr) & 0x80000000U) != 0; | |
404 | put_cpu_var(clock_sync_sync); | |
405 | return rc; | |
406 | } | |
407 | ||
750887de HC |
408 | /* Single threaded workqueue used for etr and stp sync events */ |
409 | static struct workqueue_struct *time_sync_wq; | |
410 | ||
411 | static void __init time_init_wq(void) | |
412 | { | |
179cb81a HC |
413 | if (time_sync_wq) |
414 | return; | |
415 | time_sync_wq = create_singlethread_workqueue("timesync"); | |
416 | stop_machine_create(); | |
750887de HC |
417 | } |
418 | ||
d54853ef MS |
419 | /* |
420 | * External Time Reference (ETR) code. | |
421 | */ | |
422 | static int etr_port0_online; | |
423 | static int etr_port1_online; | |
d2fec595 | 424 | static int etr_steai_available; |
d54853ef MS |
425 | |
426 | static int __init early_parse_etr(char *p) | |
427 | { | |
428 | if (strncmp(p, "off", 3) == 0) | |
429 | etr_port0_online = etr_port1_online = 0; | |
430 | else if (strncmp(p, "port0", 5) == 0) | |
431 | etr_port0_online = 1; | |
432 | else if (strncmp(p, "port1", 5) == 0) | |
433 | etr_port1_online = 1; | |
434 | else if (strncmp(p, "on", 2) == 0) | |
435 | etr_port0_online = etr_port1_online = 1; | |
436 | return 0; | |
437 | } | |
438 | early_param("etr", early_parse_etr); | |
439 | ||
440 | enum etr_event { | |
441 | ETR_EVENT_PORT0_CHANGE, | |
442 | ETR_EVENT_PORT1_CHANGE, | |
443 | ETR_EVENT_PORT_ALERT, | |
444 | ETR_EVENT_SYNC_CHECK, | |
445 | ETR_EVENT_SWITCH_LOCAL, | |
446 | ETR_EVENT_UPDATE, | |
447 | }; | |
448 | ||
d54853ef MS |
449 | /* |
450 | * Valid bit combinations of the eacr register are (x = don't care): | |
451 | * e0 e1 dp p0 p1 ea es sl | |
452 | * 0 0 x 0 0 0 0 0 initial, disabled state | |
453 | * 0 0 x 0 1 1 0 0 port 1 online | |
454 | * 0 0 x 1 0 1 0 0 port 0 online | |
455 | * 0 0 x 1 1 1 0 0 both ports online | |
456 | * 0 1 x 0 1 1 0 0 port 1 online and usable, ETR or PPS mode | |
457 | * 0 1 x 0 1 1 0 1 port 1 online, usable and ETR mode | |
458 | * 0 1 x 0 1 1 1 0 port 1 online, usable, PPS mode, in-sync | |
459 | * 0 1 x 0 1 1 1 1 port 1 online, usable, ETR mode, in-sync | |
460 | * 0 1 x 1 1 1 0 0 both ports online, port 1 usable | |
461 | * 0 1 x 1 1 1 1 0 both ports online, port 1 usable, PPS mode, in-sync | |
462 | * 0 1 x 1 1 1 1 1 both ports online, port 1 usable, ETR mode, in-sync | |
463 | * 1 0 x 1 0 1 0 0 port 0 online and usable, ETR or PPS mode | |
464 | * 1 0 x 1 0 1 0 1 port 0 online, usable and ETR mode | |
465 | * 1 0 x 1 0 1 1 0 port 0 online, usable, PPS mode, in-sync | |
466 | * 1 0 x 1 0 1 1 1 port 0 online, usable, ETR mode, in-sync | |
467 | * 1 0 x 1 1 1 0 0 both ports online, port 0 usable | |
468 | * 1 0 x 1 1 1 1 0 both ports online, port 0 usable, PPS mode, in-sync | |
469 | * 1 0 x 1 1 1 1 1 both ports online, port 0 usable, ETR mode, in-sync | |
470 | * 1 1 x 1 1 1 1 0 both ports online & usable, ETR, in-sync | |
471 | * 1 1 x 1 1 1 1 1 both ports online & usable, ETR, in-sync | |
472 | */ | |
473 | static struct etr_eacr etr_eacr; | |
474 | static u64 etr_tolec; /* time of last eacr update */ | |
d54853ef MS |
475 | static struct etr_aib etr_port0; |
476 | static int etr_port0_uptodate; | |
477 | static struct etr_aib etr_port1; | |
478 | static int etr_port1_uptodate; | |
479 | static unsigned long etr_events; | |
480 | static struct timer_list etr_timer; | |
d54853ef MS |
481 | |
482 | static void etr_timeout(unsigned long dummy); | |
ecdcc023 | 483 | static void etr_work_fn(struct work_struct *work); |
0b3016b7 | 484 | static DEFINE_MUTEX(etr_work_mutex); |
ecdcc023 | 485 | static DECLARE_WORK(etr_work, etr_work_fn); |
d54853ef | 486 | |
d54853ef MS |
487 | /* |
488 | * Reset ETR attachment. | |
489 | */ | |
490 | static void etr_reset(void) | |
491 | { | |
492 | etr_eacr = (struct etr_eacr) { | |
493 | .e0 = 0, .e1 = 0, ._pad0 = 4, .dp = 0, | |
494 | .p0 = 0, .p1 = 0, ._pad1 = 0, .ea = 0, | |
495 | .es = 0, .sl = 0 }; | |
d2fec595 | 496 | if (etr_setr(&etr_eacr) == 0) { |
d54853ef | 497 | etr_tolec = get_clock(); |
d2fec595 | 498 | set_bit(CLOCK_SYNC_HAS_ETR, &clock_sync_flags); |
8283cb43 MS |
499 | if (etr_port0_online && etr_port1_online) |
500 | set_bit(CLOCK_SYNC_ETR, &clock_sync_flags); | |
d2fec595 | 501 | } else if (etr_port0_online || etr_port1_online) { |
feab6501 MS |
502 | pr_warning("The real or virtual hardware system does " |
503 | "not provide an ETR interface\n"); | |
d2fec595 | 504 | etr_port0_online = etr_port1_online = 0; |
d54853ef MS |
505 | } |
506 | } | |
507 | ||
ecdcc023 | 508 | static int __init etr_init(void) |
d54853ef MS |
509 | { |
510 | struct etr_aib aib; | |
511 | ||
d2fec595 | 512 | if (!test_bit(CLOCK_SYNC_HAS_ETR, &clock_sync_flags)) |
ecdcc023 | 513 | return 0; |
750887de | 514 | time_init_wq(); |
d54853ef MS |
515 | /* Check if this machine has the steai instruction. */ |
516 | if (etr_steai(&aib, ETR_STEAI_STEPPING_PORT) == 0) | |
d2fec595 | 517 | etr_steai_available = 1; |
d54853ef | 518 | setup_timer(&etr_timer, etr_timeout, 0UL); |
d54853ef MS |
519 | if (etr_port0_online) { |
520 | set_bit(ETR_EVENT_PORT0_CHANGE, &etr_events); | |
750887de | 521 | queue_work(time_sync_wq, &etr_work); |
d54853ef MS |
522 | } |
523 | if (etr_port1_online) { | |
524 | set_bit(ETR_EVENT_PORT1_CHANGE, &etr_events); | |
750887de | 525 | queue_work(time_sync_wq, &etr_work); |
d54853ef | 526 | } |
ecdcc023 | 527 | return 0; |
d54853ef MS |
528 | } |
529 | ||
ecdcc023 MS |
530 | arch_initcall(etr_init); |
531 | ||
d54853ef MS |
532 | /* |
533 | * Two sorts of ETR machine checks. The architecture reads: | |
534 | * "When a machine-check niterruption occurs and if a switch-to-local or | |
535 | * ETR-sync-check interrupt request is pending but disabled, this pending | |
536 | * disabled interruption request is indicated and is cleared". | |
537 | * Which means that we can get etr_switch_to_local events from the machine | |
538 | * check handler although the interruption condition is disabled. Lovely.. | |
539 | */ | |
540 | ||
541 | /* | |
542 | * Switch to local machine check. This is called when the last usable | |
543 | * ETR port goes inactive. After switch to local the clock is not in sync. | |
544 | */ | |
545 | void etr_switch_to_local(void) | |
546 | { | |
547 | if (!etr_eacr.sl) | |
548 | return; | |
8283cb43 | 549 | disable_sync_clock(NULL); |
d54853ef | 550 | set_bit(ETR_EVENT_SWITCH_LOCAL, &etr_events); |
750887de | 551 | queue_work(time_sync_wq, &etr_work); |
d54853ef MS |
552 | } |
553 | ||
554 | /* | |
555 | * ETR sync check machine check. This is called when the ETR OTE and the | |
556 | * local clock OTE are farther apart than the ETR sync check tolerance. | |
557 | * After a ETR sync check the clock is not in sync. The machine check | |
558 | * is broadcasted to all cpus at the same time. | |
559 | */ | |
560 | void etr_sync_check(void) | |
561 | { | |
562 | if (!etr_eacr.es) | |
563 | return; | |
8283cb43 | 564 | disable_sync_clock(NULL); |
d54853ef | 565 | set_bit(ETR_EVENT_SYNC_CHECK, &etr_events); |
750887de | 566 | queue_work(time_sync_wq, &etr_work); |
d54853ef MS |
567 | } |
568 | ||
569 | /* | |
d2fec595 | 570 | * ETR timing alert. There are two causes: |
d54853ef MS |
571 | * 1) port state change, check the usability of the port |
572 | * 2) port alert, one of the ETR-data-validity bits (v1-v2 bits of the | |
573 | * sldr-status word) or ETR-data word 1 (edf1) or ETR-data word 3 (edf3) | |
574 | * or ETR-data word 4 (edf4) has changed. | |
575 | */ | |
d2fec595 | 576 | static void etr_timing_alert(struct etr_irq_parm *intparm) |
d54853ef | 577 | { |
d54853ef MS |
578 | if (intparm->pc0) |
579 | /* ETR port 0 state change. */ | |
580 | set_bit(ETR_EVENT_PORT0_CHANGE, &etr_events); | |
581 | if (intparm->pc1) | |
582 | /* ETR port 1 state change. */ | |
583 | set_bit(ETR_EVENT_PORT1_CHANGE, &etr_events); | |
584 | if (intparm->eai) | |
585 | /* | |
586 | * ETR port alert on either port 0, 1 or both. | |
587 | * Both ports are not up-to-date now. | |
588 | */ | |
589 | set_bit(ETR_EVENT_PORT_ALERT, &etr_events); | |
750887de | 590 | queue_work(time_sync_wq, &etr_work); |
d54853ef MS |
591 | } |
592 | ||
593 | static void etr_timeout(unsigned long dummy) | |
594 | { | |
595 | set_bit(ETR_EVENT_UPDATE, &etr_events); | |
750887de | 596 | queue_work(time_sync_wq, &etr_work); |
d54853ef MS |
597 | } |
598 | ||
599 | /* | |
600 | * Check if the etr mode is pss. | |
601 | */ | |
602 | static inline int etr_mode_is_pps(struct etr_eacr eacr) | |
603 | { | |
604 | return eacr.es && !eacr.sl; | |
605 | } | |
606 | ||
607 | /* | |
608 | * Check if the etr mode is etr. | |
609 | */ | |
610 | static inline int etr_mode_is_etr(struct etr_eacr eacr) | |
611 | { | |
612 | return eacr.es && eacr.sl; | |
613 | } | |
614 | ||
615 | /* | |
616 | * Check if the port can be used for TOD synchronization. | |
617 | * For PPS mode the port has to receive OTEs. For ETR mode | |
618 | * the port has to receive OTEs, the ETR stepping bit has to | |
619 | * be zero and the validity bits for data frame 1, 2, and 3 | |
620 | * have to be 1. | |
621 | */ | |
622 | static int etr_port_valid(struct etr_aib *aib, int port) | |
623 | { | |
624 | unsigned int psc; | |
625 | ||
626 | /* Check that this port is receiving OTEs. */ | |
627 | if (aib->tsp == 0) | |
628 | return 0; | |
629 | ||
630 | psc = port ? aib->esw.psc1 : aib->esw.psc0; | |
631 | if (psc == etr_lpsc_pps_mode) | |
632 | return 1; | |
633 | if (psc == etr_lpsc_operational_step) | |
634 | return !aib->esw.y && aib->slsw.v1 && | |
635 | aib->slsw.v2 && aib->slsw.v3; | |
636 | return 0; | |
637 | } | |
638 | ||
639 | /* | |
640 | * Check if two ports are on the same network. | |
641 | */ | |
642 | static int etr_compare_network(struct etr_aib *aib1, struct etr_aib *aib2) | |
643 | { | |
644 | // FIXME: any other fields we have to compare? | |
645 | return aib1->edf1.net_id == aib2->edf1.net_id; | |
646 | } | |
647 | ||
648 | /* | |
649 | * Wrapper for etr_stei that converts physical port states | |
650 | * to logical port states to be consistent with the output | |
651 | * of stetr (see etr_psc vs. etr_lpsc). | |
652 | */ | |
653 | static void etr_steai_cv(struct etr_aib *aib, unsigned int func) | |
654 | { | |
655 | BUG_ON(etr_steai(aib, func) != 0); | |
656 | /* Convert port state to logical port state. */ | |
657 | if (aib->esw.psc0 == 1) | |
658 | aib->esw.psc0 = 2; | |
659 | else if (aib->esw.psc0 == 0 && aib->esw.p == 0) | |
660 | aib->esw.psc0 = 1; | |
661 | if (aib->esw.psc1 == 1) | |
662 | aib->esw.psc1 = 2; | |
663 | else if (aib->esw.psc1 == 0 && aib->esw.p == 1) | |
664 | aib->esw.psc1 = 1; | |
665 | } | |
666 | ||
667 | /* | |
668 | * Check if the aib a2 is still connected to the same attachment as | |
669 | * aib a1, the etv values differ by one and a2 is valid. | |
670 | */ | |
671 | static int etr_aib_follows(struct etr_aib *a1, struct etr_aib *a2, int p) | |
672 | { | |
673 | int state_a1, state_a2; | |
674 | ||
675 | /* Paranoia check: e0/e1 should better be the same. */ | |
676 | if (a1->esw.eacr.e0 != a2->esw.eacr.e0 || | |
677 | a1->esw.eacr.e1 != a2->esw.eacr.e1) | |
678 | return 0; | |
679 | ||
680 | /* Still connected to the same etr ? */ | |
681 | state_a1 = p ? a1->esw.psc1 : a1->esw.psc0; | |
682 | state_a2 = p ? a2->esw.psc1 : a2->esw.psc0; | |
683 | if (state_a1 == etr_lpsc_operational_step) { | |
684 | if (state_a2 != etr_lpsc_operational_step || | |
685 | a1->edf1.net_id != a2->edf1.net_id || | |
686 | a1->edf1.etr_id != a2->edf1.etr_id || | |
687 | a1->edf1.etr_pn != a2->edf1.etr_pn) | |
688 | return 0; | |
689 | } else if (state_a2 != etr_lpsc_pps_mode) | |
690 | return 0; | |
691 | ||
692 | /* The ETV value of a2 needs to be ETV of a1 + 1. */ | |
693 | if (a1->edf2.etv + 1 != a2->edf2.etv) | |
694 | return 0; | |
695 | ||
696 | if (!etr_port_valid(a2, p)) | |
697 | return 0; | |
698 | ||
699 | return 1; | |
700 | } | |
701 | ||
d2fec595 | 702 | struct clock_sync_data { |
750887de | 703 | atomic_t cpus; |
5a62b192 HC |
704 | int in_sync; |
705 | unsigned long long fixup_cc; | |
750887de HC |
706 | int etr_port; |
707 | struct etr_aib *etr_aib; | |
d2fec595 | 708 | }; |
5a62b192 | 709 | |
750887de | 710 | static void clock_sync_cpu(struct clock_sync_data *sync) |
d54853ef | 711 | { |
750887de | 712 | atomic_dec(&sync->cpus); |
d2fec595 | 713 | enable_sync_clock(); |
d54853ef MS |
714 | /* |
715 | * This looks like a busy wait loop but it isn't. etr_sync_cpus | |
716 | * is called on all other cpus while the TOD clocks is stopped. | |
717 | * __udelay will stop the cpu on an enabled wait psw until the | |
718 | * TOD is running again. | |
719 | */ | |
d2fec595 | 720 | while (sync->in_sync == 0) { |
d54853ef | 721 | __udelay(1); |
6c732de2 HC |
722 | /* |
723 | * A different cpu changes *in_sync. Therefore use | |
724 | * barrier() to force memory access. | |
725 | */ | |
726 | barrier(); | |
727 | } | |
d2fec595 | 728 | if (sync->in_sync != 1) |
d54853ef | 729 | /* Didn't work. Clear per-cpu in sync bit again. */ |
d2fec595 | 730 | disable_sync_clock(NULL); |
d54853ef MS |
731 | /* |
732 | * This round of TOD syncing is done. Set the clock comparator | |
733 | * to the next tick and let the processor continue. | |
734 | */ | |
d2fec595 | 735 | fixup_clock_comparator(sync->fixup_cc); |
d54853ef MS |
736 | } |
737 | ||
d54853ef MS |
738 | /* |
739 | * Sync the TOD clock using the port refered to by aibp. This port | |
740 | * has to be enabled and the other port has to be disabled. The | |
741 | * last eacr update has to be more than 1.6 seconds in the past. | |
742 | */ | |
750887de | 743 | static int etr_sync_clock(void *data) |
d54853ef | 744 | { |
750887de | 745 | static int first; |
5a62b192 | 746 | unsigned long long clock, old_clock, delay, delta; |
750887de HC |
747 | struct clock_sync_data *etr_sync; |
748 | struct etr_aib *sync_port, *aib; | |
749 | int port; | |
d54853ef MS |
750 | int rc; |
751 | ||
750887de | 752 | etr_sync = data; |
d54853ef | 753 | |
750887de HC |
754 | if (xchg(&first, 1) == 1) { |
755 | /* Slave */ | |
756 | clock_sync_cpu(etr_sync); | |
757 | return 0; | |
758 | } | |
759 | ||
760 | /* Wait until all other cpus entered the sync function. */ | |
761 | while (atomic_read(&etr_sync->cpus) != 0) | |
762 | cpu_relax(); | |
763 | ||
764 | port = etr_sync->etr_port; | |
765 | aib = etr_sync->etr_aib; | |
766 | sync_port = (port == 0) ? &etr_port0 : &etr_port1; | |
d2fec595 | 767 | enable_sync_clock(); |
d54853ef MS |
768 | |
769 | /* Set clock to next OTE. */ | |
770 | __ctl_set_bit(14, 21); | |
771 | __ctl_set_bit(0, 29); | |
772 | clock = ((unsigned long long) (aib->edf2.etv + 1)) << 32; | |
5a62b192 | 773 | old_clock = get_clock(); |
d54853ef MS |
774 | if (set_clock(clock) == 0) { |
775 | __udelay(1); /* Wait for the clock to start. */ | |
776 | __ctl_clear_bit(0, 29); | |
777 | __ctl_clear_bit(14, 21); | |
778 | etr_stetr(aib); | |
779 | /* Adjust Linux timing variables. */ | |
780 | delay = (unsigned long long) | |
781 | (aib->edf2.etv - sync_port->edf2.etv) << 32; | |
d2fec595 | 782 | delta = adjust_time(old_clock, clock, delay); |
750887de | 783 | etr_sync->fixup_cc = delta; |
5a62b192 | 784 | fixup_clock_comparator(delta); |
d54853ef MS |
785 | /* Verify that the clock is properly set. */ |
786 | if (!etr_aib_follows(sync_port, aib, port)) { | |
787 | /* Didn't work. */ | |
d2fec595 | 788 | disable_sync_clock(NULL); |
750887de | 789 | etr_sync->in_sync = -EAGAIN; |
d54853ef MS |
790 | rc = -EAGAIN; |
791 | } else { | |
750887de | 792 | etr_sync->in_sync = 1; |
d54853ef MS |
793 | rc = 0; |
794 | } | |
795 | } else { | |
796 | /* Could not set the clock ?!? */ | |
797 | __ctl_clear_bit(0, 29); | |
798 | __ctl_clear_bit(14, 21); | |
d2fec595 | 799 | disable_sync_clock(NULL); |
750887de | 800 | etr_sync->in_sync = -EAGAIN; |
d54853ef MS |
801 | rc = -EAGAIN; |
802 | } | |
750887de HC |
803 | xchg(&first, 0); |
804 | return rc; | |
805 | } | |
806 | ||
807 | static int etr_sync_clock_stop(struct etr_aib *aib, int port) | |
808 | { | |
809 | struct clock_sync_data etr_sync; | |
810 | struct etr_aib *sync_port; | |
811 | int follows; | |
812 | int rc; | |
813 | ||
814 | /* Check if the current aib is adjacent to the sync port aib. */ | |
815 | sync_port = (port == 0) ? &etr_port0 : &etr_port1; | |
816 | follows = etr_aib_follows(sync_port, aib, port); | |
817 | memcpy(sync_port, aib, sizeof(*aib)); | |
818 | if (!follows) | |
819 | return -EAGAIN; | |
820 | memset(&etr_sync, 0, sizeof(etr_sync)); | |
821 | etr_sync.etr_aib = aib; | |
822 | etr_sync.etr_port = port; | |
823 | get_online_cpus(); | |
824 | atomic_set(&etr_sync.cpus, num_online_cpus() - 1); | |
825 | rc = stop_machine(etr_sync_clock, &etr_sync, &cpu_online_map); | |
826 | put_online_cpus(); | |
d54853ef MS |
827 | return rc; |
828 | } | |
829 | ||
830 | /* | |
831 | * Handle the immediate effects of the different events. | |
832 | * The port change event is used for online/offline changes. | |
833 | */ | |
834 | static struct etr_eacr etr_handle_events(struct etr_eacr eacr) | |
835 | { | |
836 | if (test_and_clear_bit(ETR_EVENT_SYNC_CHECK, &etr_events)) | |
837 | eacr.es = 0; | |
838 | if (test_and_clear_bit(ETR_EVENT_SWITCH_LOCAL, &etr_events)) | |
839 | eacr.es = eacr.sl = 0; | |
840 | if (test_and_clear_bit(ETR_EVENT_PORT_ALERT, &etr_events)) | |
841 | etr_port0_uptodate = etr_port1_uptodate = 0; | |
842 | ||
843 | if (test_and_clear_bit(ETR_EVENT_PORT0_CHANGE, &etr_events)) { | |
844 | if (eacr.e0) | |
845 | /* | |
846 | * Port change of an enabled port. We have to | |
847 | * assume that this can have caused an stepping | |
848 | * port switch. | |
849 | */ | |
850 | etr_tolec = get_clock(); | |
851 | eacr.p0 = etr_port0_online; | |
852 | if (!eacr.p0) | |
853 | eacr.e0 = 0; | |
854 | etr_port0_uptodate = 0; | |
855 | } | |
856 | if (test_and_clear_bit(ETR_EVENT_PORT1_CHANGE, &etr_events)) { | |
857 | if (eacr.e1) | |
858 | /* | |
859 | * Port change of an enabled port. We have to | |
860 | * assume that this can have caused an stepping | |
861 | * port switch. | |
862 | */ | |
863 | etr_tolec = get_clock(); | |
864 | eacr.p1 = etr_port1_online; | |
865 | if (!eacr.p1) | |
866 | eacr.e1 = 0; | |
867 | etr_port1_uptodate = 0; | |
868 | } | |
869 | clear_bit(ETR_EVENT_UPDATE, &etr_events); | |
870 | return eacr; | |
871 | } | |
872 | ||
873 | /* | |
874 | * Set up a timer that expires after the etr_tolec + 1.6 seconds if | |
875 | * one of the ports needs an update. | |
876 | */ | |
877 | static void etr_set_tolec_timeout(unsigned long long now) | |
878 | { | |
879 | unsigned long micros; | |
880 | ||
881 | if ((!etr_eacr.p0 || etr_port0_uptodate) && | |
882 | (!etr_eacr.p1 || etr_port1_uptodate)) | |
883 | return; | |
884 | micros = (now > etr_tolec) ? ((now - etr_tolec) >> 12) : 0; | |
885 | micros = (micros > 1600000) ? 0 : 1600000 - micros; | |
886 | mod_timer(&etr_timer, jiffies + (micros * HZ) / 1000000 + 1); | |
887 | } | |
888 | ||
889 | /* | |
890 | * Set up a time that expires after 1/2 second. | |
891 | */ | |
892 | static void etr_set_sync_timeout(void) | |
893 | { | |
894 | mod_timer(&etr_timer, jiffies + HZ/2); | |
895 | } | |
896 | ||
897 | /* | |
898 | * Update the aib information for one or both ports. | |
899 | */ | |
900 | static struct etr_eacr etr_handle_update(struct etr_aib *aib, | |
901 | struct etr_eacr eacr) | |
902 | { | |
903 | /* With both ports disabled the aib information is useless. */ | |
904 | if (!eacr.e0 && !eacr.e1) | |
905 | return eacr; | |
906 | ||
ecdcc023 | 907 | /* Update port0 or port1 with aib stored in etr_work_fn. */ |
d54853ef MS |
908 | if (aib->esw.q == 0) { |
909 | /* Information for port 0 stored. */ | |
910 | if (eacr.p0 && !etr_port0_uptodate) { | |
911 | etr_port0 = *aib; | |
912 | if (etr_port0_online) | |
913 | etr_port0_uptodate = 1; | |
914 | } | |
915 | } else { | |
916 | /* Information for port 1 stored. */ | |
917 | if (eacr.p1 && !etr_port1_uptodate) { | |
918 | etr_port1 = *aib; | |
919 | if (etr_port0_online) | |
920 | etr_port1_uptodate = 1; | |
921 | } | |
922 | } | |
923 | ||
924 | /* | |
925 | * Do not try to get the alternate port aib if the clock | |
926 | * is not in sync yet. | |
927 | */ | |
8283cb43 | 928 | if (!check_sync_clock()) |
d54853ef MS |
929 | return eacr; |
930 | ||
931 | /* | |
932 | * If steai is available we can get the information about | |
933 | * the other port immediately. If only stetr is available the | |
934 | * data-port bit toggle has to be used. | |
935 | */ | |
d2fec595 | 936 | if (etr_steai_available) { |
d54853ef MS |
937 | if (eacr.p0 && !etr_port0_uptodate) { |
938 | etr_steai_cv(&etr_port0, ETR_STEAI_PORT_0); | |
939 | etr_port0_uptodate = 1; | |
940 | } | |
941 | if (eacr.p1 && !etr_port1_uptodate) { | |
942 | etr_steai_cv(&etr_port1, ETR_STEAI_PORT_1); | |
943 | etr_port1_uptodate = 1; | |
944 | } | |
945 | } else { | |
946 | /* | |
947 | * One port was updated above, if the other | |
948 | * port is not uptodate toggle dp bit. | |
949 | */ | |
950 | if ((eacr.p0 && !etr_port0_uptodate) || | |
951 | (eacr.p1 && !etr_port1_uptodate)) | |
952 | eacr.dp ^= 1; | |
953 | else | |
954 | eacr.dp = 0; | |
955 | } | |
956 | return eacr; | |
957 | } | |
958 | ||
959 | /* | |
960 | * Write new etr control register if it differs from the current one. | |
961 | * Return 1 if etr_tolec has been updated as well. | |
962 | */ | |
963 | static void etr_update_eacr(struct etr_eacr eacr) | |
964 | { | |
965 | int dp_changed; | |
966 | ||
967 | if (memcmp(&etr_eacr, &eacr, sizeof(eacr)) == 0) | |
968 | /* No change, return. */ | |
969 | return; | |
970 | /* | |
971 | * The disable of an active port of the change of the data port | |
972 | * bit can/will cause a change in the data port. | |
973 | */ | |
974 | dp_changed = etr_eacr.e0 > eacr.e0 || etr_eacr.e1 > eacr.e1 || | |
975 | (etr_eacr.dp ^ eacr.dp) != 0; | |
976 | etr_eacr = eacr; | |
977 | etr_setr(&etr_eacr); | |
978 | if (dp_changed) | |
979 | etr_tolec = get_clock(); | |
980 | } | |
981 | ||
982 | /* | |
750887de | 983 | * ETR work. In this function you'll find the main logic. In |
d54853ef MS |
984 | * particular this is the only function that calls etr_update_eacr(), |
985 | * it "controls" the etr control register. | |
986 | */ | |
ecdcc023 | 987 | static void etr_work_fn(struct work_struct *work) |
d54853ef MS |
988 | { |
989 | unsigned long long now; | |
990 | struct etr_eacr eacr; | |
991 | struct etr_aib aib; | |
992 | int sync_port; | |
993 | ||
0b3016b7 MS |
994 | /* prevent multiple execution. */ |
995 | mutex_lock(&etr_work_mutex); | |
996 | ||
d54853ef MS |
997 | /* Create working copy of etr_eacr. */ |
998 | eacr = etr_eacr; | |
999 | ||
1000 | /* Check for the different events and their immediate effects. */ | |
1001 | eacr = etr_handle_events(eacr); | |
1002 | ||
1003 | /* Check if ETR is supposed to be active. */ | |
1004 | eacr.ea = eacr.p0 || eacr.p1; | |
1005 | if (!eacr.ea) { | |
1006 | /* Both ports offline. Reset everything. */ | |
1007 | eacr.dp = eacr.es = eacr.sl = 0; | |
1a781a77 | 1008 | on_each_cpu(disable_sync_clock, NULL, 1); |
d54853ef MS |
1009 | del_timer_sync(&etr_timer); |
1010 | etr_update_eacr(eacr); | |
0b3016b7 | 1011 | goto out_unlock; |
d54853ef MS |
1012 | } |
1013 | ||
1014 | /* Store aib to get the current ETR status word. */ | |
1015 | BUG_ON(etr_stetr(&aib) != 0); | |
1016 | etr_port0.esw = etr_port1.esw = aib.esw; /* Copy status word. */ | |
1017 | now = get_clock(); | |
1018 | ||
1019 | /* | |
1020 | * Update the port information if the last stepping port change | |
1021 | * or data port change is older than 1.6 seconds. | |
1022 | */ | |
1023 | if (now >= etr_tolec + (1600000 << 12)) | |
1024 | eacr = etr_handle_update(&aib, eacr); | |
1025 | ||
1026 | /* | |
1027 | * Select ports to enable. The prefered synchronization mode is PPS. | |
1028 | * If a port can be enabled depends on a number of things: | |
1029 | * 1) The port needs to be online and uptodate. A port is not | |
1030 | * disabled just because it is not uptodate, but it is only | |
1031 | * enabled if it is uptodate. | |
1032 | * 2) The port needs to have the same mode (pps / etr). | |
1033 | * 3) The port needs to be usable -> etr_port_valid() == 1 | |
1034 | * 4) To enable the second port the clock needs to be in sync. | |
1035 | * 5) If both ports are useable and are ETR ports, the network id | |
1036 | * has to be the same. | |
1037 | * The eacr.sl bit is used to indicate etr mode vs. pps mode. | |
1038 | */ | |
1039 | if (eacr.p0 && aib.esw.psc0 == etr_lpsc_pps_mode) { | |
1040 | eacr.sl = 0; | |
1041 | eacr.e0 = 1; | |
1042 | if (!etr_mode_is_pps(etr_eacr)) | |
1043 | eacr.es = 0; | |
1044 | if (!eacr.es || !eacr.p1 || aib.esw.psc1 != etr_lpsc_pps_mode) | |
1045 | eacr.e1 = 0; | |
1046 | // FIXME: uptodate checks ? | |
1047 | else if (etr_port0_uptodate && etr_port1_uptodate) | |
1048 | eacr.e1 = 1; | |
1049 | sync_port = (etr_port0_uptodate && | |
1050 | etr_port_valid(&etr_port0, 0)) ? 0 : -1; | |
d54853ef MS |
1051 | } else if (eacr.p1 && aib.esw.psc1 == etr_lpsc_pps_mode) { |
1052 | eacr.sl = 0; | |
1053 | eacr.e0 = 0; | |
1054 | eacr.e1 = 1; | |
1055 | if (!etr_mode_is_pps(etr_eacr)) | |
1056 | eacr.es = 0; | |
1057 | sync_port = (etr_port1_uptodate && | |
1058 | etr_port_valid(&etr_port1, 1)) ? 1 : -1; | |
d54853ef MS |
1059 | } else if (eacr.p0 && aib.esw.psc0 == etr_lpsc_operational_step) { |
1060 | eacr.sl = 1; | |
1061 | eacr.e0 = 1; | |
1062 | if (!etr_mode_is_etr(etr_eacr)) | |
1063 | eacr.es = 0; | |
1064 | if (!eacr.es || !eacr.p1 || | |
1065 | aib.esw.psc1 != etr_lpsc_operational_alt) | |
1066 | eacr.e1 = 0; | |
1067 | else if (etr_port0_uptodate && etr_port1_uptodate && | |
1068 | etr_compare_network(&etr_port0, &etr_port1)) | |
1069 | eacr.e1 = 1; | |
1070 | sync_port = (etr_port0_uptodate && | |
1071 | etr_port_valid(&etr_port0, 0)) ? 0 : -1; | |
d54853ef MS |
1072 | } else if (eacr.p1 && aib.esw.psc1 == etr_lpsc_operational_step) { |
1073 | eacr.sl = 1; | |
1074 | eacr.e0 = 0; | |
1075 | eacr.e1 = 1; | |
1076 | if (!etr_mode_is_etr(etr_eacr)) | |
1077 | eacr.es = 0; | |
1078 | sync_port = (etr_port1_uptodate && | |
1079 | etr_port_valid(&etr_port1, 1)) ? 1 : -1; | |
d54853ef MS |
1080 | } else { |
1081 | /* Both ports not usable. */ | |
1082 | eacr.es = eacr.sl = 0; | |
1083 | sync_port = -1; | |
d54853ef MS |
1084 | } |
1085 | ||
1086 | /* | |
1087 | * If the clock is in sync just update the eacr and return. | |
1088 | * If there is no valid sync port wait for a port update. | |
1089 | */ | |
8283cb43 | 1090 | if (check_sync_clock() || sync_port < 0) { |
d54853ef MS |
1091 | etr_update_eacr(eacr); |
1092 | etr_set_tolec_timeout(now); | |
0b3016b7 | 1093 | goto out_unlock; |
d54853ef MS |
1094 | } |
1095 | ||
1096 | /* | |
1097 | * Prepare control register for clock syncing | |
1098 | * (reset data port bit, set sync check control. | |
1099 | */ | |
1100 | eacr.dp = 0; | |
1101 | eacr.es = 1; | |
1102 | ||
1103 | /* | |
1104 | * Update eacr and try to synchronize the clock. If the update | |
1105 | * of eacr caused a stepping port switch (or if we have to | |
1106 | * assume that a stepping port switch has occured) or the | |
1107 | * clock syncing failed, reset the sync check control bit | |
1108 | * and set up a timer to try again after 0.5 seconds | |
1109 | */ | |
1110 | etr_update_eacr(eacr); | |
1111 | if (now < etr_tolec + (1600000 << 12) || | |
750887de | 1112 | etr_sync_clock_stop(&aib, sync_port) != 0) { |
d54853ef MS |
1113 | /* Sync failed. Try again in 1/2 second. */ |
1114 | eacr.es = 0; | |
1115 | etr_update_eacr(eacr); | |
1116 | etr_set_sync_timeout(); | |
1117 | } else | |
1118 | etr_set_tolec_timeout(now); | |
0b3016b7 MS |
1119 | out_unlock: |
1120 | mutex_unlock(&etr_work_mutex); | |
d54853ef MS |
1121 | } |
1122 | ||
1123 | /* | |
1124 | * Sysfs interface functions | |
1125 | */ | |
1126 | static struct sysdev_class etr_sysclass = { | |
af5ca3f4 | 1127 | .name = "etr", |
d54853ef MS |
1128 | }; |
1129 | ||
1130 | static struct sys_device etr_port0_dev = { | |
1131 | .id = 0, | |
1132 | .cls = &etr_sysclass, | |
1133 | }; | |
1134 | ||
1135 | static struct sys_device etr_port1_dev = { | |
1136 | .id = 1, | |
1137 | .cls = &etr_sysclass, | |
1138 | }; | |
1139 | ||
1140 | /* | |
1141 | * ETR class attributes | |
1142 | */ | |
1143 | static ssize_t etr_stepping_port_show(struct sysdev_class *class, char *buf) | |
1144 | { | |
1145 | return sprintf(buf, "%i\n", etr_port0.esw.p); | |
1146 | } | |
1147 | ||
1148 | static SYSDEV_CLASS_ATTR(stepping_port, 0400, etr_stepping_port_show, NULL); | |
1149 | ||
1150 | static ssize_t etr_stepping_mode_show(struct sysdev_class *class, char *buf) | |
1151 | { | |
1152 | char *mode_str; | |
1153 | ||
1154 | if (etr_mode_is_pps(etr_eacr)) | |
1155 | mode_str = "pps"; | |
1156 | else if (etr_mode_is_etr(etr_eacr)) | |
1157 | mode_str = "etr"; | |
1158 | else | |
1159 | mode_str = "local"; | |
1160 | return sprintf(buf, "%s\n", mode_str); | |
1161 | } | |
1162 | ||
1163 | static SYSDEV_CLASS_ATTR(stepping_mode, 0400, etr_stepping_mode_show, NULL); | |
1164 | ||
1165 | /* | |
1166 | * ETR port attributes | |
1167 | */ | |
1168 | static inline struct etr_aib *etr_aib_from_dev(struct sys_device *dev) | |
1169 | { | |
1170 | if (dev == &etr_port0_dev) | |
1171 | return etr_port0_online ? &etr_port0 : NULL; | |
1172 | else | |
1173 | return etr_port1_online ? &etr_port1 : NULL; | |
1174 | } | |
1175 | ||
4a0b2b4d AK |
1176 | static ssize_t etr_online_show(struct sys_device *dev, |
1177 | struct sysdev_attribute *attr, | |
1178 | char *buf) | |
d54853ef MS |
1179 | { |
1180 | unsigned int online; | |
1181 | ||
1182 | online = (dev == &etr_port0_dev) ? etr_port0_online : etr_port1_online; | |
1183 | return sprintf(buf, "%i\n", online); | |
1184 | } | |
1185 | ||
1186 | static ssize_t etr_online_store(struct sys_device *dev, | |
4a0b2b4d AK |
1187 | struct sysdev_attribute *attr, |
1188 | const char *buf, size_t count) | |
d54853ef MS |
1189 | { |
1190 | unsigned int value; | |
1191 | ||
1192 | value = simple_strtoul(buf, NULL, 0); | |
1193 | if (value != 0 && value != 1) | |
1194 | return -EINVAL; | |
d2fec595 MS |
1195 | if (!test_bit(CLOCK_SYNC_HAS_ETR, &clock_sync_flags)) |
1196 | return -EOPNOTSUPP; | |
8283cb43 | 1197 | mutex_lock(&clock_sync_mutex); |
d54853ef MS |
1198 | if (dev == &etr_port0_dev) { |
1199 | if (etr_port0_online == value) | |
8283cb43 | 1200 | goto out; /* Nothing to do. */ |
d54853ef | 1201 | etr_port0_online = value; |
8283cb43 MS |
1202 | if (etr_port0_online && etr_port1_online) |
1203 | set_bit(CLOCK_SYNC_ETR, &clock_sync_flags); | |
1204 | else | |
1205 | clear_bit(CLOCK_SYNC_ETR, &clock_sync_flags); | |
d54853ef | 1206 | set_bit(ETR_EVENT_PORT0_CHANGE, &etr_events); |
750887de | 1207 | queue_work(time_sync_wq, &etr_work); |
d54853ef MS |
1208 | } else { |
1209 | if (etr_port1_online == value) | |
8283cb43 | 1210 | goto out; /* Nothing to do. */ |
d54853ef | 1211 | etr_port1_online = value; |
8283cb43 MS |
1212 | if (etr_port0_online && etr_port1_online) |
1213 | set_bit(CLOCK_SYNC_ETR, &clock_sync_flags); | |
1214 | else | |
1215 | clear_bit(CLOCK_SYNC_ETR, &clock_sync_flags); | |
d54853ef | 1216 | set_bit(ETR_EVENT_PORT1_CHANGE, &etr_events); |
750887de | 1217 | queue_work(time_sync_wq, &etr_work); |
d54853ef | 1218 | } |
8283cb43 MS |
1219 | out: |
1220 | mutex_unlock(&clock_sync_mutex); | |
d54853ef MS |
1221 | return count; |
1222 | } | |
1223 | ||
1224 | static SYSDEV_ATTR(online, 0600, etr_online_show, etr_online_store); | |
1225 | ||
4a0b2b4d AK |
1226 | static ssize_t etr_stepping_control_show(struct sys_device *dev, |
1227 | struct sysdev_attribute *attr, | |
1228 | char *buf) | |
d54853ef MS |
1229 | { |
1230 | return sprintf(buf, "%i\n", (dev == &etr_port0_dev) ? | |
1231 | etr_eacr.e0 : etr_eacr.e1); | |
1232 | } | |
1233 | ||
1234 | static SYSDEV_ATTR(stepping_control, 0400, etr_stepping_control_show, NULL); | |
1235 | ||
4a0b2b4d AK |
1236 | static ssize_t etr_mode_code_show(struct sys_device *dev, |
1237 | struct sysdev_attribute *attr, char *buf) | |
d54853ef MS |
1238 | { |
1239 | if (!etr_port0_online && !etr_port1_online) | |
1240 | /* Status word is not uptodate if both ports are offline. */ | |
1241 | return -ENODATA; | |
1242 | return sprintf(buf, "%i\n", (dev == &etr_port0_dev) ? | |
1243 | etr_port0.esw.psc0 : etr_port0.esw.psc1); | |
1244 | } | |
1245 | ||
1246 | static SYSDEV_ATTR(state_code, 0400, etr_mode_code_show, NULL); | |
1247 | ||
4a0b2b4d AK |
1248 | static ssize_t etr_untuned_show(struct sys_device *dev, |
1249 | struct sysdev_attribute *attr, char *buf) | |
d54853ef MS |
1250 | { |
1251 | struct etr_aib *aib = etr_aib_from_dev(dev); | |
1252 | ||
1253 | if (!aib || !aib->slsw.v1) | |
1254 | return -ENODATA; | |
1255 | return sprintf(buf, "%i\n", aib->edf1.u); | |
1256 | } | |
1257 | ||
1258 | static SYSDEV_ATTR(untuned, 0400, etr_untuned_show, NULL); | |
1259 | ||
4a0b2b4d AK |
1260 | static ssize_t etr_network_id_show(struct sys_device *dev, |
1261 | struct sysdev_attribute *attr, char *buf) | |
d54853ef MS |
1262 | { |
1263 | struct etr_aib *aib = etr_aib_from_dev(dev); | |
1264 | ||
1265 | if (!aib || !aib->slsw.v1) | |
1266 | return -ENODATA; | |
1267 | return sprintf(buf, "%i\n", aib->edf1.net_id); | |
1268 | } | |
1269 | ||
1270 | static SYSDEV_ATTR(network, 0400, etr_network_id_show, NULL); | |
1271 | ||
4a0b2b4d AK |
1272 | static ssize_t etr_id_show(struct sys_device *dev, |
1273 | struct sysdev_attribute *attr, char *buf) | |
d54853ef MS |
1274 | { |
1275 | struct etr_aib *aib = etr_aib_from_dev(dev); | |
1276 | ||
1277 | if (!aib || !aib->slsw.v1) | |
1278 | return -ENODATA; | |
1279 | return sprintf(buf, "%i\n", aib->edf1.etr_id); | |
1280 | } | |
1281 | ||
1282 | static SYSDEV_ATTR(id, 0400, etr_id_show, NULL); | |
1283 | ||
4a0b2b4d AK |
1284 | static ssize_t etr_port_number_show(struct sys_device *dev, |
1285 | struct sysdev_attribute *attr, char *buf) | |
d54853ef MS |
1286 | { |
1287 | struct etr_aib *aib = etr_aib_from_dev(dev); | |
1288 | ||
1289 | if (!aib || !aib->slsw.v1) | |
1290 | return -ENODATA; | |
1291 | return sprintf(buf, "%i\n", aib->edf1.etr_pn); | |
1292 | } | |
1293 | ||
1294 | static SYSDEV_ATTR(port, 0400, etr_port_number_show, NULL); | |
1295 | ||
4a0b2b4d AK |
1296 | static ssize_t etr_coupled_show(struct sys_device *dev, |
1297 | struct sysdev_attribute *attr, char *buf) | |
d54853ef MS |
1298 | { |
1299 | struct etr_aib *aib = etr_aib_from_dev(dev); | |
1300 | ||
1301 | if (!aib || !aib->slsw.v3) | |
1302 | return -ENODATA; | |
1303 | return sprintf(buf, "%i\n", aib->edf3.c); | |
1304 | } | |
1305 | ||
1306 | static SYSDEV_ATTR(coupled, 0400, etr_coupled_show, NULL); | |
1307 | ||
4a0b2b4d AK |
1308 | static ssize_t etr_local_time_show(struct sys_device *dev, |
1309 | struct sysdev_attribute *attr, char *buf) | |
d54853ef MS |
1310 | { |
1311 | struct etr_aib *aib = etr_aib_from_dev(dev); | |
1312 | ||
1313 | if (!aib || !aib->slsw.v3) | |
1314 | return -ENODATA; | |
1315 | return sprintf(buf, "%i\n", aib->edf3.blto); | |
1316 | } | |
1317 | ||
1318 | static SYSDEV_ATTR(local_time, 0400, etr_local_time_show, NULL); | |
1319 | ||
4a0b2b4d AK |
1320 | static ssize_t etr_utc_offset_show(struct sys_device *dev, |
1321 | struct sysdev_attribute *attr, char *buf) | |
d54853ef MS |
1322 | { |
1323 | struct etr_aib *aib = etr_aib_from_dev(dev); | |
1324 | ||
1325 | if (!aib || !aib->slsw.v3) | |
1326 | return -ENODATA; | |
1327 | return sprintf(buf, "%i\n", aib->edf3.buo); | |
1328 | } | |
1329 | ||
1330 | static SYSDEV_ATTR(utc_offset, 0400, etr_utc_offset_show, NULL); | |
1331 | ||
1332 | static struct sysdev_attribute *etr_port_attributes[] = { | |
1333 | &attr_online, | |
1334 | &attr_stepping_control, | |
1335 | &attr_state_code, | |
1336 | &attr_untuned, | |
1337 | &attr_network, | |
1338 | &attr_id, | |
1339 | &attr_port, | |
1340 | &attr_coupled, | |
1341 | &attr_local_time, | |
1342 | &attr_utc_offset, | |
1343 | NULL | |
1344 | }; | |
1345 | ||
1346 | static int __init etr_register_port(struct sys_device *dev) | |
1347 | { | |
1348 | struct sysdev_attribute **attr; | |
1349 | int rc; | |
1350 | ||
1351 | rc = sysdev_register(dev); | |
1352 | if (rc) | |
1353 | goto out; | |
1354 | for (attr = etr_port_attributes; *attr; attr++) { | |
1355 | rc = sysdev_create_file(dev, *attr); | |
1356 | if (rc) | |
1357 | goto out_unreg; | |
1358 | } | |
1359 | return 0; | |
1360 | out_unreg: | |
1361 | for (; attr >= etr_port_attributes; attr--) | |
1362 | sysdev_remove_file(dev, *attr); | |
1363 | sysdev_unregister(dev); | |
1364 | out: | |
1365 | return rc; | |
1366 | } | |
1367 | ||
1368 | static void __init etr_unregister_port(struct sys_device *dev) | |
1369 | { | |
1370 | struct sysdev_attribute **attr; | |
1371 | ||
1372 | for (attr = etr_port_attributes; *attr; attr++) | |
1373 | sysdev_remove_file(dev, *attr); | |
1374 | sysdev_unregister(dev); | |
1375 | } | |
1376 | ||
1377 | static int __init etr_init_sysfs(void) | |
1378 | { | |
1379 | int rc; | |
1380 | ||
1381 | rc = sysdev_class_register(&etr_sysclass); | |
1382 | if (rc) | |
1383 | goto out; | |
1384 | rc = sysdev_class_create_file(&etr_sysclass, &attr_stepping_port); | |
1385 | if (rc) | |
1386 | goto out_unreg_class; | |
1387 | rc = sysdev_class_create_file(&etr_sysclass, &attr_stepping_mode); | |
1388 | if (rc) | |
1389 | goto out_remove_stepping_port; | |
1390 | rc = etr_register_port(&etr_port0_dev); | |
1391 | if (rc) | |
1392 | goto out_remove_stepping_mode; | |
1393 | rc = etr_register_port(&etr_port1_dev); | |
1394 | if (rc) | |
1395 | goto out_remove_port0; | |
1396 | return 0; | |
1397 | ||
1398 | out_remove_port0: | |
1399 | etr_unregister_port(&etr_port0_dev); | |
1400 | out_remove_stepping_mode: | |
1401 | sysdev_class_remove_file(&etr_sysclass, &attr_stepping_mode); | |
1402 | out_remove_stepping_port: | |
1403 | sysdev_class_remove_file(&etr_sysclass, &attr_stepping_port); | |
1404 | out_unreg_class: | |
1405 | sysdev_class_unregister(&etr_sysclass); | |
1406 | out: | |
1407 | return rc; | |
1da177e4 LT |
1408 | } |
1409 | ||
d54853ef | 1410 | device_initcall(etr_init_sysfs); |
d2fec595 MS |
1411 | |
1412 | /* | |
1413 | * Server Time Protocol (STP) code. | |
1414 | */ | |
1415 | static int stp_online; | |
1416 | static struct stp_sstpi stp_info; | |
1417 | static void *stp_page; | |
1418 | ||
1419 | static void stp_work_fn(struct work_struct *work); | |
0b3016b7 | 1420 | static DEFINE_MUTEX(stp_work_mutex); |
d2fec595 | 1421 | static DECLARE_WORK(stp_work, stp_work_fn); |
04362301 | 1422 | static struct timer_list stp_timer; |
d2fec595 MS |
1423 | |
1424 | static int __init early_parse_stp(char *p) | |
1425 | { | |
1426 | if (strncmp(p, "off", 3) == 0) | |
1427 | stp_online = 0; | |
1428 | else if (strncmp(p, "on", 2) == 0) | |
1429 | stp_online = 1; | |
1430 | return 0; | |
1431 | } | |
1432 | early_param("stp", early_parse_stp); | |
1433 | ||
1434 | /* | |
1435 | * Reset STP attachment. | |
1436 | */ | |
8f847003 | 1437 | static void __init stp_reset(void) |
d2fec595 MS |
1438 | { |
1439 | int rc; | |
1440 | ||
d7d1104f | 1441 | stp_page = (void *) get_zeroed_page(GFP_ATOMIC); |
d2fec595 | 1442 | rc = chsc_sstpc(stp_page, STP_OP_CTRL, 0x0000); |
4a672cfa | 1443 | if (rc == 0) |
d2fec595 MS |
1444 | set_bit(CLOCK_SYNC_HAS_STP, &clock_sync_flags); |
1445 | else if (stp_online) { | |
feab6501 MS |
1446 | pr_warning("The real or virtual hardware system does " |
1447 | "not provide an STP interface\n"); | |
d7d1104f | 1448 | free_page((unsigned long) stp_page); |
d2fec595 MS |
1449 | stp_page = NULL; |
1450 | stp_online = 0; | |
1451 | } | |
1452 | } | |
1453 | ||
04362301 MS |
1454 | static void stp_timeout(unsigned long dummy) |
1455 | { | |
1456 | queue_work(time_sync_wq, &stp_work); | |
1457 | } | |
1458 | ||
d2fec595 MS |
1459 | static int __init stp_init(void) |
1460 | { | |
750887de HC |
1461 | if (!test_bit(CLOCK_SYNC_HAS_STP, &clock_sync_flags)) |
1462 | return 0; | |
04362301 | 1463 | setup_timer(&stp_timer, stp_timeout, 0UL); |
750887de HC |
1464 | time_init_wq(); |
1465 | if (!stp_online) | |
1466 | return 0; | |
1467 | queue_work(time_sync_wq, &stp_work); | |
d2fec595 MS |
1468 | return 0; |
1469 | } | |
1470 | ||
1471 | arch_initcall(stp_init); | |
1472 | ||
1473 | /* | |
1474 | * STP timing alert. There are three causes: | |
1475 | * 1) timing status change | |
1476 | * 2) link availability change | |
1477 | * 3) time control parameter change | |
1478 | * In all three cases we are only interested in the clock source state. | |
1479 | * If a STP clock source is now available use it. | |
1480 | */ | |
1481 | static void stp_timing_alert(struct stp_irq_parm *intparm) | |
1482 | { | |
1483 | if (intparm->tsc || intparm->lac || intparm->tcpc) | |
750887de | 1484 | queue_work(time_sync_wq, &stp_work); |
d2fec595 MS |
1485 | } |
1486 | ||
1487 | /* | |
1488 | * STP sync check machine check. This is called when the timing state | |
1489 | * changes from the synchronized state to the unsynchronized state. | |
1490 | * After a STP sync check the clock is not in sync. The machine check | |
1491 | * is broadcasted to all cpus at the same time. | |
1492 | */ | |
1493 | void stp_sync_check(void) | |
1494 | { | |
d2fec595 | 1495 | disable_sync_clock(NULL); |
750887de | 1496 | queue_work(time_sync_wq, &stp_work); |
d2fec595 MS |
1497 | } |
1498 | ||
1499 | /* | |
1500 | * STP island condition machine check. This is called when an attached | |
1501 | * server attempts to communicate over an STP link and the servers | |
1502 | * have matching CTN ids and have a valid stratum-1 configuration | |
1503 | * but the configurations do not match. | |
1504 | */ | |
1505 | void stp_island_check(void) | |
1506 | { | |
d2fec595 | 1507 | disable_sync_clock(NULL); |
750887de | 1508 | queue_work(time_sync_wq, &stp_work); |
d2fec595 MS |
1509 | } |
1510 | ||
750887de HC |
1511 | |
1512 | static int stp_sync_clock(void *data) | |
d2fec595 | 1513 | { |
750887de | 1514 | static int first; |
d2fec595 | 1515 | unsigned long long old_clock, delta; |
750887de | 1516 | struct clock_sync_data *stp_sync; |
d2fec595 MS |
1517 | int rc; |
1518 | ||
750887de | 1519 | stp_sync = data; |
d2fec595 | 1520 | |
750887de HC |
1521 | if (xchg(&first, 1) == 1) { |
1522 | /* Slave */ | |
1523 | clock_sync_cpu(stp_sync); | |
1524 | return 0; | |
1525 | } | |
d2fec595 | 1526 | |
750887de HC |
1527 | /* Wait until all other cpus entered the sync function. */ |
1528 | while (atomic_read(&stp_sync->cpus) != 0) | |
1529 | cpu_relax(); | |
d2fec595 | 1530 | |
d2fec595 MS |
1531 | enable_sync_clock(); |
1532 | ||
d2fec595 MS |
1533 | rc = 0; |
1534 | if (stp_info.todoff[0] || stp_info.todoff[1] || | |
1535 | stp_info.todoff[2] || stp_info.todoff[3] || | |
1536 | stp_info.tmd != 2) { | |
1537 | old_clock = get_clock(); | |
1538 | rc = chsc_sstpc(stp_page, STP_OP_SYNC, 0); | |
1539 | if (rc == 0) { | |
1540 | delta = adjust_time(old_clock, get_clock(), 0); | |
1541 | fixup_clock_comparator(delta); | |
1542 | rc = chsc_sstpi(stp_page, &stp_info, | |
1543 | sizeof(struct stp_sstpi)); | |
1544 | if (rc == 0 && stp_info.tmd != 2) | |
1545 | rc = -EAGAIN; | |
1546 | } | |
1547 | } | |
1548 | if (rc) { | |
1549 | disable_sync_clock(NULL); | |
750887de | 1550 | stp_sync->in_sync = -EAGAIN; |
d2fec595 | 1551 | } else |
750887de HC |
1552 | stp_sync->in_sync = 1; |
1553 | xchg(&first, 0); | |
1554 | return 0; | |
1555 | } | |
d2fec595 | 1556 | |
750887de HC |
1557 | /* |
1558 | * STP work. Check for the STP state and take over the clock | |
1559 | * synchronization if the STP clock source is usable. | |
1560 | */ | |
1561 | static void stp_work_fn(struct work_struct *work) | |
1562 | { | |
1563 | struct clock_sync_data stp_sync; | |
1564 | int rc; | |
1565 | ||
0b3016b7 MS |
1566 | /* prevent multiple execution. */ |
1567 | mutex_lock(&stp_work_mutex); | |
1568 | ||
750887de HC |
1569 | if (!stp_online) { |
1570 | chsc_sstpc(stp_page, STP_OP_CTRL, 0x0000); | |
04362301 | 1571 | del_timer_sync(&stp_timer); |
0b3016b7 | 1572 | goto out_unlock; |
750887de HC |
1573 | } |
1574 | ||
1575 | rc = chsc_sstpc(stp_page, STP_OP_CTRL, 0xb0e0); | |
1576 | if (rc) | |
0b3016b7 | 1577 | goto out_unlock; |
750887de HC |
1578 | |
1579 | rc = chsc_sstpi(stp_page, &stp_info, sizeof(struct stp_sstpi)); | |
1580 | if (rc || stp_info.c == 0) | |
0b3016b7 | 1581 | goto out_unlock; |
750887de | 1582 | |
8283cb43 MS |
1583 | /* Skip synchronization if the clock is already in sync. */ |
1584 | if (check_sync_clock()) | |
1585 | goto out_unlock; | |
1586 | ||
750887de HC |
1587 | memset(&stp_sync, 0, sizeof(stp_sync)); |
1588 | get_online_cpus(); | |
1589 | atomic_set(&stp_sync.cpus, num_online_cpus() - 1); | |
1590 | stop_machine(stp_sync_clock, &stp_sync, &cpu_online_map); | |
1591 | put_online_cpus(); | |
0b3016b7 | 1592 | |
04362301 MS |
1593 | if (!check_sync_clock()) |
1594 | /* | |
1595 | * There is a usable clock but the synchonization failed. | |
1596 | * Retry after a second. | |
1597 | */ | |
1598 | mod_timer(&stp_timer, jiffies + HZ); | |
1599 | ||
0b3016b7 MS |
1600 | out_unlock: |
1601 | mutex_unlock(&stp_work_mutex); | |
d2fec595 MS |
1602 | } |
1603 | ||
1604 | /* | |
1605 | * STP class sysfs interface functions | |
1606 | */ | |
1607 | static struct sysdev_class stp_sysclass = { | |
1608 | .name = "stp", | |
1609 | }; | |
1610 | ||
1611 | static ssize_t stp_ctn_id_show(struct sysdev_class *class, char *buf) | |
1612 | { | |
1613 | if (!stp_online) | |
1614 | return -ENODATA; | |
1615 | return sprintf(buf, "%016llx\n", | |
1616 | *(unsigned long long *) stp_info.ctnid); | |
1617 | } | |
1618 | ||
1619 | static SYSDEV_CLASS_ATTR(ctn_id, 0400, stp_ctn_id_show, NULL); | |
1620 | ||
1621 | static ssize_t stp_ctn_type_show(struct sysdev_class *class, char *buf) | |
1622 | { | |
1623 | if (!stp_online) | |
1624 | return -ENODATA; | |
1625 | return sprintf(buf, "%i\n", stp_info.ctn); | |
1626 | } | |
1627 | ||
1628 | static SYSDEV_CLASS_ATTR(ctn_type, 0400, stp_ctn_type_show, NULL); | |
1629 | ||
1630 | static ssize_t stp_dst_offset_show(struct sysdev_class *class, char *buf) | |
1631 | { | |
1632 | if (!stp_online || !(stp_info.vbits & 0x2000)) | |
1633 | return -ENODATA; | |
1634 | return sprintf(buf, "%i\n", (int)(s16) stp_info.dsto); | |
1635 | } | |
1636 | ||
1637 | static SYSDEV_CLASS_ATTR(dst_offset, 0400, stp_dst_offset_show, NULL); | |
1638 | ||
1639 | static ssize_t stp_leap_seconds_show(struct sysdev_class *class, char *buf) | |
1640 | { | |
1641 | if (!stp_online || !(stp_info.vbits & 0x8000)) | |
1642 | return -ENODATA; | |
1643 | return sprintf(buf, "%i\n", (int)(s16) stp_info.leaps); | |
1644 | } | |
1645 | ||
1646 | static SYSDEV_CLASS_ATTR(leap_seconds, 0400, stp_leap_seconds_show, NULL); | |
1647 | ||
1648 | static ssize_t stp_stratum_show(struct sysdev_class *class, char *buf) | |
1649 | { | |
1650 | if (!stp_online) | |
1651 | return -ENODATA; | |
1652 | return sprintf(buf, "%i\n", (int)(s16) stp_info.stratum); | |
1653 | } | |
1654 | ||
1655 | static SYSDEV_CLASS_ATTR(stratum, 0400, stp_stratum_show, NULL); | |
1656 | ||
1657 | static ssize_t stp_time_offset_show(struct sysdev_class *class, char *buf) | |
1658 | { | |
1659 | if (!stp_online || !(stp_info.vbits & 0x0800)) | |
1660 | return -ENODATA; | |
1661 | return sprintf(buf, "%i\n", (int) stp_info.tto); | |
1662 | } | |
1663 | ||
1664 | static SYSDEV_CLASS_ATTR(time_offset, 0400, stp_time_offset_show, NULL); | |
1665 | ||
1666 | static ssize_t stp_time_zone_offset_show(struct sysdev_class *class, char *buf) | |
1667 | { | |
1668 | if (!stp_online || !(stp_info.vbits & 0x4000)) | |
1669 | return -ENODATA; | |
1670 | return sprintf(buf, "%i\n", (int)(s16) stp_info.tzo); | |
1671 | } | |
1672 | ||
1673 | static SYSDEV_CLASS_ATTR(time_zone_offset, 0400, | |
1674 | stp_time_zone_offset_show, NULL); | |
1675 | ||
1676 | static ssize_t stp_timing_mode_show(struct sysdev_class *class, char *buf) | |
1677 | { | |
1678 | if (!stp_online) | |
1679 | return -ENODATA; | |
1680 | return sprintf(buf, "%i\n", stp_info.tmd); | |
1681 | } | |
1682 | ||
1683 | static SYSDEV_CLASS_ATTR(timing_mode, 0400, stp_timing_mode_show, NULL); | |
1684 | ||
1685 | static ssize_t stp_timing_state_show(struct sysdev_class *class, char *buf) | |
1686 | { | |
1687 | if (!stp_online) | |
1688 | return -ENODATA; | |
1689 | return sprintf(buf, "%i\n", stp_info.tst); | |
1690 | } | |
1691 | ||
1692 | static SYSDEV_CLASS_ATTR(timing_state, 0400, stp_timing_state_show, NULL); | |
1693 | ||
1694 | static ssize_t stp_online_show(struct sysdev_class *class, char *buf) | |
1695 | { | |
1696 | return sprintf(buf, "%i\n", stp_online); | |
1697 | } | |
1698 | ||
1699 | static ssize_t stp_online_store(struct sysdev_class *class, | |
1700 | const char *buf, size_t count) | |
1701 | { | |
1702 | unsigned int value; | |
1703 | ||
1704 | value = simple_strtoul(buf, NULL, 0); | |
1705 | if (value != 0 && value != 1) | |
1706 | return -EINVAL; | |
1707 | if (!test_bit(CLOCK_SYNC_HAS_STP, &clock_sync_flags)) | |
1708 | return -EOPNOTSUPP; | |
8283cb43 | 1709 | mutex_lock(&clock_sync_mutex); |
d2fec595 | 1710 | stp_online = value; |
8283cb43 MS |
1711 | if (stp_online) |
1712 | set_bit(CLOCK_SYNC_STP, &clock_sync_flags); | |
1713 | else | |
1714 | clear_bit(CLOCK_SYNC_STP, &clock_sync_flags); | |
750887de | 1715 | queue_work(time_sync_wq, &stp_work); |
8283cb43 | 1716 | mutex_unlock(&clock_sync_mutex); |
d2fec595 MS |
1717 | return count; |
1718 | } | |
1719 | ||
1720 | /* | |
1721 | * Can't use SYSDEV_CLASS_ATTR because the attribute should be named | |
1722 | * stp/online but attr_online already exists in this file .. | |
1723 | */ | |
1724 | static struct sysdev_class_attribute attr_stp_online = { | |
1725 | .attr = { .name = "online", .mode = 0600 }, | |
1726 | .show = stp_online_show, | |
1727 | .store = stp_online_store, | |
1728 | }; | |
1729 | ||
1730 | static struct sysdev_class_attribute *stp_attributes[] = { | |
1731 | &attr_ctn_id, | |
1732 | &attr_ctn_type, | |
1733 | &attr_dst_offset, | |
1734 | &attr_leap_seconds, | |
1735 | &attr_stp_online, | |
1736 | &attr_stratum, | |
1737 | &attr_time_offset, | |
1738 | &attr_time_zone_offset, | |
1739 | &attr_timing_mode, | |
1740 | &attr_timing_state, | |
1741 | NULL | |
1742 | }; | |
1743 | ||
1744 | static int __init stp_init_sysfs(void) | |
1745 | { | |
1746 | struct sysdev_class_attribute **attr; | |
1747 | int rc; | |
1748 | ||
1749 | rc = sysdev_class_register(&stp_sysclass); | |
1750 | if (rc) | |
1751 | goto out; | |
1752 | for (attr = stp_attributes; *attr; attr++) { | |
1753 | rc = sysdev_class_create_file(&stp_sysclass, *attr); | |
1754 | if (rc) | |
1755 | goto out_unreg; | |
1756 | } | |
1757 | return 0; | |
1758 | out_unreg: | |
1759 | for (; attr >= stp_attributes; attr--) | |
1760 | sysdev_class_remove_file(&stp_sysclass, *attr); | |
1761 | sysdev_class_unregister(&stp_sysclass); | |
1762 | out: | |
1763 | return rc; | |
1764 | } | |
1765 | ||
1766 | device_initcall(stp_init_sysfs); |