s390/smp: perform initial CPU reset also for SMT siblings
[linux-2.6-block.git] / arch / s390 / kernel / smp.c
CommitLineData
b2441318 1// SPDX-License-Identifier: GPL-2.0
1da177e4 2/*
8b646bd7 3 * SMP related functions
1da177e4 4 *
a53c8fab 5 * Copyright IBM Corp. 1999, 2012
8b646bd7
MS
6 * Author(s): Denis Joseph Barrow,
7 * Martin Schwidefsky <schwidefsky@de.ibm.com>,
8 * Heiko Carstens <heiko.carstens@de.ibm.com>,
1da177e4 9 *
39ce010d 10 * based on other smp stuff by
1da177e4
LT
11 * (c) 1995 Alan Cox, CymruNET Ltd <alan@cymru.net>
12 * (c) 1998 Ingo Molnar
13 *
8b646bd7
MS
14 * The code outside of smp.c uses logical cpu numbers, only smp.c does
15 * the translation of logical to physical cpu ids. All new code that
16 * operates on physical cpu numbers needs to go into smp.c.
1da177e4
LT
17 */
18
395d31d4
MS
19#define KMSG_COMPONENT "cpu"
20#define pr_fmt(fmt) KMSG_COMPONENT ": " fmt
21
f230886b 22#include <linux/workqueue.h>
57c8a661 23#include <linux/memblock.h>
3994a52b 24#include <linux/export.h>
1da177e4 25#include <linux/init.h>
1da177e4 26#include <linux/mm.h>
4e950f6f 27#include <linux/err.h>
1da177e4
LT
28#include <linux/spinlock.h>
29#include <linux/kernel_stat.h>
1da177e4 30#include <linux/delay.h>
1da177e4 31#include <linux/interrupt.h>
3324e60a 32#include <linux/irqflags.h>
1da177e4 33#include <linux/cpu.h>
5a0e3ad6 34#include <linux/slab.h>
ef8bd77f 35#include <linux/sched/hotplug.h>
68db0cf1 36#include <linux/sched/task_stack.h>
60a0c68d 37#include <linux/crash_dump.h>
00a8f886 38#include <linux/kprobes.h>
cbb870c8 39#include <asm/asm-offsets.h>
1ec2772e 40#include <asm/diag.h>
1e3cab2f
HC
41#include <asm/switch_to.h>
42#include <asm/facility.h>
46b05d26 43#include <asm/ipl.h>
2b67fc46 44#include <asm/setup.h>
1da177e4 45#include <asm/irq.h>
1da177e4 46#include <asm/tlbflush.h>
27f6b416 47#include <asm/vtimer.h>
411ed322 48#include <asm/lowcore.h>
08d07968 49#include <asm/sclp.h>
3ab121ab 50#include <asm/debug.h>
4857d4bb 51#include <asm/os_info.h>
a9ae32c3 52#include <asm/sigp.h>
b5f87f15 53#include <asm/idle.h>
916cda1a 54#include <asm/nmi.h>
78c98f90 55#include <asm/stacktrace.h>
38389ec8 56#include <asm/topology.h>
80f06306 57#include <asm/vdso.h>
a806170e 58#include "entry.h"
1da177e4 59
8b646bd7
MS
60enum {
61 ec_schedule = 0,
8b646bd7
MS
62 ec_call_function_single,
63 ec_stop_cpu,
11886c19 64 ec_mcck_pending,
8b646bd7 65};
08d07968 66
8b646bd7 67enum {
08d07968
HC
68 CPU_STATE_STANDBY,
69 CPU_STATE_CONFIGURED,
70};
71
2f859d0d
HC
72static DEFINE_PER_CPU(struct cpu *, cpu_device);
73
8b646bd7 74struct pcpu {
c667aeac 75 struct lowcore *lowcore; /* lowcore page(s) for the cpu */
8b646bd7 76 unsigned long ec_mask; /* bit mask for ec_xxx functions */
3dbc78d3 77 unsigned long ec_clk; /* sigp timestamp for ec_xxx */
2f859d0d
HC
78 signed char state; /* physical cpu state */
79 signed char polarization; /* physical polarization */
8b646bd7
MS
80 u16 address; /* physical cpu address */
81};
82
d08d9430 83static u8 boot_core_type;
8b646bd7
MS
84static struct pcpu pcpu_devices[NR_CPUS];
85
10ad34bc
MS
86unsigned int smp_cpu_mt_shift;
87EXPORT_SYMBOL(smp_cpu_mt_shift);
88
89unsigned int smp_cpu_mtid;
90EXPORT_SYMBOL(smp_cpu_mtid);
91
1a36a39e
MS
92#ifdef CONFIG_CRASH_DUMP
93__vector128 __initdata boot_cpu_vector_save_area[__NUM_VXRS];
94#endif
95
10ad34bc
MS
96static unsigned int smp_max_threads __initdata = -1U;
97
98static int __init early_nosmt(char *s)
99{
100 smp_max_threads = 1;
101 return 0;
102}
103early_param("nosmt", early_nosmt);
104
105static int __init early_smt(char *s)
106{
107 get_option(&s, &smp_max_threads);
108 return 0;
109}
110early_param("smt", early_smt);
111
50ab9a9a
HC
112/*
113 * The smp_cpu_state_mutex must be held when changing the state or polarization
114 * member of a pcpu data structure within the pcpu_devices arreay.
115 */
dbd70fb4 116DEFINE_MUTEX(smp_cpu_state_mutex);
08d07968 117
8b646bd7
MS
118/*
119 * Signal processor helper functions.
120 */
1a36a39e 121static inline int __pcpu_sigp_relax(u16 addr, u8 order, unsigned long parm)
5c0b912e 122{
8b646bd7 123 int cc;
5c0b912e 124
8b646bd7 125 while (1) {
c5e3acd6 126 cc = __pcpu_sigp(addr, order, parm, NULL);
a9ae32c3 127 if (cc != SIGP_CC_BUSY)
8b646bd7
MS
128 return cc;
129 cpu_relax();
5c0b912e 130 }
5c0b912e
HC
131}
132
8b646bd7 133static int pcpu_sigp_retry(struct pcpu *pcpu, u8 order, u32 parm)
a93b8ec1 134{
8b646bd7
MS
135 int cc, retry;
136
137 for (retry = 0; ; retry++) {
c5e3acd6 138 cc = __pcpu_sigp(pcpu->address, order, parm, NULL);
a9ae32c3 139 if (cc != SIGP_CC_BUSY)
8b646bd7
MS
140 break;
141 if (retry >= 3)
142 udelay(10);
143 }
144 return cc;
145}
146
147static inline int pcpu_stopped(struct pcpu *pcpu)
148{
3f649ab7 149 u32 status;
c5e3acd6 150
a9ae32c3 151 if (__pcpu_sigp(pcpu->address, SIGP_SENSE,
c5e3acd6 152 0, &status) != SIGP_CC_STATUS_STORED)
8b646bd7 153 return 0;
c5e3acd6 154 return !!(status & (SIGP_STATUS_CHECK_STOP|SIGP_STATUS_STOPPED));
8b646bd7
MS
155}
156
157static inline int pcpu_running(struct pcpu *pcpu)
a93b8ec1 158{
a9ae32c3 159 if (__pcpu_sigp(pcpu->address, SIGP_SENSE_RUNNING,
c5e3acd6 160 0, NULL) != SIGP_CC_STATUS_STORED)
8b646bd7 161 return 1;
524b24ad
HC
162 /* Status stored condition code is equivalent to cpu not running. */
163 return 0;
a93b8ec1
HC
164}
165
1943f53c 166/*
8b646bd7 167 * Find struct pcpu by cpu address.
1943f53c 168 */
10ad34bc 169static struct pcpu *pcpu_find_address(const struct cpumask *mask, u16 address)
1943f53c
MH
170{
171 int cpu;
172
8b646bd7
MS
173 for_each_cpu(cpu, mask)
174 if (pcpu_devices[cpu].address == address)
175 return pcpu_devices + cpu;
176 return NULL;
177}
178
179static void pcpu_ec_call(struct pcpu *pcpu, int ec_bit)
180{
181 int order;
182
dea24190
HC
183 if (test_and_set_bit(ec_bit, &pcpu->ec_mask))
184 return;
185 order = pcpu_running(pcpu) ? SIGP_EXTERNAL_CALL : SIGP_EMERGENCY_SIGNAL;
3dbc78d3 186 pcpu->ec_clk = get_tod_clock_fast();
8b646bd7
MS
187 pcpu_sigp_retry(pcpu, order, 0);
188}
189
e2741f17 190static int pcpu_alloc_lowcore(struct pcpu *pcpu, int cpu)
8b646bd7 191{
ce3dc447 192 unsigned long async_stack, nodat_stack;
c667aeac 193 struct lowcore *lc;
8b646bd7
MS
194
195 if (pcpu != &pcpu_devices[0]) {
c667aeac 196 pcpu->lowcore = (struct lowcore *)
8b646bd7 197 __get_free_pages(GFP_KERNEL | GFP_DMA, LC_ORDER);
32ce55a6 198 nodat_stack = __get_free_pages(GFP_KERNEL, THREAD_SIZE_ORDER);
ce3dc447 199 if (!pcpu->lowcore || !nodat_stack)
8b646bd7 200 goto out;
2f859d0d 201 } else {
ce3dc447 202 nodat_stack = pcpu->lowcore->nodat_stack - STACK_INIT_OFFSET;
1943f53c 203 }
ce3dc447
MS
204 async_stack = stack_alloc();
205 if (!async_stack)
206 goto out;
8b646bd7
MS
207 lc = pcpu->lowcore;
208 memcpy(lc, &S390_lowcore, 512);
209 memset((char *) lc + 512, 0, sizeof(*lc) - 512);
ce3dc447
MS
210 lc->async_stack = async_stack + STACK_INIT_OFFSET;
211 lc->nodat_stack = nodat_stack + STACK_INIT_OFFSET;
8b646bd7 212 lc->cpu_nr = cpu;
6c8cd5bb 213 lc->spinlock_lockval = arch_spin_lockval(cpu);
b96f7d88 214 lc->spinlock_index = 0;
f19fbd5e 215 lc->br_r1_trampoline = 0x07f1; /* br %r1 */
0b38b5e1
SS
216 lc->return_lpswe = gen_lpswe(__LC_RETURN_PSW);
217 lc->return_mcck_lpswe = gen_lpswe(__LC_RETURN_MCCK_PSW);
6c81511c 218 if (nmi_alloc_per_cpu(lc))
ce3dc447 219 goto out_async;
8b646bd7 220 lowcore_ptr[cpu] = lc;
a9ae32c3 221 pcpu_sigp_retry(pcpu, SIGP_SET_PREFIX, (u32)(unsigned long) lc);
8b646bd7 222 return 0;
6c81511c 223
ce3dc447
MS
224out_async:
225 stack_free(async_stack);
8b646bd7
MS
226out:
227 if (pcpu != &pcpu_devices[0]) {
32ce55a6 228 free_pages(nodat_stack, THREAD_SIZE_ORDER);
8b646bd7
MS
229 free_pages((unsigned long) pcpu->lowcore, LC_ORDER);
230 }
231 return -ENOMEM;
1943f53c
MH
232}
233
8b646bd7 234static void pcpu_free_lowcore(struct pcpu *pcpu)
2c2df118 235{
ce3dc447
MS
236 unsigned long async_stack, nodat_stack, lowcore;
237
238 nodat_stack = pcpu->lowcore->nodat_stack - STACK_INIT_OFFSET;
239 async_stack = pcpu->lowcore->async_stack - STACK_INIT_OFFSET;
240 lowcore = (unsigned long) pcpu->lowcore;
241
a9ae32c3 242 pcpu_sigp_retry(pcpu, SIGP_SET_PREFIX, 0);
8b646bd7 243 lowcore_ptr[pcpu - pcpu_devices] = NULL;
6c81511c 244 nmi_free_per_cpu(pcpu->lowcore);
ce3dc447 245 stack_free(async_stack);
2f859d0d
HC
246 if (pcpu == &pcpu_devices[0])
247 return;
32ce55a6 248 free_pages(nodat_stack, THREAD_SIZE_ORDER);
ce3dc447 249 free_pages(lowcore, LC_ORDER);
8b646bd7
MS
250}
251
252static void pcpu_prepare_secondary(struct pcpu *pcpu, int cpu)
253{
c667aeac 254 struct lowcore *lc = pcpu->lowcore;
8b646bd7 255
64f31d58 256 cpumask_set_cpu(cpu, &init_mm.context.cpu_attach_mask);
1b948d6c 257 cpumask_set_cpu(cpu, mm_cpumask(&init_mm));
8b646bd7 258 lc->cpu_nr = cpu;
6c8cd5bb 259 lc->spinlock_lockval = arch_spin_lockval(cpu);
b96f7d88 260 lc->spinlock_index = 0;
8b646bd7
MS
261 lc->percpu_offset = __per_cpu_offset[cpu];
262 lc->kernel_asce = S390_lowcore.kernel_asce;
0290c9e3 263 lc->user_asce = s390_invalid_asce;
8b646bd7 264 lc->machine_flags = S390_lowcore.machine_flags;
152e9b86
MS
265 lc->user_timer = lc->system_timer =
266 lc->steal_timer = lc->avg_steal_timer = 0;
8b646bd7 267 __ctl_store(lc->cregs_save_area, 0, 15);
a2308c11 268 lc->cregs_save_area[1] = lc->kernel_asce;
87d59863 269 lc->cregs_save_area[7] = lc->user_asce;
8b646bd7
MS
270 save_access_regs((unsigned int *) lc->access_regs_save_area);
271 memcpy(lc->stfle_fac_list, S390_lowcore.stfle_fac_list,
cf148998
MS
272 sizeof(lc->stfle_fac_list));
273 memcpy(lc->alt_stfle_fac_list, S390_lowcore.alt_stfle_fac_list,
274 sizeof(lc->alt_stfle_fac_list));
b96f7d88 275 arch_spin_lock_setup(cpu);
8b646bd7
MS
276}
277
278static void pcpu_attach_task(struct pcpu *pcpu, struct task_struct *tsk)
279{
c667aeac 280 struct lowcore *lc = pcpu->lowcore;
8b646bd7 281
dc7ee00d
MS
282 lc->kernel_stack = (unsigned long) task_stack_page(tsk)
283 + THREAD_SIZE - STACK_FRAME_OVERHEAD - sizeof(struct pt_regs);
8b646bd7 284 lc->current_task = (unsigned long) tsk;
e22cf8ca
CB
285 lc->lpp = LPP_MAGIC;
286 lc->current_pid = tsk->pid;
90c53e65 287 lc->user_timer = tsk->thread.user_timer;
b7662eef 288 lc->guest_timer = tsk->thread.guest_timer;
90c53e65 289 lc->system_timer = tsk->thread.system_timer;
b7662eef
CB
290 lc->hardirq_timer = tsk->thread.hardirq_timer;
291 lc->softirq_timer = tsk->thread.softirq_timer;
8b646bd7
MS
292 lc->steal_timer = 0;
293}
294
295static void pcpu_start_fn(struct pcpu *pcpu, void (*func)(void *), void *data)
296{
c667aeac 297 struct lowcore *lc = pcpu->lowcore;
8b646bd7 298
ce3dc447 299 lc->restart_stack = lc->nodat_stack;
8b646bd7
MS
300 lc->restart_fn = (unsigned long) func;
301 lc->restart_data = (unsigned long) data;
302 lc->restart_source = -1UL;
a9ae32c3 303 pcpu_sigp_retry(pcpu, SIGP_RESTART, 0);
8b646bd7
MS
304}
305
306/*
307 * Call function via PSW restart on pcpu and stop the current cpu.
308 */
ce3dc447
MS
309static void __pcpu_delegate(void (*func)(void*), void *data)
310{
311 func(data); /* should not return */
312}
313
ac1256f8
VG
314static void __no_sanitize_address pcpu_delegate(struct pcpu *pcpu,
315 void (*func)(void *),
316 void *data, unsigned long stack)
8b646bd7 317{
c667aeac 318 struct lowcore *lc = lowcore_ptr[pcpu - pcpu_devices];
fbe76568 319 unsigned long source_cpu = stap();
8b646bd7 320
ce3dc447 321 __load_psw_mask(PSW_KERNEL_BITS | PSW_MASK_DAT);
fbe76568 322 if (pcpu->address == source_cpu)
ce3dc447 323 CALL_ON_STACK(__pcpu_delegate, stack, 2, func, data);
8b646bd7 324 /* Stop target cpu (if func returns this stops the current cpu). */
a9ae32c3 325 pcpu_sigp_retry(pcpu, SIGP_STOP, 0);
8b646bd7 326 /* Restart func on the target cpu and stop the current cpu. */
fbe76568
HC
327 mem_assign_absolute(lc->restart_stack, stack);
328 mem_assign_absolute(lc->restart_fn, (unsigned long) func);
329 mem_assign_absolute(lc->restart_data, (unsigned long) data);
330 mem_assign_absolute(lc->restart_source, source_cpu);
d768bd89 331 __bpon();
8b646bd7 332 asm volatile(
eb546195 333 "0: sigp 0,%0,%2 # sigp restart to target cpu\n"
8b646bd7 334 " brc 2,0b # busy, try again\n"
eb546195 335 "1: sigp 0,%1,%3 # sigp stop to current cpu\n"
8b646bd7 336 " brc 2,1b # busy, try again\n"
fbe76568 337 : : "d" (pcpu->address), "d" (source_cpu),
eb546195
HC
338 "K" (SIGP_RESTART), "K" (SIGP_STOP)
339 : "0", "1", "cc");
8b646bd7
MS
340 for (;;) ;
341}
342
10ad34bc
MS
343/*
344 * Enable additional logical cpus for multi-threading.
345 */
346static int pcpu_set_smt(unsigned int mtid)
347{
10ad34bc
MS
348 int cc;
349
350 if (smp_cpu_mtid == mtid)
351 return 0;
80a60f6e 352 cc = __pcpu_sigp(0, SIGP_SET_MULTI_THREADING, mtid, NULL);
10ad34bc
MS
353 if (cc == 0) {
354 smp_cpu_mtid = mtid;
355 smp_cpu_mt_shift = 0;
356 while (smp_cpu_mtid >= (1U << smp_cpu_mt_shift))
357 smp_cpu_mt_shift++;
358 pcpu_devices[0].address = stap();
359 }
360 return cc;
361}
362
8b646bd7
MS
363/*
364 * Call function on an online CPU.
365 */
366void smp_call_online_cpu(void (*func)(void *), void *data)
367{
368 struct pcpu *pcpu;
369
370 /* Use the current cpu if it is online. */
371 pcpu = pcpu_find_address(cpu_online_mask, stap());
372 if (!pcpu)
373 /* Use the first online cpu. */
374 pcpu = pcpu_devices + cpumask_first(cpu_online_mask);
375 pcpu_delegate(pcpu, func, data, (unsigned long) restart_stack);
376}
377
378/*
379 * Call function on the ipl CPU.
380 */
381void smp_call_ipl_cpu(void (*func)(void *), void *data)
382{
60f1bf29
DH
383 struct lowcore *lc = pcpu_devices->lowcore;
384
385 if (pcpu_devices[0].address == stap())
386 lc = &S390_lowcore;
387
c6da39f2 388 pcpu_delegate(&pcpu_devices[0], func, data,
60f1bf29 389 lc->nodat_stack);
8b646bd7
MS
390}
391
392int smp_find_processor_id(u16 address)
393{
394 int cpu;
395
396 for_each_present_cpu(cpu)
397 if (pcpu_devices[cpu].address == address)
398 return cpu;
399 return -1;
2c2df118
HC
400}
401
11886c19
SS
402void schedule_mcck_handler(void)
403{
404 pcpu_ec_call(pcpu_devices + smp_processor_id(), ec_mcck_pending);
405}
406
8ebf6da9 407bool notrace arch_vcpu_is_preempted(int cpu)
85ac7ca5 408{
760928c0
CB
409 if (test_cpu_flag_of(CIF_ENABLED_WAIT, cpu))
410 return false;
411 if (pcpu_running(pcpu_devices + cpu))
412 return false;
413 return true;
8b646bd7 414}
760928c0 415EXPORT_SYMBOL(arch_vcpu_is_preempted);
8b646bd7 416
8ebf6da9 417void notrace smp_yield_cpu(int cpu)
85ac7ca5 418{
1b68ac86
HC
419 if (!MACHINE_HAS_DIAG9C)
420 return;
421 diag_stat_inc_norecursion(DIAG_STAT_X09C);
422 asm volatile("diag %0,0,0x9c"
423 : : "d" (pcpu_devices[cpu].address));
8b646bd7
MS
424}
425
426/*
427 * Send cpus emergency shutdown signal. This gives the cpus the
428 * opportunity to complete outstanding interrupts.
429 */
00a8f886 430void notrace smp_emergency_stop(void)
8b646bd7 431{
00a8f886 432 cpumask_t cpumask;
8b646bd7
MS
433 u64 end;
434 int cpu;
435
00a8f886
MS
436 cpumask_copy(&cpumask, cpu_online_mask);
437 cpumask_clear_cpu(smp_processor_id(), &cpumask);
438
1aae0560 439 end = get_tod_clock() + (1000000UL << 12);
00a8f886 440 for_each_cpu(cpu, &cpumask) {
8b646bd7
MS
441 struct pcpu *pcpu = pcpu_devices + cpu;
442 set_bit(ec_stop_cpu, &pcpu->ec_mask);
a9ae32c3
HC
443 while (__pcpu_sigp(pcpu->address, SIGP_EMERGENCY_SIGNAL,
444 0, NULL) == SIGP_CC_BUSY &&
1aae0560 445 get_tod_clock() < end)
8b646bd7
MS
446 cpu_relax();
447 }
1aae0560 448 while (get_tod_clock() < end) {
00a8f886 449 for_each_cpu(cpu, &cpumask)
8b646bd7 450 if (pcpu_stopped(pcpu_devices + cpu))
00a8f886
MS
451 cpumask_clear_cpu(cpu, &cpumask);
452 if (cpumask_empty(&cpumask))
8b646bd7 453 break;
85ac7ca5 454 cpu_relax();
8b646bd7 455 }
85ac7ca5 456}
00a8f886 457NOKPROBE_SYMBOL(smp_emergency_stop);
85ac7ca5 458
8b646bd7
MS
459/*
460 * Stop all cpus but the current one.
461 */
677d7623 462void smp_send_stop(void)
1da177e4 463{
85ac7ca5 464 int cpu;
1da177e4 465
677d7623 466 /* Disable all interrupts/machine checks */
e258d719 467 __load_psw_mask(PSW_KERNEL_BITS | PSW_MASK_DAT);
3324e60a 468 trace_hardirqs_off();
1da177e4 469
3ab121ab 470 debug_set_critical();
85ac7ca5 471
8b646bd7 472 if (oops_in_progress)
00a8f886 473 smp_emergency_stop();
1da177e4 474
85ac7ca5 475 /* stop all processors */
00a8f886
MS
476 for_each_online_cpu(cpu) {
477 if (cpu == smp_processor_id())
478 continue;
479 pcpu_sigp_retry(pcpu_devices + cpu, SIGP_STOP, 0);
480 while (!pcpu_stopped(pcpu_devices + cpu))
c6b5b847
HC
481 cpu_relax();
482 }
483}
484
1da177e4
LT
485/*
486 * This is the main routine where commands issued by other
487 * cpus are handled.
488 */
9acf73b7 489static void smp_handle_ext_call(void)
1da177e4 490{
39ce010d 491 unsigned long bits;
1da177e4 492
9acf73b7
HC
493 /* handle bit signal external calls */
494 bits = xchg(&pcpu_devices[smp_processor_id()].ec_mask, 0);
85ac7ca5
MS
495 if (test_bit(ec_stop_cpu, &bits))
496 smp_stop_cpu();
184748cc
PZ
497 if (test_bit(ec_schedule, &bits))
498 scheduler_ipi();
ca9fc75a
HC
499 if (test_bit(ec_call_function_single, &bits))
500 generic_smp_call_function_single_interrupt();
11886c19
SS
501 if (test_bit(ec_mcck_pending, &bits))
502 s390_handle_mcck();
9acf73b7 503}
85ac7ca5 504
9acf73b7
HC
505static void do_ext_call_interrupt(struct ext_code ext_code,
506 unsigned int param32, unsigned long param64)
507{
508 inc_irq_stat(ext_code.code == 0x1202 ? IRQEXT_EXC : IRQEXT_EMS);
509 smp_handle_ext_call();
1da177e4
LT
510}
511
630cd046 512void arch_send_call_function_ipi_mask(const struct cpumask *mask)
ca9fc75a
HC
513{
514 int cpu;
515
630cd046 516 for_each_cpu(cpu, mask)
b6ed49e0 517 pcpu_ec_call(pcpu_devices + cpu, ec_call_function_single);
ca9fc75a
HC
518}
519
520void arch_send_call_function_single_ipi(int cpu)
521{
8b646bd7 522 pcpu_ec_call(pcpu_devices + cpu, ec_call_function_single);
ca9fc75a
HC
523}
524
1da177e4
LT
525/*
526 * this function sends a 'reschedule' IPI to another CPU.
527 * it goes straight through and wastes no time serializing
528 * anything. Worst case is that we lose a reschedule ...
529 */
530void smp_send_reschedule(int cpu)
531{
8b646bd7 532 pcpu_ec_call(pcpu_devices + cpu, ec_schedule);
1da177e4
LT
533}
534
535/*
536 * parameter area for the set/clear control bit callbacks
537 */
94c12cc7 538struct ec_creg_mask_parms {
8b646bd7
MS
539 unsigned long orval;
540 unsigned long andval;
541 int cr;
94c12cc7 542};
1da177e4
LT
543
544/*
545 * callback for setting/clearing control bits
546 */
39ce010d
HC
547static void smp_ctl_bit_callback(void *info)
548{
94c12cc7 549 struct ec_creg_mask_parms *pp = info;
1da177e4 550 unsigned long cregs[16];
39ce010d 551
94c12cc7 552 __ctl_store(cregs, 0, 15);
8b646bd7 553 cregs[pp->cr] = (cregs[pp->cr] & pp->andval) | pp->orval;
94c12cc7 554 __ctl_load(cregs, 0, 15);
1da177e4
LT
555}
556
557/*
558 * Set a bit in a control register of all cpus
559 */
94c12cc7
MS
560void smp_ctl_set_bit(int cr, int bit)
561{
8b646bd7 562 struct ec_creg_mask_parms parms = { 1UL << bit, -1UL, cr };
1da177e4 563
15c8b6c1 564 on_each_cpu(smp_ctl_bit_callback, &parms, 1);
1da177e4 565}
39ce010d 566EXPORT_SYMBOL(smp_ctl_set_bit);
1da177e4
LT
567
568/*
569 * Clear a bit in a control register of all cpus
570 */
94c12cc7
MS
571void smp_ctl_clear_bit(int cr, int bit)
572{
8b646bd7 573 struct ec_creg_mask_parms parms = { 0, ~(1UL << bit), cr };
1da177e4 574
15c8b6c1 575 on_each_cpu(smp_ctl_bit_callback, &parms, 1);
1da177e4 576}
39ce010d 577EXPORT_SYMBOL(smp_ctl_clear_bit);
1da177e4 578
bf28a597 579#ifdef CONFIG_CRASH_DUMP
411ed322 580
1af135a1
HC
581int smp_store_status(int cpu)
582{
1a36a39e
MS
583 struct pcpu *pcpu = pcpu_devices + cpu;
584 unsigned long pa;
1af135a1 585
1a36a39e
MS
586 pa = __pa(&pcpu->lowcore->floating_pt_save_area);
587 if (__pcpu_sigp_relax(pcpu->address, SIGP_STORE_STATUS_AT_ADDRESS,
588 pa) != SIGP_CC_ORDER_CODE_ACCEPTED)
1af135a1 589 return -EIO;
916cda1a 590 if (!MACHINE_HAS_VX && !MACHINE_HAS_GS)
1af135a1 591 return 0;
916cda1a
MS
592 pa = __pa(pcpu->lowcore->mcesad & MCESA_ORIGIN_MASK);
593 if (MACHINE_HAS_GS)
594 pa |= pcpu->lowcore->mcesad & MCESA_LC_MASK;
1a36a39e
MS
595 if (__pcpu_sigp_relax(pcpu->address, SIGP_STORE_ADDITIONAL_STATUS,
596 pa) != SIGP_CC_ORDER_CODE_ACCEPTED)
597 return -EIO;
1af135a1
HC
598 return 0;
599}
600
10ad34bc
MS
601/*
602 * Collect CPU state of the previous, crashed system.
603 * There are four cases:
bd37b368
AE
604 * 1) standard zfcp/nvme dump
605 * condition: OLDMEM_BASE == NULL && is_ipl_type_dump() == true
10ad34bc
MS
606 * The state for all CPUs except the boot CPU needs to be collected
607 * with sigp stop-and-store-status. The boot CPU state is located in
608 * the absolute lowcore of the memory stored in the HSA. The zcore code
1a36a39e 609 * will copy the boot CPU state from the HSA.
bd37b368
AE
610 * 2) stand-alone kdump for SCSI/NVMe (zfcp/nvme dump with swapped memory)
611 * condition: OLDMEM_BASE != NULL && is_ipl_type_dump() == true
10ad34bc
MS
612 * The state for all CPUs except the boot CPU needs to be collected
613 * with sigp stop-and-store-status. The firmware or the boot-loader
614 * stored the registers of the boot CPU in the absolute lowcore in the
615 * memory of the old system.
616 * 3) kdump and the old kernel did not store the CPU state,
617 * or stand-alone kdump for DASD
618 * condition: OLDMEM_BASE != NULL && !is_kdump_kernel()
619 * The state for all CPUs except the boot CPU needs to be collected
620 * with sigp stop-and-store-status. The kexec code or the boot-loader
621 * stored the registers of the boot CPU in the memory of the old system.
622 * 4) kdump and the old kernel stored the CPU state
623 * condition: OLDMEM_BASE != NULL && is_kdump_kernel()
8a07dd02
MS
624 * This case does not exist for s390 anymore, setup_arch explicitly
625 * deactivates the elfcorehdr= kernel parameter
10ad34bc 626 */
1a2c5840 627static __init void smp_save_cpu_vxrs(struct save_area *sa, u16 addr,
1a36a39e
MS
628 bool is_boot_cpu, unsigned long page)
629{
630 __vector128 *vxrs = (__vector128 *) page;
631
632 if (is_boot_cpu)
633 vxrs = boot_cpu_vector_save_area;
634 else
635 __pcpu_sigp_relax(addr, SIGP_STORE_ADDITIONAL_STATUS, page);
1a2c5840 636 save_area_add_vxrs(sa, vxrs);
1a36a39e
MS
637}
638
1a2c5840 639static __init void smp_save_cpu_regs(struct save_area *sa, u16 addr,
1a36a39e
MS
640 bool is_boot_cpu, unsigned long page)
641{
642 void *regs = (void *) page;
643
644 if (is_boot_cpu)
645 copy_oldmem_kernel(regs, (void *) __LC_FPREGS_SAVE_AREA, 512);
646 else
647 __pcpu_sigp_relax(addr, SIGP_STORE_STATUS_AT_ADDRESS, page);
1a2c5840 648 save_area_add_regs(sa, regs);
1a36a39e
MS
649}
650
1592a8e4 651void __init smp_save_dump_cpus(void)
10ad34bc 652{
1a2c5840
MS
653 int addr, boot_cpu_addr, max_cpu_addr;
654 struct save_area *sa;
1a36a39e 655 unsigned long page;
1592a8e4 656 bool is_boot_cpu;
10ad34bc 657
bd37b368 658 if (!(OLDMEM_BASE || is_ipl_type_dump()))
10ad34bc
MS
659 /* No previous system present, normal boot. */
660 return;
1a36a39e 661 /* Allocate a page as dumping area for the store status sigps */
0ba9e6ed
MR
662 page = memblock_phys_alloc_range(PAGE_SIZE, PAGE_SIZE, 0, 1UL << 31);
663 if (!page)
8a7f97b9 664 panic("ERROR: Failed to allocate %lx bytes below %lx\n",
0ba9e6ed
MR
665 PAGE_SIZE, 1UL << 31);
666
10ad34bc 667 /* Set multi-threading state to the previous system. */
37c5f6c8 668 pcpu_set_smt(sclp.mtid_prev);
1592a8e4 669 boot_cpu_addr = stap();
1a2c5840
MS
670 max_cpu_addr = SCLP_MAX_CORES << sclp.mtid_prev;
671 for (addr = 0; addr <= max_cpu_addr; addr++) {
1a36a39e 672 if (__pcpu_sigp_relax(addr, SIGP_SENSE, 0) ==
1592a8e4
MH
673 SIGP_CC_NOT_OPERATIONAL)
674 continue;
1592a8e4 675 is_boot_cpu = (addr == boot_cpu_addr);
1a2c5840
MS
676 /* Allocate save area */
677 sa = save_area_alloc(is_boot_cpu);
678 if (!sa)
679 panic("could not allocate memory for save area\n");
1a36a39e
MS
680 if (MACHINE_HAS_VX)
681 /* Get the vector registers */
1a2c5840 682 smp_save_cpu_vxrs(sa, addr, is_boot_cpu, page);
1a36a39e 683 /*
bd37b368 684 * For a zfcp/nvme dump OLDMEM_BASE == NULL and the registers
1a36a39e
MS
685 * of the boot CPU are stored in the HSA. To retrieve
686 * these registers an SCLP request is required which is
687 * done by drivers/s390/char/zcore.c:init_cpu_info()
688 */
689 if (!is_boot_cpu || OLDMEM_BASE)
690 /* Get the CPU registers */
1a2c5840 691 smp_save_cpu_regs(sa, addr, is_boot_cpu, page);
10ad34bc 692 }
1a36a39e 693 memblock_free(page, PAGE_SIZE);
a80313ff 694 diag_dma_ops.diag308_reset();
1592a8e4 695 pcpu_set_smt(0);
1af135a1 696}
1a36a39e 697#endif /* CONFIG_CRASH_DUMP */
08d07968 698
50ab9a9a
HC
699void smp_cpu_set_polarization(int cpu, int val)
700{
701 pcpu_devices[cpu].polarization = val;
702}
703
704int smp_cpu_get_polarization(int cpu)
705{
706 return pcpu_devices[cpu].polarization;
707}
708
42d211a1
AG
709int smp_cpu_get_cpu_address(int cpu)
710{
711 return pcpu_devices[cpu].address;
712}
713
af51160e 714static void __ref smp_get_core_info(struct sclp_core_info *info, int early)
08d07968 715{
8b646bd7 716 static int use_sigp_detection;
8b646bd7
MS
717 int address;
718
af51160e 719 if (use_sigp_detection || sclp_get_core_info(info, early)) {
8b646bd7 720 use_sigp_detection = 1;
e7086eb1 721 for (address = 0;
d08d9430 722 address < (SCLP_MAX_CORES << smp_cpu_mt_shift);
10ad34bc 723 address += (1U << smp_cpu_mt_shift)) {
1a36a39e 724 if (__pcpu_sigp_relax(address, SIGP_SENSE, 0) ==
a9ae32c3 725 SIGP_CC_NOT_OPERATIONAL)
8b646bd7 726 continue;
d08d9430 727 info->core[info->configured].core_id =
10ad34bc 728 address >> smp_cpu_mt_shift;
8b646bd7
MS
729 info->configured++;
730 }
731 info->combined = info->configured;
08d07968 732 }
08d07968
HC
733}
734
e2741f17 735static int smp_add_present_cpu(int cpu);
8b646bd7 736
72a81ad9
HC
737static int smp_add_core(struct sclp_core_entry *core, cpumask_t *avail,
738 bool configured, bool early)
08d07968 739{
8b646bd7 740 struct pcpu *pcpu;
72a81ad9 741 int cpu, nr, i;
10ad34bc 742 u16 address;
08d07968 743
8b646bd7 744 nr = 0;
72a81ad9
HC
745 if (sclp.has_core_type && core->type != boot_core_type)
746 return nr;
747 cpu = cpumask_first(avail);
748 address = core->core_id << smp_cpu_mt_shift;
749 for (i = 0; (i <= smp_cpu_mtid) && (cpu < nr_cpu_ids); i++) {
750 if (pcpu_find_address(cpu_present_mask, address + i))
8b646bd7 751 continue;
72a81ad9
HC
752 pcpu = pcpu_devices + cpu;
753 pcpu->address = address + i;
754 if (configured)
755 pcpu->state = CPU_STATE_CONFIGURED;
756 else
757 pcpu->state = CPU_STATE_STANDBY;
758 smp_cpu_set_polarization(cpu, POLARIZATION_UNKNOWN);
759 set_cpu_present(cpu, true);
760 if (!early && smp_add_present_cpu(cpu) != 0)
761 set_cpu_present(cpu, false);
762 else
763 nr++;
764 cpumask_clear_cpu(cpu, avail);
765 cpu = cpumask_next(cpu, avail);
766 }
767 return nr;
768}
769
770static int __smp_rescan_cpus(struct sclp_core_info *info, bool early)
771{
772 struct sclp_core_entry *core;
773 cpumask_t avail;
774 bool configured;
775 u16 core_id;
776 int nr, i;
777
778 nr = 0;
779 cpumask_xor(&avail, cpu_possible_mask, cpu_present_mask);
780 /*
781 * Add IPL core first (which got logical CPU number 0) to make sure
782 * that all SMT threads get subsequent logical CPU numbers.
783 */
784 if (early) {
785 core_id = pcpu_devices[0].address >> smp_cpu_mt_shift;
786 for (i = 0; i < info->configured; i++) {
787 core = &info->core[i];
788 if (core->core_id == core_id) {
789 nr += smp_add_core(core, &avail, true, early);
10ad34bc 790 break;
72a81ad9 791 }
10ad34bc 792 }
8b646bd7 793 }
72a81ad9
HC
794 for (i = 0; i < info->combined; i++) {
795 configured = i < info->configured;
796 nr += smp_add_core(&info->core[i], &avail, configured, early);
797 }
8b646bd7 798 return nr;
1da177e4
LT
799}
800
af51160e 801void __init smp_detect_cpus(void)
48483b32 802{
10ad34bc 803 unsigned int cpu, mtid, c_cpus, s_cpus;
d08d9430 804 struct sclp_core_info *info;
10ad34bc 805 u16 address;
48483b32 806
10ad34bc 807 /* Get CPU information */
eb31d559 808 info = memblock_alloc(sizeof(*info), 8);
8a7f97b9
MR
809 if (!info)
810 panic("%s: Failed to allocate %zu bytes align=0x%x\n",
811 __func__, sizeof(*info), 8);
af51160e 812 smp_get_core_info(info, 1);
10ad34bc 813 /* Find boot CPU type */
d08d9430 814 if (sclp.has_core_type) {
10ad34bc
MS
815 address = stap();
816 for (cpu = 0; cpu < info->combined; cpu++)
d08d9430 817 if (info->core[cpu].core_id == address) {
10ad34bc 818 /* The boot cpu dictates the cpu type. */
d08d9430 819 boot_core_type = info->core[cpu].type;
10ad34bc
MS
820 break;
821 }
822 if (cpu >= info->combined)
823 panic("Could not find boot CPU type");
48483b32 824 }
10ad34bc 825
10ad34bc 826 /* Set multi-threading state for the current system */
d08d9430 827 mtid = boot_core_type ? sclp.mtid : sclp.mtid_cp;
10ad34bc
MS
828 mtid = (mtid < smp_max_threads) ? mtid : smp_max_threads - 1;
829 pcpu_set_smt(mtid);
830
831 /* Print number of CPUs */
8b646bd7 832 c_cpus = s_cpus = 0;
48483b32 833 for (cpu = 0; cpu < info->combined; cpu++) {
d08d9430
MS
834 if (sclp.has_core_type &&
835 info->core[cpu].type != boot_core_type)
48483b32 836 continue;
10ad34bc
MS
837 if (cpu < info->configured)
838 c_cpus += smp_cpu_mtid + 1;
839 else
840 s_cpus += smp_cpu_mtid + 1;
48483b32 841 }
395d31d4 842 pr_info("%d configured CPUs, %d standby CPUs\n", c_cpus, s_cpus);
10ad34bc
MS
843
844 /* Add CPUs present at boot */
9d40d2e3 845 get_online_cpus();
72a81ad9 846 __smp_rescan_cpus(info, true);
9d40d2e3 847 put_online_cpus();
af51160e 848 memblock_free_early((unsigned long)info, sizeof(*info));
48483b32
HC
849}
850
ce3dc447 851static void smp_init_secondary(void)
1da177e4 852{
de5d9dae 853 int cpu = raw_smp_processor_id();
1887aa07 854
9e8df6da
VG
855 S390_lowcore.last_update_clock = get_tod_clock();
856 restore_access_regs(S390_lowcore.access_regs_save_area);
39ce010d 857 cpu_init();
de5d9dae 858 rcu_cpu_starting(cpu);
5bfb5d69 859 preempt_disable();
39ce010d 860 init_cpu_timer();
b5f87f15 861 vtime_init();
80f06306 862 vdso_getcpu_init();
29b08d2b 863 pfault_init();
52aeda7a 864 notify_cpu_starting(cpu);
1887aa07
MS
865 if (topology_cpu_dedicated(cpu))
866 set_cpu_flag(CIF_DEDICATED_CPU);
867 else
868 clear_cpu_flag(CIF_DEDICATED_CPU);
52aeda7a
AG
869 set_cpu_online(cpu, true);
870 update_cpu_masks();
93f3b2ee 871 inc_irq_stat(CPU_RST);
1da177e4 872 local_irq_enable();
fc6d73d6 873 cpu_startup_entry(CPUHP_AP_ONLINE_IDLE);
1da177e4
LT
874}
875
ce3dc447
MS
876/*
877 * Activate a secondary processor.
878 */
9e8df6da 879static void __no_sanitize_address smp_start_secondary(void *cpuvoid)
ce3dc447 880{
ce3dc447
MS
881 S390_lowcore.restart_stack = (unsigned long) restart_stack;
882 S390_lowcore.restart_fn = (unsigned long) do_restart;
883 S390_lowcore.restart_data = 0;
884 S390_lowcore.restart_source = -1UL;
ce3dc447
MS
885 __ctl_load(S390_lowcore.cregs_save_area, 0, 15);
886 __load_psw_mask(PSW_KERNEL_BITS | PSW_MASK_DAT);
7bcaad1f 887 CALL_ON_STACK_NORETURN(smp_init_secondary, S390_lowcore.kernel_stack);
ce3dc447
MS
888}
889
1da177e4 890/* Upping and downing of CPUs */
e2741f17 891int __cpu_up(unsigned int cpu, struct task_struct *tidle)
1da177e4 892{
b5e438eb
SS
893 struct pcpu *pcpu = pcpu_devices + cpu;
894 int rc;
1da177e4 895
8b646bd7 896 if (pcpu->state != CPU_STATE_CONFIGURED)
08d07968 897 return -EIO;
b5e438eb 898 if (pcpu_sigp_retry(pcpu, SIGP_INITIAL_CPU_RESET, 0) !=
a9ae32c3 899 SIGP_CC_ORDER_CODE_ACCEPTED)
08d07968 900 return -EIO;
e80e7813 901
8b646bd7
MS
902 rc = pcpu_alloc_lowcore(pcpu, cpu);
903 if (rc)
904 return rc;
905 pcpu_prepare_secondary(pcpu, cpu);
e80e7813 906 pcpu_attach_task(pcpu, tidle);
8b646bd7 907 pcpu_start_fn(pcpu, smp_start_secondary, NULL);
a1307bba 908 /* Wait until cpu puts itself in the online & active maps */
e9d867a6 909 while (!cpu_online(cpu))
1da177e4
LT
910 cpu_relax();
911 return 0;
912}
913
d80512f8 914static unsigned int setup_possible_cpus __initdata;
255acee7 915
d80512f8
HC
916static int __init _setup_possible_cpus(char *s)
917{
918 get_option(&s, &setup_possible_cpus);
37a33026
HC
919 return 0;
920}
d80512f8 921early_param("possible_cpus", _setup_possible_cpus);
37a33026 922
39ce010d 923int __cpu_disable(void)
1da177e4 924{
8b646bd7 925 unsigned long cregs[16];
1da177e4 926
9acf73b7
HC
927 /* Handle possible pending IPIs */
928 smp_handle_ext_call();
8b646bd7 929 set_cpu_online(smp_processor_id(), false);
52aeda7a 930 update_cpu_masks();
8b646bd7 931 /* Disable pseudo page faults on this cpu. */
29b08d2b 932 pfault_fini();
8b646bd7
MS
933 /* Disable interrupt sources via control register. */
934 __ctl_store(cregs, 0, 15);
935 cregs[0] &= ~0x0000ee70UL; /* disable all external interrupts */
936 cregs[6] &= ~0xff000000UL; /* disable all I/O interrupts */
937 cregs[14] &= ~0x1f000000UL; /* disable most machine checks */
938 __ctl_load(cregs, 0, 15);
fe0f4976 939 clear_cpu_flag(CIF_NOHZ_DELAY);
1da177e4
LT
940 return 0;
941}
942
39ce010d 943void __cpu_die(unsigned int cpu)
1da177e4 944{
8b646bd7
MS
945 struct pcpu *pcpu;
946
1da177e4 947 /* Wait until target cpu is down */
8b646bd7
MS
948 pcpu = pcpu_devices + cpu;
949 while (!pcpu_stopped(pcpu))
1da177e4 950 cpu_relax();
8b646bd7 951 pcpu_free_lowcore(pcpu);
1b948d6c 952 cpumask_clear_cpu(cpu, mm_cpumask(&init_mm));
64f31d58 953 cpumask_clear_cpu(cpu, &init_mm.context.cpu_attach_mask);
1da177e4
LT
954}
955
b456d94a 956void __noreturn cpu_die(void)
1da177e4
LT
957{
958 idle_task_exit();
d768bd89 959 __bpon();
a9ae32c3 960 pcpu_sigp_retry(pcpu_devices + smp_processor_id(), SIGP_STOP, 0);
8b646bd7 961 for (;;) ;
1da177e4
LT
962}
963
d80512f8
HC
964void __init smp_fill_possible_mask(void)
965{
9747bc47 966 unsigned int possible, sclp_max, cpu;
d80512f8 967
3a9f3fe6
DH
968 sclp_max = max(sclp.mtid, sclp.mtid_cp) + 1;
969 sclp_max = min(smp_max_threads, sclp_max);
61282aff 970 sclp_max = (sclp.max_cores * sclp_max) ?: nr_cpu_ids;
cf813db0 971 possible = setup_possible_cpus ?: nr_cpu_ids;
9747bc47 972 possible = min(possible, sclp_max);
d80512f8
HC
973 for (cpu = 0; cpu < possible && cpu < nr_cpu_ids; cpu++)
974 set_cpu_possible(cpu, true);
975}
976
1da177e4
LT
977void __init smp_prepare_cpus(unsigned int max_cpus)
978{
39ce010d 979 /* request the 0x1201 emergency signal external interrupt */
1dad093b 980 if (register_external_irq(EXT_IRQ_EMERGENCY_SIG, do_ext_call_interrupt))
39ce010d 981 panic("Couldn't request external interrupt 0x1201");
d98e19cc 982 /* request the 0x1202 external call external interrupt */
1dad093b 983 if (register_external_irq(EXT_IRQ_EXTERNAL_CALL, do_ext_call_interrupt))
d98e19cc 984 panic("Couldn't request external interrupt 0x1202");
1da177e4
LT
985}
986
ea1f4eec 987void __init smp_prepare_boot_cpu(void)
1da177e4 988{
8b646bd7
MS
989 struct pcpu *pcpu = pcpu_devices;
990
0861b5a7 991 WARN_ON(!cpu_present(0) || !cpu_online(0));
8b646bd7 992 pcpu->state = CPU_STATE_CONFIGURED;
c667aeac 993 pcpu->lowcore = (struct lowcore *)(unsigned long) store_prefix();
1da177e4 994 S390_lowcore.percpu_offset = __per_cpu_offset[0];
50ab9a9a 995 smp_cpu_set_polarization(0, POLARIZATION_UNKNOWN);
1da177e4
LT
996}
997
02beaccc
HC
998void __init smp_setup_processor_id(void)
999{
0861b5a7 1000 pcpu_devices[0].address = stap();
02beaccc 1001 S390_lowcore.cpu_nr = 0;
6c8cd5bb 1002 S390_lowcore.spinlock_lockval = arch_spin_lockval(0);
b96f7d88 1003 S390_lowcore.spinlock_index = 0;
02beaccc
HC
1004}
1005
1da177e4
LT
1006/*
1007 * the frequency of the profiling timer can be changed
1008 * by writing a multiplier value into /proc/profile.
1009 *
1010 * usually you want to run this on all CPUs ;)
1011 */
1012int setup_profiling_timer(unsigned int multiplier)
1013{
39ce010d 1014 return 0;
1da177e4
LT
1015}
1016
8a25a2fd 1017static ssize_t cpu_configure_show(struct device *dev,
8b646bd7 1018 struct device_attribute *attr, char *buf)
08d07968
HC
1019{
1020 ssize_t count;
1021
1022 mutex_lock(&smp_cpu_state_mutex);
8b646bd7 1023 count = sprintf(buf, "%d\n", pcpu_devices[dev->id].state);
08d07968
HC
1024 mutex_unlock(&smp_cpu_state_mutex);
1025 return count;
1026}
1027
8a25a2fd 1028static ssize_t cpu_configure_store(struct device *dev,
8b646bd7
MS
1029 struct device_attribute *attr,
1030 const char *buf, size_t count)
08d07968 1031{
8b646bd7 1032 struct pcpu *pcpu;
10ad34bc 1033 int cpu, val, rc, i;
08d07968
HC
1034 char delim;
1035
1036 if (sscanf(buf, "%d %c", &val, &delim) != 1)
1037 return -EINVAL;
1038 if (val != 0 && val != 1)
1039 return -EINVAL;
9d40d2e3 1040 get_online_cpus();
0b18d318 1041 mutex_lock(&smp_cpu_state_mutex);
08d07968 1042 rc = -EBUSY;
2c2df118 1043 /* disallow configuration changes of online cpus and cpu 0 */
8b646bd7 1044 cpu = dev->id;
5423145f 1045 cpu = smp_get_base_cpu(cpu);
10ad34bc 1046 if (cpu == 0)
08d07968 1047 goto out;
10ad34bc
MS
1048 for (i = 0; i <= smp_cpu_mtid; i++)
1049 if (cpu_online(cpu + i))
1050 goto out;
8b646bd7 1051 pcpu = pcpu_devices + cpu;
08d07968
HC
1052 rc = 0;
1053 switch (val) {
1054 case 0:
8b646bd7
MS
1055 if (pcpu->state != CPU_STATE_CONFIGURED)
1056 break;
d08d9430 1057 rc = sclp_core_deconfigure(pcpu->address >> smp_cpu_mt_shift);
8b646bd7
MS
1058 if (rc)
1059 break;
10ad34bc
MS
1060 for (i = 0; i <= smp_cpu_mtid; i++) {
1061 if (cpu + i >= nr_cpu_ids || !cpu_present(cpu + i))
1062 continue;
1063 pcpu[i].state = CPU_STATE_STANDBY;
1064 smp_cpu_set_polarization(cpu + i,
1065 POLARIZATION_UNKNOWN);
1066 }
8b646bd7 1067 topology_expect_change();
08d07968
HC
1068 break;
1069 case 1:
8b646bd7
MS
1070 if (pcpu->state != CPU_STATE_STANDBY)
1071 break;
d08d9430 1072 rc = sclp_core_configure(pcpu->address >> smp_cpu_mt_shift);
8b646bd7
MS
1073 if (rc)
1074 break;
10ad34bc
MS
1075 for (i = 0; i <= smp_cpu_mtid; i++) {
1076 if (cpu + i >= nr_cpu_ids || !cpu_present(cpu + i))
1077 continue;
1078 pcpu[i].state = CPU_STATE_CONFIGURED;
1079 smp_cpu_set_polarization(cpu + i,
1080 POLARIZATION_UNKNOWN);
1081 }
8b646bd7 1082 topology_expect_change();
08d07968
HC
1083 break;
1084 default:
1085 break;
1086 }
1087out:
08d07968 1088 mutex_unlock(&smp_cpu_state_mutex);
0b18d318 1089 put_online_cpus();
08d07968
HC
1090 return rc ? rc : count;
1091}
8a25a2fd 1092static DEVICE_ATTR(configure, 0644, cpu_configure_show, cpu_configure_store);
08d07968 1093
8a25a2fd
KS
1094static ssize_t show_cpu_address(struct device *dev,
1095 struct device_attribute *attr, char *buf)
08d07968 1096{
8b646bd7 1097 return sprintf(buf, "%d\n", pcpu_devices[dev->id].address);
08d07968 1098}
8a25a2fd 1099static DEVICE_ATTR(address, 0444, show_cpu_address, NULL);
08d07968 1100
08d07968 1101static struct attribute *cpu_common_attrs[] = {
8a25a2fd 1102 &dev_attr_configure.attr,
8a25a2fd 1103 &dev_attr_address.attr,
08d07968
HC
1104 NULL,
1105};
1106
1107static struct attribute_group cpu_common_attr_group = {
1108 .attrs = cpu_common_attrs,
1109};
1da177e4 1110
08d07968 1111static struct attribute *cpu_online_attrs[] = {
8a25a2fd
KS
1112 &dev_attr_idle_count.attr,
1113 &dev_attr_idle_time_us.attr,
fae8b22d
HC
1114 NULL,
1115};
1116
08d07968
HC
1117static struct attribute_group cpu_online_attr_group = {
1118 .attrs = cpu_online_attrs,
fae8b22d
HC
1119};
1120
dfbbd86a 1121static int smp_cpu_online(unsigned int cpu)
2fc2d1e9 1122{
2f859d0d 1123 struct device *s = &per_cpu(cpu_device, cpu)->dev;
2fc2d1e9 1124
dfbbd86a
SAS
1125 return sysfs_create_group(&s->kobj, &cpu_online_attr_group);
1126}
8e1398f8 1127
dfbbd86a
SAS
1128static int smp_cpu_pre_down(unsigned int cpu)
1129{
1130 struct device *s = &per_cpu(cpu_device, cpu)->dev;
1131
1132 sysfs_remove_group(&s->kobj, &cpu_online_attr_group);
1133 return 0;
2fc2d1e9
HC
1134}
1135
e2741f17 1136static int smp_add_present_cpu(int cpu)
08d07968 1137{
96619fc1
HC
1138 struct device *s;
1139 struct cpu *c;
08d07968
HC
1140 int rc;
1141
96619fc1
HC
1142 c = kzalloc(sizeof(*c), GFP_KERNEL);
1143 if (!c)
1144 return -ENOMEM;
2f859d0d 1145 per_cpu(cpu_device, cpu) = c;
96619fc1 1146 s = &c->dev;
08d07968
HC
1147 c->hotpluggable = 1;
1148 rc = register_cpu(c, cpu);
1149 if (rc)
1150 goto out;
1151 rc = sysfs_create_group(&s->kobj, &cpu_common_attr_group);
1152 if (rc)
1153 goto out_cpu;
83a24e32
HC
1154 rc = topology_cpu_init(c);
1155 if (rc)
1156 goto out_topology;
1157 return 0;
1158
1159out_topology:
08d07968
HC
1160 sysfs_remove_group(&s->kobj, &cpu_common_attr_group);
1161out_cpu:
08d07968 1162 unregister_cpu(c);
08d07968
HC
1163out:
1164 return rc;
1165}
1166
67060d9c 1167int __ref smp_rescan_cpus(void)
08d07968 1168{
d08d9430 1169 struct sclp_core_info *info;
8b646bd7 1170 int nr;
08d07968 1171
af51160e 1172 info = kzalloc(sizeof(*info), GFP_KERNEL);
8b646bd7
MS
1173 if (!info)
1174 return -ENOMEM;
af51160e 1175 smp_get_core_info(info, 0);
9d40d2e3 1176 get_online_cpus();
0b18d318 1177 mutex_lock(&smp_cpu_state_mutex);
72a81ad9 1178 nr = __smp_rescan_cpus(info, false);
08d07968 1179 mutex_unlock(&smp_cpu_state_mutex);
0b18d318 1180 put_online_cpus();
8b646bd7
MS
1181 kfree(info);
1182 if (nr)
c10fde0d 1183 topology_schedule_update();
8b646bd7 1184 return 0;
1e489518
HC
1185}
1186
8a25a2fd
KS
1187static ssize_t __ref rescan_store(struct device *dev,
1188 struct device_attribute *attr,
c9be0a36 1189 const char *buf,
1e489518
HC
1190 size_t count)
1191{
1192 int rc;
1193
b7cb707c
GS
1194 rc = lock_device_hotplug_sysfs();
1195 if (rc)
1196 return rc;
1e489518 1197 rc = smp_rescan_cpus();
b7cb707c 1198 unlock_device_hotplug();
08d07968
HC
1199 return rc ? rc : count;
1200}
6cbaefb4 1201static DEVICE_ATTR_WO(rescan);
08d07968 1202
83a24e32 1203static int __init s390_smp_init(void)
1da177e4 1204{
f4edbcd5 1205 int cpu, rc = 0;
2fc2d1e9 1206
8a25a2fd 1207 rc = device_create_file(cpu_subsys.dev_root, &dev_attr_rescan);
08d07968
HC
1208 if (rc)
1209 return rc;
08d07968
HC
1210 for_each_present_cpu(cpu) {
1211 rc = smp_add_present_cpu(cpu);
fae8b22d 1212 if (rc)
f4edbcd5 1213 goto out;
1da177e4 1214 }
f4edbcd5 1215
dfbbd86a
SAS
1216 rc = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "s390/smp:online",
1217 smp_cpu_online, smp_cpu_pre_down);
e1108e8f 1218 rc = rc <= 0 ? rc : 0;
f4edbcd5 1219out:
f4edbcd5 1220 return rc;
1da177e4 1221}
83a24e32 1222subsys_initcall(s390_smp_init);