Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * arch/s390/kernel/smp.c | |
3 | * | |
155af2f9 | 4 | * Copyright IBM Corp. 1999, 2009 |
1da177e4 | 5 | * Author(s): Denis Joseph Barrow (djbarrow@de.ibm.com,barrow_dj@yahoo.com), |
39ce010d HC |
6 | * Martin Schwidefsky (schwidefsky@de.ibm.com) |
7 | * Heiko Carstens (heiko.carstens@de.ibm.com) | |
1da177e4 | 8 | * |
39ce010d | 9 | * based on other smp stuff by |
1da177e4 LT |
10 | * (c) 1995 Alan Cox, CymruNET Ltd <alan@cymru.net> |
11 | * (c) 1998 Ingo Molnar | |
12 | * | |
13 | * We work with logical cpu numbering everywhere we can. The only | |
14 | * functions using the real cpu address (got from STAP) are the sigp | |
15 | * functions. For all other functions we use the identity mapping. | |
16 | * That means that cpu_number_map[i] == i for every cpu. cpu_number_map is | |
17 | * used e.g. to find the idle task belonging to a logical cpu. Every array | |
18 | * in the kernel is sorted by the logical cpu number and not by the physical | |
19 | * one which is causing all the confusion with __cpu_logical_map and | |
20 | * cpu_number_map in other architectures. | |
21 | */ | |
22 | ||
395d31d4 MS |
23 | #define KMSG_COMPONENT "cpu" |
24 | #define pr_fmt(fmt) KMSG_COMPONENT ": " fmt | |
25 | ||
f230886b | 26 | #include <linux/workqueue.h> |
1da177e4 LT |
27 | #include <linux/module.h> |
28 | #include <linux/init.h> | |
1da177e4 | 29 | #include <linux/mm.h> |
4e950f6f | 30 | #include <linux/err.h> |
1da177e4 LT |
31 | #include <linux/spinlock.h> |
32 | #include <linux/kernel_stat.h> | |
1da177e4 LT |
33 | #include <linux/delay.h> |
34 | #include <linux/cache.h> | |
35 | #include <linux/interrupt.h> | |
3324e60a | 36 | #include <linux/irqflags.h> |
1da177e4 | 37 | #include <linux/cpu.h> |
2b67fc46 | 38 | #include <linux/timex.h> |
411ed322 | 39 | #include <linux/bootmem.h> |
5a0e3ad6 | 40 | #include <linux/slab.h> |
60a0c68d | 41 | #include <linux/crash_dump.h> |
cbb870c8 | 42 | #include <asm/asm-offsets.h> |
46b05d26 | 43 | #include <asm/ipl.h> |
2b67fc46 | 44 | #include <asm/setup.h> |
1da177e4 LT |
45 | #include <asm/sigp.h> |
46 | #include <asm/pgalloc.h> | |
47 | #include <asm/irq.h> | |
1da177e4 LT |
48 | #include <asm/cpcmd.h> |
49 | #include <asm/tlbflush.h> | |
2b67fc46 | 50 | #include <asm/timer.h> |
411ed322 | 51 | #include <asm/lowcore.h> |
08d07968 | 52 | #include <asm/sclp.h> |
76d4e00a | 53 | #include <asm/cputime.h> |
c742b31c | 54 | #include <asm/vdso.h> |
4bb5e07b | 55 | #include <asm/cpu.h> |
a806170e | 56 | #include "entry.h" |
1da177e4 | 57 | |
fb380aad | 58 | /* logical cpu to cpu address */ |
a93b8ec1 | 59 | unsigned short __cpu_logical_map[NR_CPUS]; |
fb380aad | 60 | |
1da177e4 LT |
61 | static struct task_struct *current_set[NR_CPUS]; |
62 | ||
08d07968 HC |
63 | static u8 smp_cpu_type; |
64 | static int smp_use_sigp_detection; | |
65 | ||
66 | enum s390_cpu_state { | |
67 | CPU_STATE_STANDBY, | |
68 | CPU_STATE_CONFIGURED, | |
69 | }; | |
70 | ||
dbd70fb4 | 71 | DEFINE_MUTEX(smp_cpu_state_mutex); |
08d07968 HC |
72 | static int smp_cpu_state[NR_CPUS]; |
73 | ||
74 | static DEFINE_PER_CPU(struct cpu, cpu_devices); | |
08d07968 | 75 | |
a93b8ec1 | 76 | static void smp_ext_bitcall(int, int); |
1da177e4 | 77 | |
a93b8ec1 | 78 | static int raw_cpu_stopped(int cpu) |
5c0b912e | 79 | { |
a93b8ec1 | 80 | u32 status; |
5c0b912e | 81 | |
a93b8ec1 | 82 | switch (raw_sigp_ps(&status, 0, cpu, sigp_sense)) { |
5c0b912e HC |
83 | case sigp_status_stored: |
84 | /* Check for stopped and check stop state */ | |
85 | if (status & 0x50) | |
86 | return 1; | |
87 | break; | |
88 | default: | |
89 | break; | |
90 | } | |
91 | return 0; | |
92 | } | |
93 | ||
a93b8ec1 HC |
94 | static inline int cpu_stopped(int cpu) |
95 | { | |
96 | return raw_cpu_stopped(cpu_logical_map(cpu)); | |
97 | } | |
98 | ||
1943f53c MH |
99 | /* |
100 | * Ensure that PSW restart is done on an online CPU | |
101 | */ | |
102 | void smp_restart_with_online_cpu(void) | |
103 | { | |
104 | int cpu; | |
105 | ||
106 | for_each_online_cpu(cpu) { | |
107 | if (stap() == __cpu_logical_map[cpu]) { | |
108 | /* We are online: Enable DAT again and return */ | |
b50511e4 | 109 | __load_psw_mask(psw_kernel_bits | PSW_MASK_DAT); |
1943f53c MH |
110 | return; |
111 | } | |
112 | } | |
113 | /* We are not online: Do PSW restart on an online CPU */ | |
114 | while (sigp(cpu, sigp_restart) == sigp_busy) | |
115 | cpu_relax(); | |
116 | /* And stop ourself */ | |
117 | while (raw_sigp(stap(), sigp_stop) == sigp_busy) | |
118 | cpu_relax(); | |
119 | for (;;); | |
120 | } | |
121 | ||
2c2df118 HC |
122 | void smp_switch_to_ipl_cpu(void (*func)(void *), void *data) |
123 | { | |
124 | struct _lowcore *lc, *current_lc; | |
125 | struct stack_frame *sf; | |
126 | struct pt_regs *regs; | |
127 | unsigned long sp; | |
128 | ||
129 | if (smp_processor_id() == 0) | |
130 | func(data); | |
b50511e4 MS |
131 | __load_psw_mask(PSW_DEFAULT_KEY | PSW_MASK_BASE | |
132 | PSW_MASK_EA | PSW_MASK_BA); | |
2c2df118 HC |
133 | /* Disable lowcore protection */ |
134 | __ctl_clear_bit(0, 28); | |
135 | current_lc = lowcore_ptr[smp_processor_id()]; | |
136 | lc = lowcore_ptr[0]; | |
137 | if (!lc) | |
138 | lc = current_lc; | |
b50511e4 MS |
139 | lc->restart_psw.mask = |
140 | PSW_DEFAULT_KEY | PSW_MASK_BASE | PSW_MASK_EA | PSW_MASK_BA; | |
2c2df118 HC |
141 | lc->restart_psw.addr = PSW_ADDR_AMODE | (unsigned long) smp_restart_cpu; |
142 | if (!cpu_online(0)) | |
143 | smp_switch_to_cpu(func, data, 0, stap(), __cpu_logical_map[0]); | |
a93b8ec1 | 144 | while (sigp(0, sigp_stop_and_store_status) == sigp_busy) |
2c2df118 HC |
145 | cpu_relax(); |
146 | sp = lc->panic_stack; | |
147 | sp -= sizeof(struct pt_regs); | |
148 | regs = (struct pt_regs *) sp; | |
149 | memcpy(®s->gprs, ¤t_lc->gpregs_save_area, sizeof(regs->gprs)); | |
3931723f | 150 | regs->psw = current_lc->psw_save_area; |
2c2df118 HC |
151 | sp -= STACK_FRAME_OVERHEAD; |
152 | sf = (struct stack_frame *) sp; | |
3931723f | 153 | sf->back_chain = 0; |
2c2df118 HC |
154 | smp_switch_to_cpu(func, data, sp, stap(), __cpu_logical_map[0]); |
155 | } | |
156 | ||
85ac7ca5 MS |
157 | static void smp_stop_cpu(void) |
158 | { | |
159 | while (sigp(smp_processor_id(), sigp_stop) == sigp_busy) | |
160 | cpu_relax(); | |
161 | } | |
162 | ||
677d7623 | 163 | void smp_send_stop(void) |
1da177e4 | 164 | { |
85ac7ca5 MS |
165 | cpumask_t cpumask; |
166 | int cpu; | |
167 | u64 end; | |
1da177e4 | 168 | |
677d7623 | 169 | /* Disable all interrupts/machine checks */ |
b50511e4 | 170 | __load_psw_mask(psw_kernel_bits | PSW_MASK_DAT); |
3324e60a | 171 | trace_hardirqs_off(); |
1da177e4 | 172 | |
85ac7ca5 MS |
173 | cpumask_copy(&cpumask, cpu_online_mask); |
174 | cpumask_clear_cpu(smp_processor_id(), &cpumask); | |
175 | ||
176 | if (oops_in_progress) { | |
177 | /* | |
178 | * Give the other cpus the opportunity to complete | |
179 | * outstanding interrupts before stopping them. | |
180 | */ | |
181 | end = get_clock() + (1000000UL << 12); | |
182 | for_each_cpu(cpu, &cpumask) { | |
183 | set_bit(ec_stop_cpu, (unsigned long *) | |
184 | &lowcore_ptr[cpu]->ext_call_fast); | |
185 | while (sigp(cpu, sigp_emergency_signal) == sigp_busy && | |
186 | get_clock() < end) | |
187 | cpu_relax(); | |
188 | } | |
189 | while (get_clock() < end) { | |
190 | for_each_cpu(cpu, &cpumask) | |
191 | if (cpu_stopped(cpu)) | |
192 | cpumask_clear_cpu(cpu, &cpumask); | |
193 | if (cpumask_empty(&cpumask)) | |
194 | break; | |
195 | cpu_relax(); | |
196 | } | |
197 | } | |
1da177e4 | 198 | |
85ac7ca5 MS |
199 | /* stop all processors */ |
200 | for_each_cpu(cpu, &cpumask) { | |
201 | while (sigp(cpu, sigp_stop) == sigp_busy) | |
202 | cpu_relax(); | |
5c0b912e | 203 | while (!cpu_stopped(cpu)) |
c6b5b847 HC |
204 | cpu_relax(); |
205 | } | |
206 | } | |
207 | ||
1da177e4 LT |
208 | /* |
209 | * This is the main routine where commands issued by other | |
210 | * cpus are handled. | |
211 | */ | |
212 | ||
f6649a7e MS |
213 | static void do_ext_call_interrupt(unsigned int ext_int_code, |
214 | unsigned int param32, unsigned long param64) | |
1da177e4 | 215 | { |
39ce010d | 216 | unsigned long bits; |
1da177e4 | 217 | |
272f01bf | 218 | if ((ext_int_code & 0xffff) == 0x1202) |
2a3a2d66 HC |
219 | kstat_cpu(smp_processor_id()).irqs[EXTINT_EXC]++; |
220 | else | |
221 | kstat_cpu(smp_processor_id()).irqs[EXTINT_EMS]++; | |
39ce010d HC |
222 | /* |
223 | * handle bit signal external calls | |
39ce010d | 224 | */ |
1da177e4 LT |
225 | bits = xchg(&S390_lowcore.ext_call_fast, 0); |
226 | ||
85ac7ca5 MS |
227 | if (test_bit(ec_stop_cpu, &bits)) |
228 | smp_stop_cpu(); | |
229 | ||
184748cc PZ |
230 | if (test_bit(ec_schedule, &bits)) |
231 | scheduler_ipi(); | |
232 | ||
39ce010d | 233 | if (test_bit(ec_call_function, &bits)) |
ca9fc75a HC |
234 | generic_smp_call_function_interrupt(); |
235 | ||
236 | if (test_bit(ec_call_function_single, &bits)) | |
237 | generic_smp_call_function_single_interrupt(); | |
85ac7ca5 | 238 | |
1da177e4 LT |
239 | } |
240 | ||
241 | /* | |
242 | * Send an external call sigp to another cpu and return without waiting | |
243 | * for its completion. | |
244 | */ | |
a93b8ec1 | 245 | static void smp_ext_bitcall(int cpu, int sig) |
1da177e4 | 246 | { |
d98e19cc MS |
247 | int order; |
248 | ||
39ce010d HC |
249 | /* |
250 | * Set signaling bit in lowcore of target cpu and kick it | |
251 | */ | |
1da177e4 | 252 | set_bit(sig, (unsigned long *) &lowcore_ptr[cpu]->ext_call_fast); |
d98e19cc MS |
253 | while (1) { |
254 | order = smp_vcpu_scheduled(cpu) ? | |
255 | sigp_external_call : sigp_emergency_signal; | |
256 | if (sigp(cpu, order) != sigp_busy) | |
257 | break; | |
1da177e4 | 258 | udelay(10); |
d98e19cc | 259 | } |
1da177e4 LT |
260 | } |
261 | ||
630cd046 | 262 | void arch_send_call_function_ipi_mask(const struct cpumask *mask) |
ca9fc75a HC |
263 | { |
264 | int cpu; | |
265 | ||
630cd046 | 266 | for_each_cpu(cpu, mask) |
ca9fc75a HC |
267 | smp_ext_bitcall(cpu, ec_call_function); |
268 | } | |
269 | ||
270 | void arch_send_call_function_single_ipi(int cpu) | |
271 | { | |
272 | smp_ext_bitcall(cpu, ec_call_function_single); | |
273 | } | |
274 | ||
347a8dc3 | 275 | #ifndef CONFIG_64BIT |
1da177e4 LT |
276 | /* |
277 | * this function sends a 'purge tlb' signal to another CPU. | |
278 | */ | |
a806170e | 279 | static void smp_ptlb_callback(void *info) |
1da177e4 | 280 | { |
ba8a9229 | 281 | __tlb_flush_local(); |
1da177e4 LT |
282 | } |
283 | ||
284 | void smp_ptlb_all(void) | |
285 | { | |
15c8b6c1 | 286 | on_each_cpu(smp_ptlb_callback, NULL, 1); |
1da177e4 LT |
287 | } |
288 | EXPORT_SYMBOL(smp_ptlb_all); | |
347a8dc3 | 289 | #endif /* ! CONFIG_64BIT */ |
1da177e4 LT |
290 | |
291 | /* | |
292 | * this function sends a 'reschedule' IPI to another CPU. | |
293 | * it goes straight through and wastes no time serializing | |
294 | * anything. Worst case is that we lose a reschedule ... | |
295 | */ | |
296 | void smp_send_reschedule(int cpu) | |
297 | { | |
39ce010d | 298 | smp_ext_bitcall(cpu, ec_schedule); |
1da177e4 LT |
299 | } |
300 | ||
301 | /* | |
302 | * parameter area for the set/clear control bit callbacks | |
303 | */ | |
94c12cc7 | 304 | struct ec_creg_mask_parms { |
1da177e4 LT |
305 | unsigned long orvals[16]; |
306 | unsigned long andvals[16]; | |
94c12cc7 | 307 | }; |
1da177e4 LT |
308 | |
309 | /* | |
310 | * callback for setting/clearing control bits | |
311 | */ | |
39ce010d HC |
312 | static void smp_ctl_bit_callback(void *info) |
313 | { | |
94c12cc7 | 314 | struct ec_creg_mask_parms *pp = info; |
1da177e4 LT |
315 | unsigned long cregs[16]; |
316 | int i; | |
39ce010d | 317 | |
94c12cc7 MS |
318 | __ctl_store(cregs, 0, 15); |
319 | for (i = 0; i <= 15; i++) | |
1da177e4 | 320 | cregs[i] = (cregs[i] & pp->andvals[i]) | pp->orvals[i]; |
94c12cc7 | 321 | __ctl_load(cregs, 0, 15); |
1da177e4 LT |
322 | } |
323 | ||
324 | /* | |
325 | * Set a bit in a control register of all cpus | |
326 | */ | |
94c12cc7 MS |
327 | void smp_ctl_set_bit(int cr, int bit) |
328 | { | |
329 | struct ec_creg_mask_parms parms; | |
1da177e4 | 330 | |
94c12cc7 MS |
331 | memset(&parms.orvals, 0, sizeof(parms.orvals)); |
332 | memset(&parms.andvals, 0xff, sizeof(parms.andvals)); | |
859c9651 | 333 | parms.orvals[cr] = 1UL << bit; |
15c8b6c1 | 334 | on_each_cpu(smp_ctl_bit_callback, &parms, 1); |
1da177e4 | 335 | } |
39ce010d | 336 | EXPORT_SYMBOL(smp_ctl_set_bit); |
1da177e4 LT |
337 | |
338 | /* | |
339 | * Clear a bit in a control register of all cpus | |
340 | */ | |
94c12cc7 MS |
341 | void smp_ctl_clear_bit(int cr, int bit) |
342 | { | |
343 | struct ec_creg_mask_parms parms; | |
1da177e4 | 344 | |
94c12cc7 MS |
345 | memset(&parms.orvals, 0, sizeof(parms.orvals)); |
346 | memset(&parms.andvals, 0xff, sizeof(parms.andvals)); | |
859c9651 | 347 | parms.andvals[cr] = ~(1UL << bit); |
15c8b6c1 | 348 | on_each_cpu(smp_ctl_bit_callback, &parms, 1); |
1da177e4 | 349 | } |
39ce010d | 350 | EXPORT_SYMBOL(smp_ctl_clear_bit); |
1da177e4 | 351 | |
60a0c68d | 352 | #if defined(CONFIG_ZFCPDUMP) || defined(CONFIG_CRASH_DUMP) |
411ed322 | 353 | |
285f6722 | 354 | static void __init smp_get_save_area(unsigned int cpu, unsigned int phy_cpu) |
411ed322 | 355 | { |
60a0c68d MH |
356 | if (ipl_info.type != IPL_TYPE_FCP_DUMP && !OLDMEM_BASE) |
357 | return; | |
358 | if (is_kdump_kernel()) | |
411ed322 | 359 | return; |
285f6722 | 360 | if (cpu >= NR_CPUS) { |
395d31d4 MS |
361 | pr_warning("CPU %i exceeds the maximum %i and is excluded from " |
362 | "the dump\n", cpu, NR_CPUS - 1); | |
285f6722 | 363 | return; |
411ed322 | 364 | } |
f64ca217 | 365 | zfcpdump_save_areas[cpu] = kmalloc(sizeof(struct save_area), GFP_KERNEL); |
a93b8ec1 | 366 | while (raw_sigp(phy_cpu, sigp_stop_and_store_status) == sigp_busy) |
285f6722 | 367 | cpu_relax(); |
92fe3132 MH |
368 | memcpy_real(zfcpdump_save_areas[cpu], |
369 | (void *)(unsigned long) store_prefix() + SAVE_AREA_BASE, | |
370 | sizeof(struct save_area)); | |
411ed322 MH |
371 | } |
372 | ||
f64ca217 | 373 | struct save_area *zfcpdump_save_areas[NR_CPUS + 1]; |
411ed322 MH |
374 | EXPORT_SYMBOL_GPL(zfcpdump_save_areas); |
375 | ||
376 | #else | |
285f6722 HC |
377 | |
378 | static inline void smp_get_save_area(unsigned int cpu, unsigned int phy_cpu) { } | |
379 | ||
59f2e69d | 380 | #endif /* CONFIG_ZFCPDUMP */ |
411ed322 | 381 | |
08d07968 HC |
382 | static int cpu_known(int cpu_id) |
383 | { | |
384 | int cpu; | |
385 | ||
386 | for_each_present_cpu(cpu) { | |
387 | if (__cpu_logical_map[cpu] == cpu_id) | |
388 | return 1; | |
389 | } | |
390 | return 0; | |
391 | } | |
392 | ||
393 | static int smp_rescan_cpus_sigp(cpumask_t avail) | |
394 | { | |
395 | int cpu_id, logical_cpu; | |
396 | ||
93632d1b RR |
397 | logical_cpu = cpumask_first(&avail); |
398 | if (logical_cpu >= nr_cpu_ids) | |
08d07968 | 399 | return 0; |
4bb5e07b | 400 | for (cpu_id = 0; cpu_id <= MAX_CPU_ADDRESS; cpu_id++) { |
08d07968 HC |
401 | if (cpu_known(cpu_id)) |
402 | continue; | |
403 | __cpu_logical_map[logical_cpu] = cpu_id; | |
83a24e32 | 404 | cpu_set_polarization(logical_cpu, POLARIZATION_UNKNOWN); |
08d07968 HC |
405 | if (!cpu_stopped(logical_cpu)) |
406 | continue; | |
0f1959f5 | 407 | set_cpu_present(logical_cpu, true); |
08d07968 | 408 | smp_cpu_state[logical_cpu] = CPU_STATE_CONFIGURED; |
93632d1b RR |
409 | logical_cpu = cpumask_next(logical_cpu, &avail); |
410 | if (logical_cpu >= nr_cpu_ids) | |
08d07968 HC |
411 | break; |
412 | } | |
413 | return 0; | |
414 | } | |
415 | ||
48483b32 | 416 | static int smp_rescan_cpus_sclp(cpumask_t avail) |
08d07968 HC |
417 | { |
418 | struct sclp_cpu_info *info; | |
419 | int cpu_id, logical_cpu, cpu; | |
420 | int rc; | |
421 | ||
93632d1b RR |
422 | logical_cpu = cpumask_first(&avail); |
423 | if (logical_cpu >= nr_cpu_ids) | |
08d07968 | 424 | return 0; |
48483b32 | 425 | info = kmalloc(sizeof(*info), GFP_KERNEL); |
08d07968 HC |
426 | if (!info) |
427 | return -ENOMEM; | |
428 | rc = sclp_get_cpu_info(info); | |
429 | if (rc) | |
430 | goto out; | |
431 | for (cpu = 0; cpu < info->combined; cpu++) { | |
432 | if (info->has_cpu_type && info->cpu[cpu].type != smp_cpu_type) | |
433 | continue; | |
434 | cpu_id = info->cpu[cpu].address; | |
435 | if (cpu_known(cpu_id)) | |
436 | continue; | |
437 | __cpu_logical_map[logical_cpu] = cpu_id; | |
83a24e32 | 438 | cpu_set_polarization(logical_cpu, POLARIZATION_UNKNOWN); |
0f1959f5 | 439 | set_cpu_present(logical_cpu, true); |
08d07968 HC |
440 | if (cpu >= info->configured) |
441 | smp_cpu_state[logical_cpu] = CPU_STATE_STANDBY; | |
442 | else | |
443 | smp_cpu_state[logical_cpu] = CPU_STATE_CONFIGURED; | |
93632d1b RR |
444 | logical_cpu = cpumask_next(logical_cpu, &avail); |
445 | if (logical_cpu >= nr_cpu_ids) | |
08d07968 HC |
446 | break; |
447 | } | |
448 | out: | |
48483b32 | 449 | kfree(info); |
08d07968 HC |
450 | return rc; |
451 | } | |
452 | ||
1e489518 | 453 | static int __smp_rescan_cpus(void) |
08d07968 HC |
454 | { |
455 | cpumask_t avail; | |
456 | ||
0f1959f5 | 457 | cpumask_xor(&avail, cpu_possible_mask, cpu_present_mask); |
08d07968 HC |
458 | if (smp_use_sigp_detection) |
459 | return smp_rescan_cpus_sigp(avail); | |
460 | else | |
461 | return smp_rescan_cpus_sclp(avail); | |
1da177e4 LT |
462 | } |
463 | ||
48483b32 HC |
464 | static void __init smp_detect_cpus(void) |
465 | { | |
466 | unsigned int cpu, c_cpus, s_cpus; | |
467 | struct sclp_cpu_info *info; | |
468 | u16 boot_cpu_addr, cpu_addr; | |
469 | ||
470 | c_cpus = 1; | |
471 | s_cpus = 0; | |
7b468488 | 472 | boot_cpu_addr = __cpu_logical_map[0]; |
48483b32 HC |
473 | info = kmalloc(sizeof(*info), GFP_KERNEL); |
474 | if (!info) | |
475 | panic("smp_detect_cpus failed to allocate memory\n"); | |
60a0c68d MH |
476 | #ifdef CONFIG_CRASH_DUMP |
477 | if (OLDMEM_BASE && !is_kdump_kernel()) { | |
478 | struct save_area *save_area; | |
479 | ||
480 | save_area = kmalloc(sizeof(*save_area), GFP_KERNEL); | |
481 | if (!save_area) | |
482 | panic("could not allocate memory for save area\n"); | |
483 | copy_oldmem_page(1, (void *) save_area, sizeof(*save_area), | |
484 | 0x200, 0); | |
485 | zfcpdump_save_areas[0] = save_area; | |
486 | } | |
487 | #endif | |
48483b32 HC |
488 | /* Use sigp detection algorithm if sclp doesn't work. */ |
489 | if (sclp_get_cpu_info(info)) { | |
490 | smp_use_sigp_detection = 1; | |
4bb5e07b | 491 | for (cpu = 0; cpu <= MAX_CPU_ADDRESS; cpu++) { |
48483b32 HC |
492 | if (cpu == boot_cpu_addr) |
493 | continue; | |
a93b8ec1 | 494 | if (!raw_cpu_stopped(cpu)) |
48483b32 HC |
495 | continue; |
496 | smp_get_save_area(c_cpus, cpu); | |
497 | c_cpus++; | |
498 | } | |
499 | goto out; | |
500 | } | |
501 | ||
502 | if (info->has_cpu_type) { | |
503 | for (cpu = 0; cpu < info->combined; cpu++) { | |
504 | if (info->cpu[cpu].address == boot_cpu_addr) { | |
505 | smp_cpu_type = info->cpu[cpu].type; | |
506 | break; | |
507 | } | |
508 | } | |
509 | } | |
510 | ||
511 | for (cpu = 0; cpu < info->combined; cpu++) { | |
512 | if (info->has_cpu_type && info->cpu[cpu].type != smp_cpu_type) | |
513 | continue; | |
514 | cpu_addr = info->cpu[cpu].address; | |
515 | if (cpu_addr == boot_cpu_addr) | |
516 | continue; | |
a93b8ec1 | 517 | if (!raw_cpu_stopped(cpu_addr)) { |
48483b32 HC |
518 | s_cpus++; |
519 | continue; | |
520 | } | |
521 | smp_get_save_area(c_cpus, cpu_addr); | |
522 | c_cpus++; | |
523 | } | |
524 | out: | |
525 | kfree(info); | |
395d31d4 | 526 | pr_info("%d configured CPUs, %d standby CPUs\n", c_cpus, s_cpus); |
9d40d2e3 | 527 | get_online_cpus(); |
1e489518 | 528 | __smp_rescan_cpus(); |
9d40d2e3 | 529 | put_online_cpus(); |
48483b32 HC |
530 | } |
531 | ||
1da177e4 | 532 | /* |
39ce010d | 533 | * Activate a secondary processor. |
1da177e4 | 534 | */ |
ea1f4eec | 535 | int __cpuinit start_secondary(void *cpuvoid) |
1da177e4 | 536 | { |
39ce010d | 537 | cpu_init(); |
5bfb5d69 | 538 | preempt_disable(); |
39ce010d | 539 | init_cpu_timer(); |
39ce010d | 540 | init_cpu_vtimer(); |
29b08d2b HC |
541 | pfault_init(); |
542 | ||
e545a614 | 543 | notify_cpu_starting(smp_processor_id()); |
ca9fc75a | 544 | ipi_call_lock(); |
0f1959f5 | 545 | set_cpu_online(smp_processor_id(), true); |
ca9fc75a | 546 | ipi_call_unlock(); |
7dd6b334 | 547 | __ctl_clear_bit(0, 28); /* Disable lowcore protection */ |
b50511e4 MS |
548 | S390_lowcore.restart_psw.mask = |
549 | PSW_DEFAULT_KEY | PSW_MASK_BASE | PSW_MASK_EA | PSW_MASK_BA; | |
7dd6b334 MH |
550 | S390_lowcore.restart_psw.addr = |
551 | PSW_ADDR_AMODE | (unsigned long) psw_restart_int_handler; | |
552 | __ctl_set_bit(0, 28); /* Enable lowcore protection */ | |
cc34321d HC |
553 | /* |
554 | * Wait until the cpu which brought this one up marked it | |
555 | * active before enabling interrupts. | |
556 | */ | |
557 | while (!cpumask_test_cpu(smp_processor_id(), cpu_active_mask)) | |
558 | cpu_relax(); | |
1da177e4 | 559 | local_irq_enable(); |
39ce010d HC |
560 | /* cpu_idle will call schedule for us */ |
561 | cpu_idle(); | |
562 | return 0; | |
1da177e4 LT |
563 | } |
564 | ||
f230886b HC |
565 | struct create_idle { |
566 | struct work_struct work; | |
567 | struct task_struct *idle; | |
568 | struct completion done; | |
569 | int cpu; | |
570 | }; | |
571 | ||
572 | static void __cpuinit smp_fork_idle(struct work_struct *work) | |
1da177e4 | 573 | { |
f230886b | 574 | struct create_idle *c_idle; |
1da177e4 | 575 | |
f230886b HC |
576 | c_idle = container_of(work, struct create_idle, work); |
577 | c_idle->idle = fork_idle(c_idle->cpu); | |
578 | complete(&c_idle->done); | |
1da177e4 LT |
579 | } |
580 | ||
1cb6bb4b HC |
581 | static int __cpuinit smp_alloc_lowcore(int cpu) |
582 | { | |
583 | unsigned long async_stack, panic_stack; | |
584 | struct _lowcore *lowcore; | |
1cb6bb4b | 585 | |
3fd26a77 | 586 | lowcore = (void *) __get_free_pages(GFP_KERNEL | GFP_DMA, LC_ORDER); |
1cb6bb4b HC |
587 | if (!lowcore) |
588 | return -ENOMEM; | |
589 | async_stack = __get_free_pages(GFP_KERNEL, ASYNC_ORDER); | |
1cb6bb4b | 590 | panic_stack = __get_free_page(GFP_KERNEL); |
591bb4f6 HC |
591 | if (!panic_stack || !async_stack) |
592 | goto out; | |
98c7b388 HC |
593 | memcpy(lowcore, &S390_lowcore, 512); |
594 | memset((char *)lowcore + 512, 0, sizeof(*lowcore) - 512); | |
1cb6bb4b HC |
595 | lowcore->async_stack = async_stack + ASYNC_SIZE; |
596 | lowcore->panic_stack = panic_stack + PAGE_SIZE; | |
b50511e4 MS |
597 | lowcore->restart_psw.mask = |
598 | PSW_DEFAULT_KEY | PSW_MASK_BASE | PSW_MASK_EA | PSW_MASK_BA; | |
7dd6b334 MH |
599 | lowcore->restart_psw.addr = |
600 | PSW_ADDR_AMODE | (unsigned long) restart_int_handler; | |
601 | if (user_mode != HOME_SPACE_MODE) | |
602 | lowcore->restart_psw.mask |= PSW_ASC_HOME; | |
1cb6bb4b HC |
603 | #ifndef CONFIG_64BIT |
604 | if (MACHINE_HAS_IEEE) { | |
605 | unsigned long save_area; | |
606 | ||
607 | save_area = get_zeroed_page(GFP_KERNEL); | |
608 | if (!save_area) | |
33b1d09e | 609 | goto out; |
1cb6bb4b HC |
610 | lowcore->extended_save_area_addr = (u32) save_area; |
611 | } | |
c742b31c MS |
612 | #else |
613 | if (vdso_alloc_per_cpu(cpu, lowcore)) | |
614 | goto out; | |
1cb6bb4b HC |
615 | #endif |
616 | lowcore_ptr[cpu] = lowcore; | |
617 | return 0; | |
618 | ||
591bb4f6 | 619 | out: |
33b1d09e | 620 | free_page(panic_stack); |
1cb6bb4b | 621 | free_pages(async_stack, ASYNC_ORDER); |
3fd26a77 | 622 | free_pages((unsigned long) lowcore, LC_ORDER); |
1cb6bb4b HC |
623 | return -ENOMEM; |
624 | } | |
625 | ||
1cb6bb4b HC |
626 | static void smp_free_lowcore(int cpu) |
627 | { | |
628 | struct _lowcore *lowcore; | |
1cb6bb4b | 629 | |
1cb6bb4b HC |
630 | lowcore = lowcore_ptr[cpu]; |
631 | #ifndef CONFIG_64BIT | |
632 | if (MACHINE_HAS_IEEE) | |
633 | free_page((unsigned long) lowcore->extended_save_area_addr); | |
c742b31c MS |
634 | #else |
635 | vdso_free_per_cpu(cpu, lowcore); | |
1cb6bb4b HC |
636 | #endif |
637 | free_page(lowcore->panic_stack - PAGE_SIZE); | |
638 | free_pages(lowcore->async_stack - ASYNC_SIZE, ASYNC_ORDER); | |
3fd26a77 | 639 | free_pages((unsigned long) lowcore, LC_ORDER); |
1cb6bb4b HC |
640 | lowcore_ptr[cpu] = NULL; |
641 | } | |
1cb6bb4b | 642 | |
1da177e4 | 643 | /* Upping and downing of CPUs */ |
1cb6bb4b | 644 | int __cpuinit __cpu_up(unsigned int cpu) |
1da177e4 | 645 | { |
39ce010d | 646 | struct _lowcore *cpu_lowcore; |
f230886b | 647 | struct create_idle c_idle; |
a93b8ec1 | 648 | struct task_struct *idle; |
1da177e4 | 649 | struct stack_frame *sf; |
d0d3cdf4 | 650 | u32 lowcore; |
a93b8ec1 | 651 | int ccode; |
1da177e4 | 652 | |
08d07968 HC |
653 | if (smp_cpu_state[cpu] != CPU_STATE_CONFIGURED) |
654 | return -EIO; | |
f230886b HC |
655 | idle = current_set[cpu]; |
656 | if (!idle) { | |
657 | c_idle.done = COMPLETION_INITIALIZER_ONSTACK(c_idle.done); | |
658 | INIT_WORK_ONSTACK(&c_idle.work, smp_fork_idle); | |
659 | c_idle.cpu = cpu; | |
660 | schedule_work(&c_idle.work); | |
661 | wait_for_completion(&c_idle.done); | |
662 | if (IS_ERR(c_idle.idle)) | |
663 | return PTR_ERR(c_idle.idle); | |
664 | idle = c_idle.idle; | |
665 | current_set[cpu] = c_idle.idle; | |
666 | } | |
da7f51c1 | 667 | init_idle(idle, cpu); |
1cb6bb4b HC |
668 | if (smp_alloc_lowcore(cpu)) |
669 | return -ENOMEM; | |
d0d3cdf4 | 670 | do { |
a93b8ec1 | 671 | ccode = sigp(cpu, sigp_initial_cpu_reset); |
d0d3cdf4 HC |
672 | if (ccode == sigp_busy) |
673 | udelay(10); | |
674 | if (ccode == sigp_not_operational) | |
675 | goto err_out; | |
676 | } while (ccode == sigp_busy); | |
677 | ||
678 | lowcore = (u32)(unsigned long)lowcore_ptr[cpu]; | |
a93b8ec1 | 679 | while (sigp_p(lowcore, cpu, sigp_set_prefix) == sigp_busy) |
d0d3cdf4 | 680 | udelay(10); |
1da177e4 | 681 | |
39ce010d | 682 | cpu_lowcore = lowcore_ptr[cpu]; |
1da177e4 | 683 | cpu_lowcore->kernel_stack = (unsigned long) |
39ce010d | 684 | task_stack_page(idle) + THREAD_SIZE; |
1cb6bb4b | 685 | cpu_lowcore->thread_info = (unsigned long) task_thread_info(idle); |
1da177e4 LT |
686 | sf = (struct stack_frame *) (cpu_lowcore->kernel_stack |
687 | - sizeof(struct pt_regs) | |
688 | - sizeof(struct stack_frame)); | |
689 | memset(sf, 0, sizeof(struct stack_frame)); | |
690 | sf->gprs[9] = (unsigned long) sf; | |
c5328901 | 691 | cpu_lowcore->gpregs_save_area[15] = (unsigned long) sf; |
24d3e210 | 692 | __ctl_store(cpu_lowcore->cregs_save_area, 0, 15); |
050eef36 | 693 | atomic_inc(&init_mm.context.attach_count); |
94c12cc7 MS |
694 | asm volatile( |
695 | " stam 0,15,0(%0)" | |
696 | : : "a" (&cpu_lowcore->access_regs_save_area) : "memory"); | |
1da177e4 | 697 | cpu_lowcore->percpu_offset = __per_cpu_offset[cpu]; |
39ce010d | 698 | cpu_lowcore->current_task = (unsigned long) idle; |
7b468488 | 699 | cpu_lowcore->cpu_nr = cpu; |
591bb4f6 | 700 | cpu_lowcore->kernel_asce = S390_lowcore.kernel_asce; |
25097bf1 | 701 | cpu_lowcore->machine_flags = S390_lowcore.machine_flags; |
dfd9f7ab | 702 | cpu_lowcore->ftrace_func = S390_lowcore.ftrace_func; |
14375bc4 MS |
703 | memcpy(cpu_lowcore->stfle_fac_list, S390_lowcore.stfle_fac_list, |
704 | MAX_FACILITY_BIT/8); | |
1da177e4 | 705 | eieio(); |
699ff13f | 706 | |
a93b8ec1 | 707 | while (sigp(cpu, sigp_restart) == sigp_busy) |
699ff13f | 708 | udelay(10); |
1da177e4 LT |
709 | |
710 | while (!cpu_online(cpu)) | |
711 | cpu_relax(); | |
712 | return 0; | |
d0d3cdf4 HC |
713 | |
714 | err_out: | |
715 | smp_free_lowcore(cpu); | |
716 | return -EIO; | |
1da177e4 LT |
717 | } |
718 | ||
48483b32 | 719 | static int __init setup_possible_cpus(char *s) |
255acee7 | 720 | { |
48483b32 | 721 | int pcpus, cpu; |
255acee7 | 722 | |
48483b32 | 723 | pcpus = simple_strtoul(s, NULL, 0); |
88e01285 HC |
724 | init_cpu_possible(cpumask_of(0)); |
725 | for (cpu = 1; cpu < pcpus && cpu < nr_cpu_ids; cpu++) | |
def6cfb7 | 726 | set_cpu_possible(cpu, true); |
37a33026 HC |
727 | return 0; |
728 | } | |
729 | early_param("possible_cpus", setup_possible_cpus); | |
730 | ||
48483b32 HC |
731 | #ifdef CONFIG_HOTPLUG_CPU |
732 | ||
39ce010d | 733 | int __cpu_disable(void) |
1da177e4 | 734 | { |
94c12cc7 | 735 | struct ec_creg_mask_parms cr_parms; |
f3705136 | 736 | int cpu = smp_processor_id(); |
1da177e4 | 737 | |
0f1959f5 | 738 | set_cpu_online(cpu, false); |
1da177e4 | 739 | |
1da177e4 | 740 | /* Disable pfault pseudo page faults on this cpu. */ |
29b08d2b | 741 | pfault_fini(); |
1da177e4 | 742 | |
94c12cc7 MS |
743 | memset(&cr_parms.orvals, 0, sizeof(cr_parms.orvals)); |
744 | memset(&cr_parms.andvals, 0xff, sizeof(cr_parms.andvals)); | |
1da177e4 | 745 | |
94c12cc7 | 746 | /* disable all external interrupts */ |
1da177e4 | 747 | cr_parms.orvals[0] = 0; |
5bd41878 | 748 | cr_parms.andvals[0] = ~(1 << 15 | 1 << 14 | 1 << 13 | 1 << 11 | |
cadfce72 JG |
749 | 1 << 10 | 1 << 9 | 1 << 6 | 1 << 5 | |
750 | 1 << 4); | |
1da177e4 | 751 | /* disable all I/O interrupts */ |
1da177e4 | 752 | cr_parms.orvals[6] = 0; |
39ce010d HC |
753 | cr_parms.andvals[6] = ~(1 << 31 | 1 << 30 | 1 << 29 | 1 << 28 | |
754 | 1 << 27 | 1 << 26 | 1 << 25 | 1 << 24); | |
1da177e4 | 755 | /* disable most machine checks */ |
1da177e4 | 756 | cr_parms.orvals[14] = 0; |
39ce010d HC |
757 | cr_parms.andvals[14] = ~(1 << 28 | 1 << 27 | 1 << 26 | |
758 | 1 << 25 | 1 << 24); | |
94c12cc7 | 759 | |
1da177e4 LT |
760 | smp_ctl_bit_callback(&cr_parms); |
761 | ||
1da177e4 LT |
762 | return 0; |
763 | } | |
764 | ||
39ce010d | 765 | void __cpu_die(unsigned int cpu) |
1da177e4 LT |
766 | { |
767 | /* Wait until target cpu is down */ | |
5c0b912e | 768 | while (!cpu_stopped(cpu)) |
1da177e4 | 769 | cpu_relax(); |
a93b8ec1 | 770 | while (sigp_p(0, cpu, sigp_set_prefix) == sigp_busy) |
4f8048ee | 771 | udelay(10); |
1cb6bb4b | 772 | smp_free_lowcore(cpu); |
050eef36 | 773 | atomic_dec(&init_mm.context.attach_count); |
1da177e4 LT |
774 | } |
775 | ||
b456d94a | 776 | void __noreturn cpu_die(void) |
1da177e4 LT |
777 | { |
778 | idle_task_exit(); | |
a93b8ec1 | 779 | while (sigp(smp_processor_id(), sigp_stop) == sigp_busy) |
f8501ba7 | 780 | cpu_relax(); |
39ce010d | 781 | for (;;); |
1da177e4 LT |
782 | } |
783 | ||
255acee7 HC |
784 | #endif /* CONFIG_HOTPLUG_CPU */ |
785 | ||
1da177e4 LT |
786 | void __init smp_prepare_cpus(unsigned int max_cpus) |
787 | { | |
591bb4f6 HC |
788 | #ifndef CONFIG_64BIT |
789 | unsigned long save_area = 0; | |
790 | #endif | |
791 | unsigned long async_stack, panic_stack; | |
792 | struct _lowcore *lowcore; | |
39ce010d | 793 | |
48483b32 HC |
794 | smp_detect_cpus(); |
795 | ||
39ce010d HC |
796 | /* request the 0x1201 emergency signal external interrupt */ |
797 | if (register_external_interrupt(0x1201, do_ext_call_interrupt) != 0) | |
798 | panic("Couldn't request external interrupt 0x1201"); | |
d98e19cc MS |
799 | /* request the 0x1202 external call external interrupt */ |
800 | if (register_external_interrupt(0x1202, do_ext_call_interrupt) != 0) | |
801 | panic("Couldn't request external interrupt 0x1202"); | |
1da177e4 | 802 | |
591bb4f6 | 803 | /* Reallocate current lowcore, but keep its contents. */ |
3fd26a77 | 804 | lowcore = (void *) __get_free_pages(GFP_KERNEL | GFP_DMA, LC_ORDER); |
591bb4f6 HC |
805 | panic_stack = __get_free_page(GFP_KERNEL); |
806 | async_stack = __get_free_pages(GFP_KERNEL, ASYNC_ORDER); | |
c742b31c | 807 | BUG_ON(!lowcore || !panic_stack || !async_stack); |
347a8dc3 | 808 | #ifndef CONFIG_64BIT |
77fa2245 | 809 | if (MACHINE_HAS_IEEE) |
591bb4f6 | 810 | save_area = get_zeroed_page(GFP_KERNEL); |
77fa2245 | 811 | #endif |
591bb4f6 HC |
812 | local_irq_disable(); |
813 | local_mcck_disable(); | |
814 | lowcore_ptr[smp_processor_id()] = lowcore; | |
815 | *lowcore = S390_lowcore; | |
816 | lowcore->panic_stack = panic_stack + PAGE_SIZE; | |
817 | lowcore->async_stack = async_stack + ASYNC_SIZE; | |
818 | #ifndef CONFIG_64BIT | |
819 | if (MACHINE_HAS_IEEE) | |
820 | lowcore->extended_save_area_addr = (u32) save_area; | |
821 | #endif | |
822 | set_prefix((u32)(unsigned long) lowcore); | |
823 | local_mcck_enable(); | |
824 | local_irq_enable(); | |
3a6ba460 HC |
825 | #ifdef CONFIG_64BIT |
826 | if (vdso_alloc_per_cpu(smp_processor_id(), &S390_lowcore)) | |
827 | BUG(); | |
828 | #endif | |
1da177e4 LT |
829 | } |
830 | ||
ea1f4eec | 831 | void __init smp_prepare_boot_cpu(void) |
1da177e4 LT |
832 | { |
833 | BUG_ON(smp_processor_id() != 0); | |
834 | ||
48483b32 | 835 | current_thread_info()->cpu = 0; |
0f1959f5 KM |
836 | set_cpu_present(0, true); |
837 | set_cpu_online(0, true); | |
1da177e4 LT |
838 | S390_lowcore.percpu_offset = __per_cpu_offset[0]; |
839 | current_set[0] = current; | |
08d07968 | 840 | smp_cpu_state[0] = CPU_STATE_CONFIGURED; |
83a24e32 | 841 | cpu_set_polarization(0, POLARIZATION_UNKNOWN); |
1da177e4 LT |
842 | } |
843 | ||
ea1f4eec | 844 | void __init smp_cpus_done(unsigned int max_cpus) |
1da177e4 | 845 | { |
1da177e4 LT |
846 | } |
847 | ||
02beaccc HC |
848 | void __init smp_setup_processor_id(void) |
849 | { | |
850 | S390_lowcore.cpu_nr = 0; | |
851 | __cpu_logical_map[0] = stap(); | |
852 | } | |
853 | ||
1da177e4 LT |
854 | /* |
855 | * the frequency of the profiling timer can be changed | |
856 | * by writing a multiplier value into /proc/profile. | |
857 | * | |
858 | * usually you want to run this on all CPUs ;) | |
859 | */ | |
860 | int setup_profiling_timer(unsigned int multiplier) | |
861 | { | |
39ce010d | 862 | return 0; |
1da177e4 LT |
863 | } |
864 | ||
08d07968 | 865 | #ifdef CONFIG_HOTPLUG_CPU |
8a25a2fd KS |
866 | static ssize_t cpu_configure_show(struct device *dev, |
867 | struct device_attribute *attr, char *buf) | |
08d07968 HC |
868 | { |
869 | ssize_t count; | |
870 | ||
871 | mutex_lock(&smp_cpu_state_mutex); | |
872 | count = sprintf(buf, "%d\n", smp_cpu_state[dev->id]); | |
873 | mutex_unlock(&smp_cpu_state_mutex); | |
874 | return count; | |
875 | } | |
876 | ||
8a25a2fd KS |
877 | static ssize_t cpu_configure_store(struct device *dev, |
878 | struct device_attribute *attr, | |
4a0b2b4d | 879 | const char *buf, size_t count) |
08d07968 HC |
880 | { |
881 | int cpu = dev->id; | |
882 | int val, rc; | |
883 | char delim; | |
884 | ||
885 | if (sscanf(buf, "%d %c", &val, &delim) != 1) | |
886 | return -EINVAL; | |
887 | if (val != 0 && val != 1) | |
888 | return -EINVAL; | |
889 | ||
9d40d2e3 | 890 | get_online_cpus(); |
0b18d318 | 891 | mutex_lock(&smp_cpu_state_mutex); |
08d07968 | 892 | rc = -EBUSY; |
2c2df118 HC |
893 | /* disallow configuration changes of online cpus and cpu 0 */ |
894 | if (cpu_online(cpu) || cpu == 0) | |
08d07968 HC |
895 | goto out; |
896 | rc = 0; | |
897 | switch (val) { | |
898 | case 0: | |
899 | if (smp_cpu_state[cpu] == CPU_STATE_CONFIGURED) { | |
900 | rc = sclp_cpu_deconfigure(__cpu_logical_map[cpu]); | |
c10fde0d | 901 | if (!rc) { |
08d07968 | 902 | smp_cpu_state[cpu] = CPU_STATE_STANDBY; |
83a24e32 | 903 | cpu_set_polarization(cpu, POLARIZATION_UNKNOWN); |
d68bddb7 | 904 | topology_expect_change(); |
c10fde0d | 905 | } |
08d07968 HC |
906 | } |
907 | break; | |
908 | case 1: | |
909 | if (smp_cpu_state[cpu] == CPU_STATE_STANDBY) { | |
910 | rc = sclp_cpu_configure(__cpu_logical_map[cpu]); | |
c10fde0d | 911 | if (!rc) { |
08d07968 | 912 | smp_cpu_state[cpu] = CPU_STATE_CONFIGURED; |
83a24e32 | 913 | cpu_set_polarization(cpu, POLARIZATION_UNKNOWN); |
d68bddb7 | 914 | topology_expect_change(); |
c10fde0d | 915 | } |
08d07968 HC |
916 | } |
917 | break; | |
918 | default: | |
919 | break; | |
920 | } | |
921 | out: | |
08d07968 | 922 | mutex_unlock(&smp_cpu_state_mutex); |
0b18d318 | 923 | put_online_cpus(); |
08d07968 HC |
924 | return rc ? rc : count; |
925 | } | |
8a25a2fd | 926 | static DEVICE_ATTR(configure, 0644, cpu_configure_show, cpu_configure_store); |
08d07968 HC |
927 | #endif /* CONFIG_HOTPLUG_CPU */ |
928 | ||
8a25a2fd KS |
929 | static ssize_t show_cpu_address(struct device *dev, |
930 | struct device_attribute *attr, char *buf) | |
08d07968 HC |
931 | { |
932 | return sprintf(buf, "%d\n", __cpu_logical_map[dev->id]); | |
933 | } | |
8a25a2fd | 934 | static DEVICE_ATTR(address, 0444, show_cpu_address, NULL); |
08d07968 | 935 | |
08d07968 HC |
936 | static struct attribute *cpu_common_attrs[] = { |
937 | #ifdef CONFIG_HOTPLUG_CPU | |
8a25a2fd | 938 | &dev_attr_configure.attr, |
08d07968 | 939 | #endif |
8a25a2fd | 940 | &dev_attr_address.attr, |
08d07968 HC |
941 | NULL, |
942 | }; | |
943 | ||
944 | static struct attribute_group cpu_common_attr_group = { | |
945 | .attrs = cpu_common_attrs, | |
946 | }; | |
1da177e4 | 947 | |
8a25a2fd KS |
948 | static ssize_t show_capability(struct device *dev, |
949 | struct device_attribute *attr, char *buf) | |
2fc2d1e9 HC |
950 | { |
951 | unsigned int capability; | |
952 | int rc; | |
953 | ||
954 | rc = get_cpu_capability(&capability); | |
955 | if (rc) | |
956 | return rc; | |
957 | return sprintf(buf, "%u\n", capability); | |
958 | } | |
8a25a2fd | 959 | static DEVICE_ATTR(capability, 0444, show_capability, NULL); |
2fc2d1e9 | 960 | |
8a25a2fd KS |
961 | static ssize_t show_idle_count(struct device *dev, |
962 | struct device_attribute *attr, char *buf) | |
fae8b22d HC |
963 | { |
964 | struct s390_idle_data *idle; | |
965 | unsigned long long idle_count; | |
e98bbaaf | 966 | unsigned int sequence; |
fae8b22d HC |
967 | |
968 | idle = &per_cpu(s390_idle, dev->id); | |
e98bbaaf MS |
969 | repeat: |
970 | sequence = idle->sequence; | |
971 | smp_rmb(); | |
972 | if (sequence & 1) | |
973 | goto repeat; | |
fae8b22d | 974 | idle_count = idle->idle_count; |
6f430924 MS |
975 | if (idle->idle_enter) |
976 | idle_count++; | |
e98bbaaf MS |
977 | smp_rmb(); |
978 | if (idle->sequence != sequence) | |
979 | goto repeat; | |
fae8b22d HC |
980 | return sprintf(buf, "%llu\n", idle_count); |
981 | } | |
8a25a2fd | 982 | static DEVICE_ATTR(idle_count, 0444, show_idle_count, NULL); |
fae8b22d | 983 | |
8a25a2fd KS |
984 | static ssize_t show_idle_time(struct device *dev, |
985 | struct device_attribute *attr, char *buf) | |
fae8b22d HC |
986 | { |
987 | struct s390_idle_data *idle; | |
6f430924 | 988 | unsigned long long now, idle_time, idle_enter; |
e98bbaaf | 989 | unsigned int sequence; |
fae8b22d HC |
990 | |
991 | idle = &per_cpu(s390_idle, dev->id); | |
6f430924 | 992 | now = get_clock(); |
e98bbaaf MS |
993 | repeat: |
994 | sequence = idle->sequence; | |
995 | smp_rmb(); | |
996 | if (sequence & 1) | |
997 | goto repeat; | |
6f430924 MS |
998 | idle_time = idle->idle_time; |
999 | idle_enter = idle->idle_enter; | |
1000 | if (idle_enter != 0ULL && idle_enter < now) | |
1001 | idle_time += now - idle_enter; | |
e98bbaaf MS |
1002 | smp_rmb(); |
1003 | if (idle->sequence != sequence) | |
1004 | goto repeat; | |
6f430924 | 1005 | return sprintf(buf, "%llu\n", idle_time >> 12); |
fae8b22d | 1006 | } |
8a25a2fd | 1007 | static DEVICE_ATTR(idle_time_us, 0444, show_idle_time, NULL); |
fae8b22d | 1008 | |
08d07968 | 1009 | static struct attribute *cpu_online_attrs[] = { |
8a25a2fd KS |
1010 | &dev_attr_capability.attr, |
1011 | &dev_attr_idle_count.attr, | |
1012 | &dev_attr_idle_time_us.attr, | |
fae8b22d HC |
1013 | NULL, |
1014 | }; | |
1015 | ||
08d07968 HC |
1016 | static struct attribute_group cpu_online_attr_group = { |
1017 | .attrs = cpu_online_attrs, | |
fae8b22d HC |
1018 | }; |
1019 | ||
2fc2d1e9 HC |
1020 | static int __cpuinit smp_cpu_notify(struct notifier_block *self, |
1021 | unsigned long action, void *hcpu) | |
1022 | { | |
1023 | unsigned int cpu = (unsigned int)(long)hcpu; | |
1024 | struct cpu *c = &per_cpu(cpu_devices, cpu); | |
8a25a2fd | 1025 | struct device *s = &c->dev; |
fae8b22d | 1026 | struct s390_idle_data *idle; |
d882ba69 | 1027 | int err = 0; |
2fc2d1e9 HC |
1028 | |
1029 | switch (action) { | |
1030 | case CPU_ONLINE: | |
8bb78442 | 1031 | case CPU_ONLINE_FROZEN: |
fae8b22d | 1032 | idle = &per_cpu(s390_idle, cpu); |
e98bbaaf | 1033 | memset(idle, 0, sizeof(struct s390_idle_data)); |
d882ba69 | 1034 | err = sysfs_create_group(&s->kobj, &cpu_online_attr_group); |
2fc2d1e9 HC |
1035 | break; |
1036 | case CPU_DEAD: | |
8bb78442 | 1037 | case CPU_DEAD_FROZEN: |
08d07968 | 1038 | sysfs_remove_group(&s->kobj, &cpu_online_attr_group); |
2fc2d1e9 HC |
1039 | break; |
1040 | } | |
d882ba69 | 1041 | return notifier_from_errno(err); |
2fc2d1e9 HC |
1042 | } |
1043 | ||
1044 | static struct notifier_block __cpuinitdata smp_cpu_nb = { | |
39ce010d | 1045 | .notifier_call = smp_cpu_notify, |
2fc2d1e9 HC |
1046 | }; |
1047 | ||
2bc89b5e | 1048 | static int __devinit smp_add_present_cpu(int cpu) |
08d07968 HC |
1049 | { |
1050 | struct cpu *c = &per_cpu(cpu_devices, cpu); | |
8a25a2fd | 1051 | struct device *s = &c->dev; |
08d07968 HC |
1052 | int rc; |
1053 | ||
1054 | c->hotpluggable = 1; | |
1055 | rc = register_cpu(c, cpu); | |
1056 | if (rc) | |
1057 | goto out; | |
1058 | rc = sysfs_create_group(&s->kobj, &cpu_common_attr_group); | |
1059 | if (rc) | |
1060 | goto out_cpu; | |
83a24e32 HC |
1061 | if (cpu_online(cpu)) { |
1062 | rc = sysfs_create_group(&s->kobj, &cpu_online_attr_group); | |
1063 | if (rc) | |
1064 | goto out_online; | |
1065 | } | |
1066 | rc = topology_cpu_init(c); | |
1067 | if (rc) | |
1068 | goto out_topology; | |
1069 | return 0; | |
1070 | ||
1071 | out_topology: | |
1072 | if (cpu_online(cpu)) | |
1073 | sysfs_remove_group(&s->kobj, &cpu_online_attr_group); | |
1074 | out_online: | |
08d07968 HC |
1075 | sysfs_remove_group(&s->kobj, &cpu_common_attr_group); |
1076 | out_cpu: | |
1077 | #ifdef CONFIG_HOTPLUG_CPU | |
1078 | unregister_cpu(c); | |
1079 | #endif | |
1080 | out: | |
1081 | return rc; | |
1082 | } | |
1083 | ||
1084 | #ifdef CONFIG_HOTPLUG_CPU | |
1e489518 | 1085 | |
67060d9c | 1086 | int __ref smp_rescan_cpus(void) |
08d07968 HC |
1087 | { |
1088 | cpumask_t newcpus; | |
1089 | int cpu; | |
1090 | int rc; | |
1091 | ||
9d40d2e3 | 1092 | get_online_cpus(); |
0b18d318 | 1093 | mutex_lock(&smp_cpu_state_mutex); |
0f1959f5 | 1094 | cpumask_copy(&newcpus, cpu_present_mask); |
1e489518 | 1095 | rc = __smp_rescan_cpus(); |
08d07968 HC |
1096 | if (rc) |
1097 | goto out; | |
0f1959f5 KM |
1098 | cpumask_andnot(&newcpus, cpu_present_mask, &newcpus); |
1099 | for_each_cpu(cpu, &newcpus) { | |
08d07968 HC |
1100 | rc = smp_add_present_cpu(cpu); |
1101 | if (rc) | |
0f1959f5 | 1102 | set_cpu_present(cpu, false); |
08d07968 HC |
1103 | } |
1104 | rc = 0; | |
1105 | out: | |
08d07968 | 1106 | mutex_unlock(&smp_cpu_state_mutex); |
0b18d318 | 1107 | put_online_cpus(); |
0f1959f5 | 1108 | if (!cpumask_empty(&newcpus)) |
c10fde0d | 1109 | topology_schedule_update(); |
1e489518 HC |
1110 | return rc; |
1111 | } | |
1112 | ||
8a25a2fd KS |
1113 | static ssize_t __ref rescan_store(struct device *dev, |
1114 | struct device_attribute *attr, | |
c9be0a36 | 1115 | const char *buf, |
1e489518 HC |
1116 | size_t count) |
1117 | { | |
1118 | int rc; | |
1119 | ||
1120 | rc = smp_rescan_cpus(); | |
08d07968 HC |
1121 | return rc ? rc : count; |
1122 | } | |
8a25a2fd | 1123 | static DEVICE_ATTR(rescan, 0200, NULL, rescan_store); |
08d07968 HC |
1124 | #endif /* CONFIG_HOTPLUG_CPU */ |
1125 | ||
83a24e32 | 1126 | static int __init s390_smp_init(void) |
1da177e4 | 1127 | { |
83a24e32 | 1128 | int cpu, rc; |
2fc2d1e9 HC |
1129 | |
1130 | register_cpu_notifier(&smp_cpu_nb); | |
08d07968 | 1131 | #ifdef CONFIG_HOTPLUG_CPU |
8a25a2fd | 1132 | rc = device_create_file(cpu_subsys.dev_root, &dev_attr_rescan); |
08d07968 HC |
1133 | if (rc) |
1134 | return rc; | |
1135 | #endif | |
1136 | for_each_present_cpu(cpu) { | |
1137 | rc = smp_add_present_cpu(cpu); | |
fae8b22d HC |
1138 | if (rc) |
1139 | return rc; | |
1da177e4 LT |
1140 | } |
1141 | return 0; | |
1142 | } | |
83a24e32 | 1143 | subsys_initcall(s390_smp_init); |