Commit | Line | Data |
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b2441318 | 1 | // SPDX-License-Identifier: GPL-2.0 |
1da177e4 | 2 | /* |
8b646bd7 | 3 | * SMP related functions |
1da177e4 | 4 | * |
a53c8fab | 5 | * Copyright IBM Corp. 1999, 2012 |
8b646bd7 MS |
6 | * Author(s): Denis Joseph Barrow, |
7 | * Martin Schwidefsky <schwidefsky@de.ibm.com>, | |
8 | * Heiko Carstens <heiko.carstens@de.ibm.com>, | |
1da177e4 | 9 | * |
39ce010d | 10 | * based on other smp stuff by |
1da177e4 LT |
11 | * (c) 1995 Alan Cox, CymruNET Ltd <alan@cymru.net> |
12 | * (c) 1998 Ingo Molnar | |
13 | * | |
8b646bd7 MS |
14 | * The code outside of smp.c uses logical cpu numbers, only smp.c does |
15 | * the translation of logical to physical cpu ids. All new code that | |
16 | * operates on physical cpu numbers needs to go into smp.c. | |
1da177e4 LT |
17 | */ |
18 | ||
395d31d4 MS |
19 | #define KMSG_COMPONENT "cpu" |
20 | #define pr_fmt(fmt) KMSG_COMPONENT ": " fmt | |
21 | ||
f230886b | 22 | #include <linux/workqueue.h> |
af51160e | 23 | #include <linux/bootmem.h> |
3994a52b | 24 | #include <linux/export.h> |
1da177e4 | 25 | #include <linux/init.h> |
1da177e4 | 26 | #include <linux/mm.h> |
4e950f6f | 27 | #include <linux/err.h> |
1da177e4 LT |
28 | #include <linux/spinlock.h> |
29 | #include <linux/kernel_stat.h> | |
1da177e4 | 30 | #include <linux/delay.h> |
1da177e4 | 31 | #include <linux/interrupt.h> |
3324e60a | 32 | #include <linux/irqflags.h> |
1da177e4 | 33 | #include <linux/cpu.h> |
5a0e3ad6 | 34 | #include <linux/slab.h> |
ef8bd77f | 35 | #include <linux/sched/hotplug.h> |
68db0cf1 | 36 | #include <linux/sched/task_stack.h> |
60a0c68d | 37 | #include <linux/crash_dump.h> |
1592a8e4 | 38 | #include <linux/memblock.h> |
00a8f886 | 39 | #include <linux/kprobes.h> |
cbb870c8 | 40 | #include <asm/asm-offsets.h> |
1ec2772e | 41 | #include <asm/diag.h> |
1e3cab2f HC |
42 | #include <asm/switch_to.h> |
43 | #include <asm/facility.h> | |
46b05d26 | 44 | #include <asm/ipl.h> |
2b67fc46 | 45 | #include <asm/setup.h> |
1da177e4 | 46 | #include <asm/irq.h> |
1da177e4 | 47 | #include <asm/tlbflush.h> |
27f6b416 | 48 | #include <asm/vtimer.h> |
411ed322 | 49 | #include <asm/lowcore.h> |
08d07968 | 50 | #include <asm/sclp.h> |
c742b31c | 51 | #include <asm/vdso.h> |
3ab121ab | 52 | #include <asm/debug.h> |
4857d4bb | 53 | #include <asm/os_info.h> |
a9ae32c3 | 54 | #include <asm/sigp.h> |
b5f87f15 | 55 | #include <asm/idle.h> |
916cda1a | 56 | #include <asm/nmi.h> |
38389ec8 | 57 | #include <asm/topology.h> |
a806170e | 58 | #include "entry.h" |
1da177e4 | 59 | |
8b646bd7 MS |
60 | enum { |
61 | ec_schedule = 0, | |
8b646bd7 MS |
62 | ec_call_function_single, |
63 | ec_stop_cpu, | |
64 | }; | |
08d07968 | 65 | |
8b646bd7 | 66 | enum { |
08d07968 HC |
67 | CPU_STATE_STANDBY, |
68 | CPU_STATE_CONFIGURED, | |
69 | }; | |
70 | ||
2f859d0d HC |
71 | static DEFINE_PER_CPU(struct cpu *, cpu_device); |
72 | ||
8b646bd7 | 73 | struct pcpu { |
c667aeac | 74 | struct lowcore *lowcore; /* lowcore page(s) for the cpu */ |
8b646bd7 | 75 | unsigned long ec_mask; /* bit mask for ec_xxx functions */ |
3dbc78d3 | 76 | unsigned long ec_clk; /* sigp timestamp for ec_xxx */ |
2f859d0d HC |
77 | signed char state; /* physical cpu state */ |
78 | signed char polarization; /* physical polarization */ | |
8b646bd7 MS |
79 | u16 address; /* physical cpu address */ |
80 | }; | |
81 | ||
d08d9430 | 82 | static u8 boot_core_type; |
8b646bd7 MS |
83 | static struct pcpu pcpu_devices[NR_CPUS]; |
84 | ||
10ad34bc MS |
85 | unsigned int smp_cpu_mt_shift; |
86 | EXPORT_SYMBOL(smp_cpu_mt_shift); | |
87 | ||
88 | unsigned int smp_cpu_mtid; | |
89 | EXPORT_SYMBOL(smp_cpu_mtid); | |
90 | ||
1a36a39e MS |
91 | #ifdef CONFIG_CRASH_DUMP |
92 | __vector128 __initdata boot_cpu_vector_save_area[__NUM_VXRS]; | |
93 | #endif | |
94 | ||
10ad34bc MS |
95 | static unsigned int smp_max_threads __initdata = -1U; |
96 | ||
97 | static int __init early_nosmt(char *s) | |
98 | { | |
99 | smp_max_threads = 1; | |
100 | return 0; | |
101 | } | |
102 | early_param("nosmt", early_nosmt); | |
103 | ||
104 | static int __init early_smt(char *s) | |
105 | { | |
106 | get_option(&s, &smp_max_threads); | |
107 | return 0; | |
108 | } | |
109 | early_param("smt", early_smt); | |
110 | ||
50ab9a9a HC |
111 | /* |
112 | * The smp_cpu_state_mutex must be held when changing the state or polarization | |
113 | * member of a pcpu data structure within the pcpu_devices arreay. | |
114 | */ | |
dbd70fb4 | 115 | DEFINE_MUTEX(smp_cpu_state_mutex); |
08d07968 | 116 | |
8b646bd7 MS |
117 | /* |
118 | * Signal processor helper functions. | |
119 | */ | |
1a36a39e | 120 | static inline int __pcpu_sigp_relax(u16 addr, u8 order, unsigned long parm) |
5c0b912e | 121 | { |
8b646bd7 | 122 | int cc; |
5c0b912e | 123 | |
8b646bd7 | 124 | while (1) { |
c5e3acd6 | 125 | cc = __pcpu_sigp(addr, order, parm, NULL); |
a9ae32c3 | 126 | if (cc != SIGP_CC_BUSY) |
8b646bd7 MS |
127 | return cc; |
128 | cpu_relax(); | |
5c0b912e | 129 | } |
5c0b912e HC |
130 | } |
131 | ||
8b646bd7 | 132 | static int pcpu_sigp_retry(struct pcpu *pcpu, u8 order, u32 parm) |
a93b8ec1 | 133 | { |
8b646bd7 MS |
134 | int cc, retry; |
135 | ||
136 | for (retry = 0; ; retry++) { | |
c5e3acd6 | 137 | cc = __pcpu_sigp(pcpu->address, order, parm, NULL); |
a9ae32c3 | 138 | if (cc != SIGP_CC_BUSY) |
8b646bd7 MS |
139 | break; |
140 | if (retry >= 3) | |
141 | udelay(10); | |
142 | } | |
143 | return cc; | |
144 | } | |
145 | ||
146 | static inline int pcpu_stopped(struct pcpu *pcpu) | |
147 | { | |
41459d36 | 148 | u32 uninitialized_var(status); |
c5e3acd6 | 149 | |
a9ae32c3 | 150 | if (__pcpu_sigp(pcpu->address, SIGP_SENSE, |
c5e3acd6 | 151 | 0, &status) != SIGP_CC_STATUS_STORED) |
8b646bd7 | 152 | return 0; |
c5e3acd6 | 153 | return !!(status & (SIGP_STATUS_CHECK_STOP|SIGP_STATUS_STOPPED)); |
8b646bd7 MS |
154 | } |
155 | ||
156 | static inline int pcpu_running(struct pcpu *pcpu) | |
a93b8ec1 | 157 | { |
a9ae32c3 | 158 | if (__pcpu_sigp(pcpu->address, SIGP_SENSE_RUNNING, |
c5e3acd6 | 159 | 0, NULL) != SIGP_CC_STATUS_STORED) |
8b646bd7 | 160 | return 1; |
524b24ad HC |
161 | /* Status stored condition code is equivalent to cpu not running. */ |
162 | return 0; | |
a93b8ec1 HC |
163 | } |
164 | ||
1943f53c | 165 | /* |
8b646bd7 | 166 | * Find struct pcpu by cpu address. |
1943f53c | 167 | */ |
10ad34bc | 168 | static struct pcpu *pcpu_find_address(const struct cpumask *mask, u16 address) |
1943f53c MH |
169 | { |
170 | int cpu; | |
171 | ||
8b646bd7 MS |
172 | for_each_cpu(cpu, mask) |
173 | if (pcpu_devices[cpu].address == address) | |
174 | return pcpu_devices + cpu; | |
175 | return NULL; | |
176 | } | |
177 | ||
178 | static void pcpu_ec_call(struct pcpu *pcpu, int ec_bit) | |
179 | { | |
180 | int order; | |
181 | ||
dea24190 HC |
182 | if (test_and_set_bit(ec_bit, &pcpu->ec_mask)) |
183 | return; | |
184 | order = pcpu_running(pcpu) ? SIGP_EXTERNAL_CALL : SIGP_EMERGENCY_SIGNAL; | |
3dbc78d3 | 185 | pcpu->ec_clk = get_tod_clock_fast(); |
8b646bd7 MS |
186 | pcpu_sigp_retry(pcpu, order, 0); |
187 | } | |
188 | ||
2f859d0d HC |
189 | #define ASYNC_FRAME_OFFSET (ASYNC_SIZE - STACK_FRAME_OVERHEAD - __PT_SIZE) |
190 | #define PANIC_FRAME_OFFSET (PAGE_SIZE - STACK_FRAME_OVERHEAD - __PT_SIZE) | |
191 | ||
e2741f17 | 192 | static int pcpu_alloc_lowcore(struct pcpu *pcpu, int cpu) |
8b646bd7 | 193 | { |
2f859d0d | 194 | unsigned long async_stack, panic_stack; |
c667aeac | 195 | struct lowcore *lc; |
8b646bd7 MS |
196 | |
197 | if (pcpu != &pcpu_devices[0]) { | |
c667aeac | 198 | pcpu->lowcore = (struct lowcore *) |
8b646bd7 | 199 | __get_free_pages(GFP_KERNEL | GFP_DMA, LC_ORDER); |
2f859d0d HC |
200 | async_stack = __get_free_pages(GFP_KERNEL, ASYNC_ORDER); |
201 | panic_stack = __get_free_page(GFP_KERNEL); | |
202 | if (!pcpu->lowcore || !panic_stack || !async_stack) | |
8b646bd7 | 203 | goto out; |
2f859d0d HC |
204 | } else { |
205 | async_stack = pcpu->lowcore->async_stack - ASYNC_FRAME_OFFSET; | |
206 | panic_stack = pcpu->lowcore->panic_stack - PANIC_FRAME_OFFSET; | |
1943f53c | 207 | } |
8b646bd7 MS |
208 | lc = pcpu->lowcore; |
209 | memcpy(lc, &S390_lowcore, 512); | |
210 | memset((char *) lc + 512, 0, sizeof(*lc) - 512); | |
2f859d0d HC |
211 | lc->async_stack = async_stack + ASYNC_FRAME_OFFSET; |
212 | lc->panic_stack = panic_stack + PANIC_FRAME_OFFSET; | |
8b646bd7 | 213 | lc->cpu_nr = cpu; |
6c8cd5bb | 214 | lc->spinlock_lockval = arch_spin_lockval(cpu); |
b96f7d88 | 215 | lc->spinlock_index = 0; |
f19fbd5e | 216 | lc->br_r1_trampoline = 0x07f1; /* br %r1 */ |
6c81511c | 217 | if (nmi_alloc_per_cpu(lc)) |
8b646bd7 | 218 | goto out; |
6c81511c MS |
219 | if (vdso_alloc_per_cpu(lc)) |
220 | goto out_mcesa; | |
8b646bd7 | 221 | lowcore_ptr[cpu] = lc; |
a9ae32c3 | 222 | pcpu_sigp_retry(pcpu, SIGP_SET_PREFIX, (u32)(unsigned long) lc); |
8b646bd7 | 223 | return 0; |
6c81511c MS |
224 | |
225 | out_mcesa: | |
226 | nmi_free_per_cpu(lc); | |
8b646bd7 MS |
227 | out: |
228 | if (pcpu != &pcpu_devices[0]) { | |
2f859d0d HC |
229 | free_page(panic_stack); |
230 | free_pages(async_stack, ASYNC_ORDER); | |
8b646bd7 MS |
231 | free_pages((unsigned long) pcpu->lowcore, LC_ORDER); |
232 | } | |
233 | return -ENOMEM; | |
1943f53c MH |
234 | } |
235 | ||
9d0f46af HC |
236 | #ifdef CONFIG_HOTPLUG_CPU |
237 | ||
8b646bd7 | 238 | static void pcpu_free_lowcore(struct pcpu *pcpu) |
2c2df118 | 239 | { |
a9ae32c3 | 240 | pcpu_sigp_retry(pcpu, SIGP_SET_PREFIX, 0); |
8b646bd7 | 241 | lowcore_ptr[pcpu - pcpu_devices] = NULL; |
8b646bd7 | 242 | vdso_free_per_cpu(pcpu->lowcore); |
6c81511c | 243 | nmi_free_per_cpu(pcpu->lowcore); |
2f859d0d HC |
244 | if (pcpu == &pcpu_devices[0]) |
245 | return; | |
246 | free_page(pcpu->lowcore->panic_stack-PANIC_FRAME_OFFSET); | |
247 | free_pages(pcpu->lowcore->async_stack-ASYNC_FRAME_OFFSET, ASYNC_ORDER); | |
248 | free_pages((unsigned long) pcpu->lowcore, LC_ORDER); | |
8b646bd7 MS |
249 | } |
250 | ||
9d0f46af HC |
251 | #endif /* CONFIG_HOTPLUG_CPU */ |
252 | ||
8b646bd7 MS |
253 | static void pcpu_prepare_secondary(struct pcpu *pcpu, int cpu) |
254 | { | |
c667aeac | 255 | struct lowcore *lc = pcpu->lowcore; |
8b646bd7 | 256 | |
64f31d58 | 257 | cpumask_set_cpu(cpu, &init_mm.context.cpu_attach_mask); |
1b948d6c | 258 | cpumask_set_cpu(cpu, mm_cpumask(&init_mm)); |
8b646bd7 | 259 | lc->cpu_nr = cpu; |
6c8cd5bb | 260 | lc->spinlock_lockval = arch_spin_lockval(cpu); |
b96f7d88 | 261 | lc->spinlock_index = 0; |
8b646bd7 MS |
262 | lc->percpu_offset = __per_cpu_offset[cpu]; |
263 | lc->kernel_asce = S390_lowcore.kernel_asce; | |
264 | lc->machine_flags = S390_lowcore.machine_flags; | |
8b646bd7 MS |
265 | lc->user_timer = lc->system_timer = lc->steal_timer = 0; |
266 | __ctl_store(lc->cregs_save_area, 0, 15); | |
267 | save_access_regs((unsigned int *) lc->access_regs_save_area); | |
268 | memcpy(lc->stfle_fac_list, S390_lowcore.stfle_fac_list, | |
cf148998 MS |
269 | sizeof(lc->stfle_fac_list)); |
270 | memcpy(lc->alt_stfle_fac_list, S390_lowcore.alt_stfle_fac_list, | |
271 | sizeof(lc->alt_stfle_fac_list)); | |
b96f7d88 | 272 | arch_spin_lock_setup(cpu); |
8b646bd7 MS |
273 | } |
274 | ||
275 | static void pcpu_attach_task(struct pcpu *pcpu, struct task_struct *tsk) | |
276 | { | |
c667aeac | 277 | struct lowcore *lc = pcpu->lowcore; |
8b646bd7 | 278 | |
dc7ee00d MS |
279 | lc->kernel_stack = (unsigned long) task_stack_page(tsk) |
280 | + THREAD_SIZE - STACK_FRAME_OVERHEAD - sizeof(struct pt_regs); | |
8b646bd7 | 281 | lc->current_task = (unsigned long) tsk; |
e22cf8ca CB |
282 | lc->lpp = LPP_MAGIC; |
283 | lc->current_pid = tsk->pid; | |
90c53e65 | 284 | lc->user_timer = tsk->thread.user_timer; |
b7662eef | 285 | lc->guest_timer = tsk->thread.guest_timer; |
90c53e65 | 286 | lc->system_timer = tsk->thread.system_timer; |
b7662eef CB |
287 | lc->hardirq_timer = tsk->thread.hardirq_timer; |
288 | lc->softirq_timer = tsk->thread.softirq_timer; | |
8b646bd7 MS |
289 | lc->steal_timer = 0; |
290 | } | |
291 | ||
292 | static void pcpu_start_fn(struct pcpu *pcpu, void (*func)(void *), void *data) | |
293 | { | |
c667aeac | 294 | struct lowcore *lc = pcpu->lowcore; |
8b646bd7 MS |
295 | |
296 | lc->restart_stack = lc->kernel_stack; | |
297 | lc->restart_fn = (unsigned long) func; | |
298 | lc->restart_data = (unsigned long) data; | |
299 | lc->restart_source = -1UL; | |
a9ae32c3 | 300 | pcpu_sigp_retry(pcpu, SIGP_RESTART, 0); |
8b646bd7 MS |
301 | } |
302 | ||
303 | /* | |
304 | * Call function via PSW restart on pcpu and stop the current cpu. | |
305 | */ | |
306 | static void pcpu_delegate(struct pcpu *pcpu, void (*func)(void *), | |
307 | void *data, unsigned long stack) | |
308 | { | |
c667aeac | 309 | struct lowcore *lc = lowcore_ptr[pcpu - pcpu_devices]; |
fbe76568 | 310 | unsigned long source_cpu = stap(); |
8b646bd7 | 311 | |
e258d719 | 312 | __load_psw_mask(PSW_KERNEL_BITS); |
fbe76568 | 313 | if (pcpu->address == source_cpu) |
8b646bd7 MS |
314 | func(data); /* should not return */ |
315 | /* Stop target cpu (if func returns this stops the current cpu). */ | |
a9ae32c3 | 316 | pcpu_sigp_retry(pcpu, SIGP_STOP, 0); |
8b646bd7 | 317 | /* Restart func on the target cpu and stop the current cpu. */ |
fbe76568 HC |
318 | mem_assign_absolute(lc->restart_stack, stack); |
319 | mem_assign_absolute(lc->restart_fn, (unsigned long) func); | |
320 | mem_assign_absolute(lc->restart_data, (unsigned long) data); | |
321 | mem_assign_absolute(lc->restart_source, source_cpu); | |
d768bd89 | 322 | __bpon(); |
8b646bd7 | 323 | asm volatile( |
eb546195 | 324 | "0: sigp 0,%0,%2 # sigp restart to target cpu\n" |
8b646bd7 | 325 | " brc 2,0b # busy, try again\n" |
eb546195 | 326 | "1: sigp 0,%1,%3 # sigp stop to current cpu\n" |
8b646bd7 | 327 | " brc 2,1b # busy, try again\n" |
fbe76568 | 328 | : : "d" (pcpu->address), "d" (source_cpu), |
eb546195 HC |
329 | "K" (SIGP_RESTART), "K" (SIGP_STOP) |
330 | : "0", "1", "cc"); | |
8b646bd7 MS |
331 | for (;;) ; |
332 | } | |
333 | ||
10ad34bc MS |
334 | /* |
335 | * Enable additional logical cpus for multi-threading. | |
336 | */ | |
337 | static int pcpu_set_smt(unsigned int mtid) | |
338 | { | |
10ad34bc MS |
339 | int cc; |
340 | ||
341 | if (smp_cpu_mtid == mtid) | |
342 | return 0; | |
80a60f6e | 343 | cc = __pcpu_sigp(0, SIGP_SET_MULTI_THREADING, mtid, NULL); |
10ad34bc MS |
344 | if (cc == 0) { |
345 | smp_cpu_mtid = mtid; | |
346 | smp_cpu_mt_shift = 0; | |
347 | while (smp_cpu_mtid >= (1U << smp_cpu_mt_shift)) | |
348 | smp_cpu_mt_shift++; | |
349 | pcpu_devices[0].address = stap(); | |
350 | } | |
351 | return cc; | |
352 | } | |
353 | ||
8b646bd7 MS |
354 | /* |
355 | * Call function on an online CPU. | |
356 | */ | |
357 | void smp_call_online_cpu(void (*func)(void *), void *data) | |
358 | { | |
359 | struct pcpu *pcpu; | |
360 | ||
361 | /* Use the current cpu if it is online. */ | |
362 | pcpu = pcpu_find_address(cpu_online_mask, stap()); | |
363 | if (!pcpu) | |
364 | /* Use the first online cpu. */ | |
365 | pcpu = pcpu_devices + cpumask_first(cpu_online_mask); | |
366 | pcpu_delegate(pcpu, func, data, (unsigned long) restart_stack); | |
367 | } | |
368 | ||
369 | /* | |
370 | * Call function on the ipl CPU. | |
371 | */ | |
372 | void smp_call_ipl_cpu(void (*func)(void *), void *data) | |
373 | { | |
c6da39f2 | 374 | pcpu_delegate(&pcpu_devices[0], func, data, |
2f859d0d HC |
375 | pcpu_devices->lowcore->panic_stack - |
376 | PANIC_FRAME_OFFSET + PAGE_SIZE); | |
8b646bd7 MS |
377 | } |
378 | ||
379 | int smp_find_processor_id(u16 address) | |
380 | { | |
381 | int cpu; | |
382 | ||
383 | for_each_present_cpu(cpu) | |
384 | if (pcpu_devices[cpu].address == address) | |
385 | return cpu; | |
386 | return -1; | |
2c2df118 HC |
387 | } |
388 | ||
760928c0 | 389 | bool arch_vcpu_is_preempted(int cpu) |
85ac7ca5 | 390 | { |
760928c0 CB |
391 | if (test_cpu_flag_of(CIF_ENABLED_WAIT, cpu)) |
392 | return false; | |
393 | if (pcpu_running(pcpu_devices + cpu)) | |
394 | return false; | |
395 | return true; | |
8b646bd7 | 396 | } |
760928c0 | 397 | EXPORT_SYMBOL(arch_vcpu_is_preempted); |
8b646bd7 | 398 | |
8b646bd7 | 399 | void smp_yield_cpu(int cpu) |
85ac7ca5 | 400 | { |
1ec2772e | 401 | if (MACHINE_HAS_DIAG9C) { |
b5a6b71b | 402 | diag_stat_inc_norecursion(DIAG_STAT_X09C); |
8b646bd7 MS |
403 | asm volatile("diag %0,0,0x9c" |
404 | : : "d" (pcpu_devices[cpu].address)); | |
1ec2772e | 405 | } else if (MACHINE_HAS_DIAG44) { |
b5a6b71b | 406 | diag_stat_inc_norecursion(DIAG_STAT_X044); |
8b646bd7 | 407 | asm volatile("diag 0,0,0x44"); |
1ec2772e | 408 | } |
8b646bd7 MS |
409 | } |
410 | ||
411 | /* | |
412 | * Send cpus emergency shutdown signal. This gives the cpus the | |
413 | * opportunity to complete outstanding interrupts. | |
414 | */ | |
00a8f886 | 415 | void notrace smp_emergency_stop(void) |
8b646bd7 | 416 | { |
00a8f886 | 417 | cpumask_t cpumask; |
8b646bd7 MS |
418 | u64 end; |
419 | int cpu; | |
420 | ||
00a8f886 MS |
421 | cpumask_copy(&cpumask, cpu_online_mask); |
422 | cpumask_clear_cpu(smp_processor_id(), &cpumask); | |
423 | ||
1aae0560 | 424 | end = get_tod_clock() + (1000000UL << 12); |
00a8f886 | 425 | for_each_cpu(cpu, &cpumask) { |
8b646bd7 MS |
426 | struct pcpu *pcpu = pcpu_devices + cpu; |
427 | set_bit(ec_stop_cpu, &pcpu->ec_mask); | |
a9ae32c3 HC |
428 | while (__pcpu_sigp(pcpu->address, SIGP_EMERGENCY_SIGNAL, |
429 | 0, NULL) == SIGP_CC_BUSY && | |
1aae0560 | 430 | get_tod_clock() < end) |
8b646bd7 MS |
431 | cpu_relax(); |
432 | } | |
1aae0560 | 433 | while (get_tod_clock() < end) { |
00a8f886 | 434 | for_each_cpu(cpu, &cpumask) |
8b646bd7 | 435 | if (pcpu_stopped(pcpu_devices + cpu)) |
00a8f886 MS |
436 | cpumask_clear_cpu(cpu, &cpumask); |
437 | if (cpumask_empty(&cpumask)) | |
8b646bd7 | 438 | break; |
85ac7ca5 | 439 | cpu_relax(); |
8b646bd7 | 440 | } |
85ac7ca5 | 441 | } |
00a8f886 | 442 | NOKPROBE_SYMBOL(smp_emergency_stop); |
85ac7ca5 | 443 | |
8b646bd7 MS |
444 | /* |
445 | * Stop all cpus but the current one. | |
446 | */ | |
677d7623 | 447 | void smp_send_stop(void) |
1da177e4 | 448 | { |
85ac7ca5 | 449 | int cpu; |
1da177e4 | 450 | |
677d7623 | 451 | /* Disable all interrupts/machine checks */ |
e258d719 | 452 | __load_psw_mask(PSW_KERNEL_BITS | PSW_MASK_DAT); |
3324e60a | 453 | trace_hardirqs_off(); |
1da177e4 | 454 | |
3ab121ab | 455 | debug_set_critical(); |
85ac7ca5 | 456 | |
8b646bd7 | 457 | if (oops_in_progress) |
00a8f886 | 458 | smp_emergency_stop(); |
1da177e4 | 459 | |
85ac7ca5 | 460 | /* stop all processors */ |
00a8f886 MS |
461 | for_each_online_cpu(cpu) { |
462 | if (cpu == smp_processor_id()) | |
463 | continue; | |
464 | pcpu_sigp_retry(pcpu_devices + cpu, SIGP_STOP, 0); | |
465 | while (!pcpu_stopped(pcpu_devices + cpu)) | |
c6b5b847 HC |
466 | cpu_relax(); |
467 | } | |
468 | } | |
469 | ||
1da177e4 LT |
470 | /* |
471 | * This is the main routine where commands issued by other | |
472 | * cpus are handled. | |
473 | */ | |
9acf73b7 | 474 | static void smp_handle_ext_call(void) |
1da177e4 | 475 | { |
39ce010d | 476 | unsigned long bits; |
1da177e4 | 477 | |
9acf73b7 HC |
478 | /* handle bit signal external calls */ |
479 | bits = xchg(&pcpu_devices[smp_processor_id()].ec_mask, 0); | |
85ac7ca5 MS |
480 | if (test_bit(ec_stop_cpu, &bits)) |
481 | smp_stop_cpu(); | |
184748cc PZ |
482 | if (test_bit(ec_schedule, &bits)) |
483 | scheduler_ipi(); | |
ca9fc75a HC |
484 | if (test_bit(ec_call_function_single, &bits)) |
485 | generic_smp_call_function_single_interrupt(); | |
9acf73b7 | 486 | } |
85ac7ca5 | 487 | |
9acf73b7 HC |
488 | static void do_ext_call_interrupt(struct ext_code ext_code, |
489 | unsigned int param32, unsigned long param64) | |
490 | { | |
491 | inc_irq_stat(ext_code.code == 0x1202 ? IRQEXT_EXC : IRQEXT_EMS); | |
492 | smp_handle_ext_call(); | |
1da177e4 LT |
493 | } |
494 | ||
630cd046 | 495 | void arch_send_call_function_ipi_mask(const struct cpumask *mask) |
ca9fc75a HC |
496 | { |
497 | int cpu; | |
498 | ||
630cd046 | 499 | for_each_cpu(cpu, mask) |
b6ed49e0 | 500 | pcpu_ec_call(pcpu_devices + cpu, ec_call_function_single); |
ca9fc75a HC |
501 | } |
502 | ||
503 | void arch_send_call_function_single_ipi(int cpu) | |
504 | { | |
8b646bd7 | 505 | pcpu_ec_call(pcpu_devices + cpu, ec_call_function_single); |
ca9fc75a HC |
506 | } |
507 | ||
1da177e4 LT |
508 | /* |
509 | * this function sends a 'reschedule' IPI to another CPU. | |
510 | * it goes straight through and wastes no time serializing | |
511 | * anything. Worst case is that we lose a reschedule ... | |
512 | */ | |
513 | void smp_send_reschedule(int cpu) | |
514 | { | |
8b646bd7 | 515 | pcpu_ec_call(pcpu_devices + cpu, ec_schedule); |
1da177e4 LT |
516 | } |
517 | ||
518 | /* | |
519 | * parameter area for the set/clear control bit callbacks | |
520 | */ | |
94c12cc7 | 521 | struct ec_creg_mask_parms { |
8b646bd7 MS |
522 | unsigned long orval; |
523 | unsigned long andval; | |
524 | int cr; | |
94c12cc7 | 525 | }; |
1da177e4 LT |
526 | |
527 | /* | |
528 | * callback for setting/clearing control bits | |
529 | */ | |
39ce010d HC |
530 | static void smp_ctl_bit_callback(void *info) |
531 | { | |
94c12cc7 | 532 | struct ec_creg_mask_parms *pp = info; |
1da177e4 | 533 | unsigned long cregs[16]; |
39ce010d | 534 | |
94c12cc7 | 535 | __ctl_store(cregs, 0, 15); |
8b646bd7 | 536 | cregs[pp->cr] = (cregs[pp->cr] & pp->andval) | pp->orval; |
94c12cc7 | 537 | __ctl_load(cregs, 0, 15); |
1da177e4 LT |
538 | } |
539 | ||
540 | /* | |
541 | * Set a bit in a control register of all cpus | |
542 | */ | |
94c12cc7 MS |
543 | void smp_ctl_set_bit(int cr, int bit) |
544 | { | |
8b646bd7 | 545 | struct ec_creg_mask_parms parms = { 1UL << bit, -1UL, cr }; |
1da177e4 | 546 | |
15c8b6c1 | 547 | on_each_cpu(smp_ctl_bit_callback, &parms, 1); |
1da177e4 | 548 | } |
39ce010d | 549 | EXPORT_SYMBOL(smp_ctl_set_bit); |
1da177e4 LT |
550 | |
551 | /* | |
552 | * Clear a bit in a control register of all cpus | |
553 | */ | |
94c12cc7 MS |
554 | void smp_ctl_clear_bit(int cr, int bit) |
555 | { | |
8b646bd7 | 556 | struct ec_creg_mask_parms parms = { 0, ~(1UL << bit), cr }; |
1da177e4 | 557 | |
15c8b6c1 | 558 | on_each_cpu(smp_ctl_bit_callback, &parms, 1); |
1da177e4 | 559 | } |
39ce010d | 560 | EXPORT_SYMBOL(smp_ctl_clear_bit); |
1da177e4 | 561 | |
bf28a597 | 562 | #ifdef CONFIG_CRASH_DUMP |
411ed322 | 563 | |
1af135a1 HC |
564 | int smp_store_status(int cpu) |
565 | { | |
1a36a39e MS |
566 | struct pcpu *pcpu = pcpu_devices + cpu; |
567 | unsigned long pa; | |
1af135a1 | 568 | |
1a36a39e MS |
569 | pa = __pa(&pcpu->lowcore->floating_pt_save_area); |
570 | if (__pcpu_sigp_relax(pcpu->address, SIGP_STORE_STATUS_AT_ADDRESS, | |
571 | pa) != SIGP_CC_ORDER_CODE_ACCEPTED) | |
1af135a1 | 572 | return -EIO; |
916cda1a | 573 | if (!MACHINE_HAS_VX && !MACHINE_HAS_GS) |
1af135a1 | 574 | return 0; |
916cda1a MS |
575 | pa = __pa(pcpu->lowcore->mcesad & MCESA_ORIGIN_MASK); |
576 | if (MACHINE_HAS_GS) | |
577 | pa |= pcpu->lowcore->mcesad & MCESA_LC_MASK; | |
1a36a39e MS |
578 | if (__pcpu_sigp_relax(pcpu->address, SIGP_STORE_ADDITIONAL_STATUS, |
579 | pa) != SIGP_CC_ORDER_CODE_ACCEPTED) | |
580 | return -EIO; | |
1af135a1 HC |
581 | return 0; |
582 | } | |
583 | ||
10ad34bc MS |
584 | /* |
585 | * Collect CPU state of the previous, crashed system. | |
586 | * There are four cases: | |
587 | * 1) standard zfcp dump | |
588 | * condition: OLDMEM_BASE == NULL && ipl_info.type == IPL_TYPE_FCP_DUMP | |
589 | * The state for all CPUs except the boot CPU needs to be collected | |
590 | * with sigp stop-and-store-status. The boot CPU state is located in | |
591 | * the absolute lowcore of the memory stored in the HSA. The zcore code | |
1a36a39e | 592 | * will copy the boot CPU state from the HSA. |
10ad34bc MS |
593 | * 2) stand-alone kdump for SCSI (zfcp dump with swapped memory) |
594 | * condition: OLDMEM_BASE != NULL && ipl_info.type == IPL_TYPE_FCP_DUMP | |
595 | * The state for all CPUs except the boot CPU needs to be collected | |
596 | * with sigp stop-and-store-status. The firmware or the boot-loader | |
597 | * stored the registers of the boot CPU in the absolute lowcore in the | |
598 | * memory of the old system. | |
599 | * 3) kdump and the old kernel did not store the CPU state, | |
600 | * or stand-alone kdump for DASD | |
601 | * condition: OLDMEM_BASE != NULL && !is_kdump_kernel() | |
602 | * The state for all CPUs except the boot CPU needs to be collected | |
603 | * with sigp stop-and-store-status. The kexec code or the boot-loader | |
604 | * stored the registers of the boot CPU in the memory of the old system. | |
605 | * 4) kdump and the old kernel stored the CPU state | |
606 | * condition: OLDMEM_BASE != NULL && is_kdump_kernel() | |
8a07dd02 MS |
607 | * This case does not exist for s390 anymore, setup_arch explicitly |
608 | * deactivates the elfcorehdr= kernel parameter | |
10ad34bc | 609 | */ |
1a2c5840 | 610 | static __init void smp_save_cpu_vxrs(struct save_area *sa, u16 addr, |
1a36a39e MS |
611 | bool is_boot_cpu, unsigned long page) |
612 | { | |
613 | __vector128 *vxrs = (__vector128 *) page; | |
614 | ||
615 | if (is_boot_cpu) | |
616 | vxrs = boot_cpu_vector_save_area; | |
617 | else | |
618 | __pcpu_sigp_relax(addr, SIGP_STORE_ADDITIONAL_STATUS, page); | |
1a2c5840 | 619 | save_area_add_vxrs(sa, vxrs); |
1a36a39e MS |
620 | } |
621 | ||
1a2c5840 | 622 | static __init void smp_save_cpu_regs(struct save_area *sa, u16 addr, |
1a36a39e MS |
623 | bool is_boot_cpu, unsigned long page) |
624 | { | |
625 | void *regs = (void *) page; | |
626 | ||
627 | if (is_boot_cpu) | |
628 | copy_oldmem_kernel(regs, (void *) __LC_FPREGS_SAVE_AREA, 512); | |
629 | else | |
630 | __pcpu_sigp_relax(addr, SIGP_STORE_STATUS_AT_ADDRESS, page); | |
1a2c5840 | 631 | save_area_add_regs(sa, regs); |
1a36a39e MS |
632 | } |
633 | ||
1592a8e4 | 634 | void __init smp_save_dump_cpus(void) |
10ad34bc | 635 | { |
1a2c5840 MS |
636 | int addr, boot_cpu_addr, max_cpu_addr; |
637 | struct save_area *sa; | |
1a36a39e | 638 | unsigned long page; |
1592a8e4 | 639 | bool is_boot_cpu; |
10ad34bc | 640 | |
10ad34bc MS |
641 | if (!(OLDMEM_BASE || ipl_info.type == IPL_TYPE_FCP_DUMP)) |
642 | /* No previous system present, normal boot. */ | |
643 | return; | |
1a36a39e MS |
644 | /* Allocate a page as dumping area for the store status sigps */ |
645 | page = memblock_alloc_base(PAGE_SIZE, PAGE_SIZE, 1UL << 31); | |
10ad34bc | 646 | /* Set multi-threading state to the previous system. */ |
37c5f6c8 | 647 | pcpu_set_smt(sclp.mtid_prev); |
1592a8e4 | 648 | boot_cpu_addr = stap(); |
1a2c5840 MS |
649 | max_cpu_addr = SCLP_MAX_CORES << sclp.mtid_prev; |
650 | for (addr = 0; addr <= max_cpu_addr; addr++) { | |
1a36a39e | 651 | if (__pcpu_sigp_relax(addr, SIGP_SENSE, 0) == |
1592a8e4 MH |
652 | SIGP_CC_NOT_OPERATIONAL) |
653 | continue; | |
1592a8e4 | 654 | is_boot_cpu = (addr == boot_cpu_addr); |
1a2c5840 MS |
655 | /* Allocate save area */ |
656 | sa = save_area_alloc(is_boot_cpu); | |
657 | if (!sa) | |
658 | panic("could not allocate memory for save area\n"); | |
1a36a39e MS |
659 | if (MACHINE_HAS_VX) |
660 | /* Get the vector registers */ | |
1a2c5840 | 661 | smp_save_cpu_vxrs(sa, addr, is_boot_cpu, page); |
1a36a39e MS |
662 | /* |
663 | * For a zfcp dump OLDMEM_BASE == NULL and the registers | |
664 | * of the boot CPU are stored in the HSA. To retrieve | |
665 | * these registers an SCLP request is required which is | |
666 | * done by drivers/s390/char/zcore.c:init_cpu_info() | |
667 | */ | |
668 | if (!is_boot_cpu || OLDMEM_BASE) | |
669 | /* Get the CPU registers */ | |
1a2c5840 | 670 | smp_save_cpu_regs(sa, addr, is_boot_cpu, page); |
10ad34bc | 671 | } |
1a36a39e | 672 | memblock_free(page, PAGE_SIZE); |
1592a8e4 MH |
673 | diag308_reset(); |
674 | pcpu_set_smt(0); | |
1af135a1 | 675 | } |
1a36a39e | 676 | #endif /* CONFIG_CRASH_DUMP */ |
08d07968 | 677 | |
50ab9a9a HC |
678 | void smp_cpu_set_polarization(int cpu, int val) |
679 | { | |
680 | pcpu_devices[cpu].polarization = val; | |
681 | } | |
682 | ||
683 | int smp_cpu_get_polarization(int cpu) | |
684 | { | |
685 | return pcpu_devices[cpu].polarization; | |
686 | } | |
687 | ||
af51160e | 688 | static void __ref smp_get_core_info(struct sclp_core_info *info, int early) |
08d07968 | 689 | { |
8b646bd7 | 690 | static int use_sigp_detection; |
8b646bd7 MS |
691 | int address; |
692 | ||
af51160e | 693 | if (use_sigp_detection || sclp_get_core_info(info, early)) { |
8b646bd7 | 694 | use_sigp_detection = 1; |
e7086eb1 | 695 | for (address = 0; |
d08d9430 | 696 | address < (SCLP_MAX_CORES << smp_cpu_mt_shift); |
10ad34bc | 697 | address += (1U << smp_cpu_mt_shift)) { |
1a36a39e | 698 | if (__pcpu_sigp_relax(address, SIGP_SENSE, 0) == |
a9ae32c3 | 699 | SIGP_CC_NOT_OPERATIONAL) |
8b646bd7 | 700 | continue; |
d08d9430 | 701 | info->core[info->configured].core_id = |
10ad34bc | 702 | address >> smp_cpu_mt_shift; |
8b646bd7 MS |
703 | info->configured++; |
704 | } | |
705 | info->combined = info->configured; | |
08d07968 | 706 | } |
08d07968 HC |
707 | } |
708 | ||
e2741f17 | 709 | static int smp_add_present_cpu(int cpu); |
8b646bd7 | 710 | |
d08d9430 | 711 | static int __smp_rescan_cpus(struct sclp_core_info *info, int sysfs_add) |
08d07968 | 712 | { |
8b646bd7 | 713 | struct pcpu *pcpu; |
08d07968 | 714 | cpumask_t avail; |
10ad34bc MS |
715 | int cpu, nr, i, j; |
716 | u16 address; | |
08d07968 | 717 | |
8b646bd7 | 718 | nr = 0; |
0f1959f5 | 719 | cpumask_xor(&avail, cpu_possible_mask, cpu_present_mask); |
8b646bd7 MS |
720 | cpu = cpumask_first(&avail); |
721 | for (i = 0; (i < info->combined) && (cpu < nr_cpu_ids); i++) { | |
d08d9430 | 722 | if (sclp.has_core_type && info->core[i].type != boot_core_type) |
8b646bd7 | 723 | continue; |
d08d9430 | 724 | address = info->core[i].core_id << smp_cpu_mt_shift; |
10ad34bc MS |
725 | for (j = 0; j <= smp_cpu_mtid; j++) { |
726 | if (pcpu_find_address(cpu_present_mask, address + j)) | |
727 | continue; | |
728 | pcpu = pcpu_devices + cpu; | |
729 | pcpu->address = address + j; | |
730 | pcpu->state = | |
731 | (cpu >= info->configured*(smp_cpu_mtid + 1)) ? | |
732 | CPU_STATE_STANDBY : CPU_STATE_CONFIGURED; | |
733 | smp_cpu_set_polarization(cpu, POLARIZATION_UNKNOWN); | |
734 | set_cpu_present(cpu, true); | |
735 | if (sysfs_add && smp_add_present_cpu(cpu) != 0) | |
736 | set_cpu_present(cpu, false); | |
737 | else | |
738 | nr++; | |
739 | cpu = cpumask_next(cpu, &avail); | |
740 | if (cpu >= nr_cpu_ids) | |
741 | break; | |
742 | } | |
8b646bd7 MS |
743 | } |
744 | return nr; | |
1da177e4 LT |
745 | } |
746 | ||
af51160e | 747 | void __init smp_detect_cpus(void) |
48483b32 | 748 | { |
10ad34bc | 749 | unsigned int cpu, mtid, c_cpus, s_cpus; |
d08d9430 | 750 | struct sclp_core_info *info; |
10ad34bc | 751 | u16 address; |
48483b32 | 752 | |
10ad34bc | 753 | /* Get CPU information */ |
af51160e HC |
754 | info = memblock_virt_alloc(sizeof(*info), 8); |
755 | smp_get_core_info(info, 1); | |
10ad34bc | 756 | /* Find boot CPU type */ |
d08d9430 | 757 | if (sclp.has_core_type) { |
10ad34bc MS |
758 | address = stap(); |
759 | for (cpu = 0; cpu < info->combined; cpu++) | |
d08d9430 | 760 | if (info->core[cpu].core_id == address) { |
10ad34bc | 761 | /* The boot cpu dictates the cpu type. */ |
d08d9430 | 762 | boot_core_type = info->core[cpu].type; |
10ad34bc MS |
763 | break; |
764 | } | |
765 | if (cpu >= info->combined) | |
766 | panic("Could not find boot CPU type"); | |
48483b32 | 767 | } |
10ad34bc | 768 | |
10ad34bc | 769 | /* Set multi-threading state for the current system */ |
d08d9430 | 770 | mtid = boot_core_type ? sclp.mtid : sclp.mtid_cp; |
10ad34bc MS |
771 | mtid = (mtid < smp_max_threads) ? mtid : smp_max_threads - 1; |
772 | pcpu_set_smt(mtid); | |
773 | ||
774 | /* Print number of CPUs */ | |
8b646bd7 | 775 | c_cpus = s_cpus = 0; |
48483b32 | 776 | for (cpu = 0; cpu < info->combined; cpu++) { |
d08d9430 MS |
777 | if (sclp.has_core_type && |
778 | info->core[cpu].type != boot_core_type) | |
48483b32 | 779 | continue; |
10ad34bc MS |
780 | if (cpu < info->configured) |
781 | c_cpus += smp_cpu_mtid + 1; | |
782 | else | |
783 | s_cpus += smp_cpu_mtid + 1; | |
48483b32 | 784 | } |
395d31d4 | 785 | pr_info("%d configured CPUs, %d standby CPUs\n", c_cpus, s_cpus); |
10ad34bc MS |
786 | |
787 | /* Add CPUs present at boot */ | |
9d40d2e3 | 788 | get_online_cpus(); |
8b646bd7 | 789 | __smp_rescan_cpus(info, 0); |
9d40d2e3 | 790 | put_online_cpus(); |
af51160e | 791 | memblock_free_early((unsigned long)info, sizeof(*info)); |
48483b32 HC |
792 | } |
793 | ||
1da177e4 | 794 | /* |
39ce010d | 795 | * Activate a secondary processor. |
1da177e4 | 796 | */ |
e2741f17 | 797 | static void smp_start_secondary(void *cpuvoid) |
1da177e4 | 798 | { |
1887aa07 MS |
799 | int cpu = smp_processor_id(); |
800 | ||
1aae0560 | 801 | S390_lowcore.last_update_clock = get_tod_clock(); |
8b646bd7 MS |
802 | S390_lowcore.restart_stack = (unsigned long) restart_stack; |
803 | S390_lowcore.restart_fn = (unsigned long) do_restart; | |
804 | S390_lowcore.restart_data = 0; | |
805 | S390_lowcore.restart_source = -1UL; | |
806 | restore_access_regs(S390_lowcore.access_regs_save_area); | |
807 | __ctl_load(S390_lowcore.cregs_save_area, 0, 15); | |
e258d719 | 808 | __load_psw_mask(PSW_KERNEL_BITS | PSW_MASK_DAT); |
39ce010d | 809 | cpu_init(); |
5bfb5d69 | 810 | preempt_disable(); |
39ce010d | 811 | init_cpu_timer(); |
b5f87f15 | 812 | vtime_init(); |
29b08d2b | 813 | pfault_init(); |
1887aa07 MS |
814 | notify_cpu_starting(cpu); |
815 | if (topology_cpu_dedicated(cpu)) | |
816 | set_cpu_flag(CIF_DEDICATED_CPU); | |
817 | else | |
818 | clear_cpu_flag(CIF_DEDICATED_CPU); | |
819 | set_cpu_online(cpu, true); | |
93f3b2ee | 820 | inc_irq_stat(CPU_RST); |
1da177e4 | 821 | local_irq_enable(); |
fc6d73d6 | 822 | cpu_startup_entry(CPUHP_AP_ONLINE_IDLE); |
1da177e4 LT |
823 | } |
824 | ||
1da177e4 | 825 | /* Upping and downing of CPUs */ |
e2741f17 | 826 | int __cpu_up(unsigned int cpu, struct task_struct *tidle) |
1da177e4 | 827 | { |
8b646bd7 | 828 | struct pcpu *pcpu; |
10ad34bc | 829 | int base, i, rc; |
1da177e4 | 830 | |
8b646bd7 MS |
831 | pcpu = pcpu_devices + cpu; |
832 | if (pcpu->state != CPU_STATE_CONFIGURED) | |
08d07968 | 833 | return -EIO; |
5423145f | 834 | base = smp_get_base_cpu(cpu); |
10ad34bc MS |
835 | for (i = 0; i <= smp_cpu_mtid; i++) { |
836 | if (base + i < nr_cpu_ids) | |
837 | if (cpu_online(base + i)) | |
838 | break; | |
839 | } | |
840 | /* | |
841 | * If this is the first CPU of the core to get online | |
842 | * do an initial CPU reset. | |
843 | */ | |
844 | if (i > smp_cpu_mtid && | |
845 | pcpu_sigp_retry(pcpu_devices + base, SIGP_INITIAL_CPU_RESET, 0) != | |
a9ae32c3 | 846 | SIGP_CC_ORDER_CODE_ACCEPTED) |
08d07968 | 847 | return -EIO; |
e80e7813 | 848 | |
8b646bd7 MS |
849 | rc = pcpu_alloc_lowcore(pcpu, cpu); |
850 | if (rc) | |
851 | return rc; | |
852 | pcpu_prepare_secondary(pcpu, cpu); | |
e80e7813 | 853 | pcpu_attach_task(pcpu, tidle); |
8b646bd7 | 854 | pcpu_start_fn(pcpu, smp_start_secondary, NULL); |
a1307bba | 855 | /* Wait until cpu puts itself in the online & active maps */ |
e9d867a6 | 856 | while (!cpu_online(cpu)) |
1da177e4 LT |
857 | cpu_relax(); |
858 | return 0; | |
859 | } | |
860 | ||
d80512f8 | 861 | static unsigned int setup_possible_cpus __initdata; |
255acee7 | 862 | |
d80512f8 HC |
863 | static int __init _setup_possible_cpus(char *s) |
864 | { | |
865 | get_option(&s, &setup_possible_cpus); | |
37a33026 HC |
866 | return 0; |
867 | } | |
d80512f8 | 868 | early_param("possible_cpus", _setup_possible_cpus); |
37a33026 | 869 | |
48483b32 HC |
870 | #ifdef CONFIG_HOTPLUG_CPU |
871 | ||
39ce010d | 872 | int __cpu_disable(void) |
1da177e4 | 873 | { |
8b646bd7 | 874 | unsigned long cregs[16]; |
1da177e4 | 875 | |
9acf73b7 HC |
876 | /* Handle possible pending IPIs */ |
877 | smp_handle_ext_call(); | |
8b646bd7 MS |
878 | set_cpu_online(smp_processor_id(), false); |
879 | /* Disable pseudo page faults on this cpu. */ | |
29b08d2b | 880 | pfault_fini(); |
8b646bd7 MS |
881 | /* Disable interrupt sources via control register. */ |
882 | __ctl_store(cregs, 0, 15); | |
883 | cregs[0] &= ~0x0000ee70UL; /* disable all external interrupts */ | |
884 | cregs[6] &= ~0xff000000UL; /* disable all I/O interrupts */ | |
885 | cregs[14] &= ~0x1f000000UL; /* disable most machine checks */ | |
886 | __ctl_load(cregs, 0, 15); | |
fe0f4976 | 887 | clear_cpu_flag(CIF_NOHZ_DELAY); |
1da177e4 LT |
888 | return 0; |
889 | } | |
890 | ||
39ce010d | 891 | void __cpu_die(unsigned int cpu) |
1da177e4 | 892 | { |
8b646bd7 MS |
893 | struct pcpu *pcpu; |
894 | ||
1da177e4 | 895 | /* Wait until target cpu is down */ |
8b646bd7 MS |
896 | pcpu = pcpu_devices + cpu; |
897 | while (!pcpu_stopped(pcpu)) | |
1da177e4 | 898 | cpu_relax(); |
8b646bd7 | 899 | pcpu_free_lowcore(pcpu); |
1b948d6c | 900 | cpumask_clear_cpu(cpu, mm_cpumask(&init_mm)); |
64f31d58 | 901 | cpumask_clear_cpu(cpu, &init_mm.context.cpu_attach_mask); |
1da177e4 LT |
902 | } |
903 | ||
b456d94a | 904 | void __noreturn cpu_die(void) |
1da177e4 LT |
905 | { |
906 | idle_task_exit(); | |
d768bd89 | 907 | __bpon(); |
a9ae32c3 | 908 | pcpu_sigp_retry(pcpu_devices + smp_processor_id(), SIGP_STOP, 0); |
8b646bd7 | 909 | for (;;) ; |
1da177e4 LT |
910 | } |
911 | ||
255acee7 HC |
912 | #endif /* CONFIG_HOTPLUG_CPU */ |
913 | ||
d80512f8 HC |
914 | void __init smp_fill_possible_mask(void) |
915 | { | |
9747bc47 | 916 | unsigned int possible, sclp_max, cpu; |
d80512f8 | 917 | |
3a9f3fe6 DH |
918 | sclp_max = max(sclp.mtid, sclp.mtid_cp) + 1; |
919 | sclp_max = min(smp_max_threads, sclp_max); | |
61282aff | 920 | sclp_max = (sclp.max_cores * sclp_max) ?: nr_cpu_ids; |
cf813db0 | 921 | possible = setup_possible_cpus ?: nr_cpu_ids; |
9747bc47 | 922 | possible = min(possible, sclp_max); |
d80512f8 HC |
923 | for (cpu = 0; cpu < possible && cpu < nr_cpu_ids; cpu++) |
924 | set_cpu_possible(cpu, true); | |
925 | } | |
926 | ||
1da177e4 LT |
927 | void __init smp_prepare_cpus(unsigned int max_cpus) |
928 | { | |
39ce010d | 929 | /* request the 0x1201 emergency signal external interrupt */ |
1dad093b | 930 | if (register_external_irq(EXT_IRQ_EMERGENCY_SIG, do_ext_call_interrupt)) |
39ce010d | 931 | panic("Couldn't request external interrupt 0x1201"); |
d98e19cc | 932 | /* request the 0x1202 external call external interrupt */ |
1dad093b | 933 | if (register_external_irq(EXT_IRQ_EXTERNAL_CALL, do_ext_call_interrupt)) |
d98e19cc | 934 | panic("Couldn't request external interrupt 0x1202"); |
1da177e4 LT |
935 | } |
936 | ||
ea1f4eec | 937 | void __init smp_prepare_boot_cpu(void) |
1da177e4 | 938 | { |
8b646bd7 MS |
939 | struct pcpu *pcpu = pcpu_devices; |
940 | ||
0861b5a7 | 941 | WARN_ON(!cpu_present(0) || !cpu_online(0)); |
8b646bd7 | 942 | pcpu->state = CPU_STATE_CONFIGURED; |
c667aeac | 943 | pcpu->lowcore = (struct lowcore *)(unsigned long) store_prefix(); |
1da177e4 | 944 | S390_lowcore.percpu_offset = __per_cpu_offset[0]; |
50ab9a9a | 945 | smp_cpu_set_polarization(0, POLARIZATION_UNKNOWN); |
1da177e4 LT |
946 | } |
947 | ||
ea1f4eec | 948 | void __init smp_cpus_done(unsigned int max_cpus) |
1da177e4 | 949 | { |
1da177e4 LT |
950 | } |
951 | ||
02beaccc HC |
952 | void __init smp_setup_processor_id(void) |
953 | { | |
0861b5a7 | 954 | pcpu_devices[0].address = stap(); |
02beaccc | 955 | S390_lowcore.cpu_nr = 0; |
6c8cd5bb | 956 | S390_lowcore.spinlock_lockval = arch_spin_lockval(0); |
b96f7d88 | 957 | S390_lowcore.spinlock_index = 0; |
02beaccc HC |
958 | } |
959 | ||
1da177e4 LT |
960 | /* |
961 | * the frequency of the profiling timer can be changed | |
962 | * by writing a multiplier value into /proc/profile. | |
963 | * | |
964 | * usually you want to run this on all CPUs ;) | |
965 | */ | |
966 | int setup_profiling_timer(unsigned int multiplier) | |
967 | { | |
39ce010d | 968 | return 0; |
1da177e4 LT |
969 | } |
970 | ||
08d07968 | 971 | #ifdef CONFIG_HOTPLUG_CPU |
8a25a2fd | 972 | static ssize_t cpu_configure_show(struct device *dev, |
8b646bd7 | 973 | struct device_attribute *attr, char *buf) |
08d07968 HC |
974 | { |
975 | ssize_t count; | |
976 | ||
977 | mutex_lock(&smp_cpu_state_mutex); | |
8b646bd7 | 978 | count = sprintf(buf, "%d\n", pcpu_devices[dev->id].state); |
08d07968 HC |
979 | mutex_unlock(&smp_cpu_state_mutex); |
980 | return count; | |
981 | } | |
982 | ||
8a25a2fd | 983 | static ssize_t cpu_configure_store(struct device *dev, |
8b646bd7 MS |
984 | struct device_attribute *attr, |
985 | const char *buf, size_t count) | |
08d07968 | 986 | { |
8b646bd7 | 987 | struct pcpu *pcpu; |
10ad34bc | 988 | int cpu, val, rc, i; |
08d07968 HC |
989 | char delim; |
990 | ||
991 | if (sscanf(buf, "%d %c", &val, &delim) != 1) | |
992 | return -EINVAL; | |
993 | if (val != 0 && val != 1) | |
994 | return -EINVAL; | |
9d40d2e3 | 995 | get_online_cpus(); |
0b18d318 | 996 | mutex_lock(&smp_cpu_state_mutex); |
08d07968 | 997 | rc = -EBUSY; |
2c2df118 | 998 | /* disallow configuration changes of online cpus and cpu 0 */ |
8b646bd7 | 999 | cpu = dev->id; |
5423145f | 1000 | cpu = smp_get_base_cpu(cpu); |
10ad34bc | 1001 | if (cpu == 0) |
08d07968 | 1002 | goto out; |
10ad34bc MS |
1003 | for (i = 0; i <= smp_cpu_mtid; i++) |
1004 | if (cpu_online(cpu + i)) | |
1005 | goto out; | |
8b646bd7 | 1006 | pcpu = pcpu_devices + cpu; |
08d07968 HC |
1007 | rc = 0; |
1008 | switch (val) { | |
1009 | case 0: | |
8b646bd7 MS |
1010 | if (pcpu->state != CPU_STATE_CONFIGURED) |
1011 | break; | |
d08d9430 | 1012 | rc = sclp_core_deconfigure(pcpu->address >> smp_cpu_mt_shift); |
8b646bd7 MS |
1013 | if (rc) |
1014 | break; | |
10ad34bc MS |
1015 | for (i = 0; i <= smp_cpu_mtid; i++) { |
1016 | if (cpu + i >= nr_cpu_ids || !cpu_present(cpu + i)) | |
1017 | continue; | |
1018 | pcpu[i].state = CPU_STATE_STANDBY; | |
1019 | smp_cpu_set_polarization(cpu + i, | |
1020 | POLARIZATION_UNKNOWN); | |
1021 | } | |
8b646bd7 | 1022 | topology_expect_change(); |
08d07968 HC |
1023 | break; |
1024 | case 1: | |
8b646bd7 MS |
1025 | if (pcpu->state != CPU_STATE_STANDBY) |
1026 | break; | |
d08d9430 | 1027 | rc = sclp_core_configure(pcpu->address >> smp_cpu_mt_shift); |
8b646bd7 MS |
1028 | if (rc) |
1029 | break; | |
10ad34bc MS |
1030 | for (i = 0; i <= smp_cpu_mtid; i++) { |
1031 | if (cpu + i >= nr_cpu_ids || !cpu_present(cpu + i)) | |
1032 | continue; | |
1033 | pcpu[i].state = CPU_STATE_CONFIGURED; | |
1034 | smp_cpu_set_polarization(cpu + i, | |
1035 | POLARIZATION_UNKNOWN); | |
1036 | } | |
8b646bd7 | 1037 | topology_expect_change(); |
08d07968 HC |
1038 | break; |
1039 | default: | |
1040 | break; | |
1041 | } | |
1042 | out: | |
08d07968 | 1043 | mutex_unlock(&smp_cpu_state_mutex); |
0b18d318 | 1044 | put_online_cpus(); |
08d07968 HC |
1045 | return rc ? rc : count; |
1046 | } | |
8a25a2fd | 1047 | static DEVICE_ATTR(configure, 0644, cpu_configure_show, cpu_configure_store); |
08d07968 HC |
1048 | #endif /* CONFIG_HOTPLUG_CPU */ |
1049 | ||
8a25a2fd KS |
1050 | static ssize_t show_cpu_address(struct device *dev, |
1051 | struct device_attribute *attr, char *buf) | |
08d07968 | 1052 | { |
8b646bd7 | 1053 | return sprintf(buf, "%d\n", pcpu_devices[dev->id].address); |
08d07968 | 1054 | } |
8a25a2fd | 1055 | static DEVICE_ATTR(address, 0444, show_cpu_address, NULL); |
08d07968 | 1056 | |
08d07968 HC |
1057 | static struct attribute *cpu_common_attrs[] = { |
1058 | #ifdef CONFIG_HOTPLUG_CPU | |
8a25a2fd | 1059 | &dev_attr_configure.attr, |
08d07968 | 1060 | #endif |
8a25a2fd | 1061 | &dev_attr_address.attr, |
08d07968 HC |
1062 | NULL, |
1063 | }; | |
1064 | ||
1065 | static struct attribute_group cpu_common_attr_group = { | |
1066 | .attrs = cpu_common_attrs, | |
1067 | }; | |
1da177e4 | 1068 | |
08d07968 | 1069 | static struct attribute *cpu_online_attrs[] = { |
8a25a2fd KS |
1070 | &dev_attr_idle_count.attr, |
1071 | &dev_attr_idle_time_us.attr, | |
fae8b22d HC |
1072 | NULL, |
1073 | }; | |
1074 | ||
08d07968 HC |
1075 | static struct attribute_group cpu_online_attr_group = { |
1076 | .attrs = cpu_online_attrs, | |
fae8b22d HC |
1077 | }; |
1078 | ||
dfbbd86a | 1079 | static int smp_cpu_online(unsigned int cpu) |
2fc2d1e9 | 1080 | { |
2f859d0d | 1081 | struct device *s = &per_cpu(cpu_device, cpu)->dev; |
2fc2d1e9 | 1082 | |
dfbbd86a SAS |
1083 | return sysfs_create_group(&s->kobj, &cpu_online_attr_group); |
1084 | } | |
1085 | static int smp_cpu_pre_down(unsigned int cpu) | |
1086 | { | |
1087 | struct device *s = &per_cpu(cpu_device, cpu)->dev; | |
1088 | ||
1089 | sysfs_remove_group(&s->kobj, &cpu_online_attr_group); | |
1090 | return 0; | |
2fc2d1e9 HC |
1091 | } |
1092 | ||
e2741f17 | 1093 | static int smp_add_present_cpu(int cpu) |
08d07968 | 1094 | { |
96619fc1 HC |
1095 | struct device *s; |
1096 | struct cpu *c; | |
08d07968 HC |
1097 | int rc; |
1098 | ||
96619fc1 HC |
1099 | c = kzalloc(sizeof(*c), GFP_KERNEL); |
1100 | if (!c) | |
1101 | return -ENOMEM; | |
2f859d0d | 1102 | per_cpu(cpu_device, cpu) = c; |
96619fc1 | 1103 | s = &c->dev; |
08d07968 HC |
1104 | c->hotpluggable = 1; |
1105 | rc = register_cpu(c, cpu); | |
1106 | if (rc) | |
1107 | goto out; | |
1108 | rc = sysfs_create_group(&s->kobj, &cpu_common_attr_group); | |
1109 | if (rc) | |
1110 | goto out_cpu; | |
83a24e32 HC |
1111 | rc = topology_cpu_init(c); |
1112 | if (rc) | |
1113 | goto out_topology; | |
1114 | return 0; | |
1115 | ||
1116 | out_topology: | |
08d07968 HC |
1117 | sysfs_remove_group(&s->kobj, &cpu_common_attr_group); |
1118 | out_cpu: | |
1119 | #ifdef CONFIG_HOTPLUG_CPU | |
1120 | unregister_cpu(c); | |
1121 | #endif | |
1122 | out: | |
1123 | return rc; | |
1124 | } | |
1125 | ||
1126 | #ifdef CONFIG_HOTPLUG_CPU | |
1e489518 | 1127 | |
67060d9c | 1128 | int __ref smp_rescan_cpus(void) |
08d07968 | 1129 | { |
d08d9430 | 1130 | struct sclp_core_info *info; |
8b646bd7 | 1131 | int nr; |
08d07968 | 1132 | |
af51160e | 1133 | info = kzalloc(sizeof(*info), GFP_KERNEL); |
8b646bd7 MS |
1134 | if (!info) |
1135 | return -ENOMEM; | |
af51160e | 1136 | smp_get_core_info(info, 0); |
9d40d2e3 | 1137 | get_online_cpus(); |
0b18d318 | 1138 | mutex_lock(&smp_cpu_state_mutex); |
8b646bd7 | 1139 | nr = __smp_rescan_cpus(info, 1); |
08d07968 | 1140 | mutex_unlock(&smp_cpu_state_mutex); |
0b18d318 | 1141 | put_online_cpus(); |
8b646bd7 MS |
1142 | kfree(info); |
1143 | if (nr) | |
c10fde0d | 1144 | topology_schedule_update(); |
8b646bd7 | 1145 | return 0; |
1e489518 HC |
1146 | } |
1147 | ||
8a25a2fd KS |
1148 | static ssize_t __ref rescan_store(struct device *dev, |
1149 | struct device_attribute *attr, | |
c9be0a36 | 1150 | const char *buf, |
1e489518 HC |
1151 | size_t count) |
1152 | { | |
1153 | int rc; | |
1154 | ||
1155 | rc = smp_rescan_cpus(); | |
08d07968 HC |
1156 | return rc ? rc : count; |
1157 | } | |
6cbaefb4 | 1158 | static DEVICE_ATTR_WO(rescan); |
08d07968 HC |
1159 | #endif /* CONFIG_HOTPLUG_CPU */ |
1160 | ||
83a24e32 | 1161 | static int __init s390_smp_init(void) |
1da177e4 | 1162 | { |
f4edbcd5 | 1163 | int cpu, rc = 0; |
2fc2d1e9 | 1164 | |
08d07968 | 1165 | #ifdef CONFIG_HOTPLUG_CPU |
8a25a2fd | 1166 | rc = device_create_file(cpu_subsys.dev_root, &dev_attr_rescan); |
08d07968 HC |
1167 | if (rc) |
1168 | return rc; | |
1169 | #endif | |
1170 | for_each_present_cpu(cpu) { | |
1171 | rc = smp_add_present_cpu(cpu); | |
fae8b22d | 1172 | if (rc) |
f4edbcd5 | 1173 | goto out; |
1da177e4 | 1174 | } |
f4edbcd5 | 1175 | |
dfbbd86a SAS |
1176 | rc = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "s390/smp:online", |
1177 | smp_cpu_online, smp_cpu_pre_down); | |
e1108e8f | 1178 | rc = rc <= 0 ? rc : 0; |
f4edbcd5 | 1179 | out: |
f4edbcd5 | 1180 | return rc; |
1da177e4 | 1181 | } |
83a24e32 | 1182 | subsys_initcall(s390_smp_init); |