projects / linux-block.git / blame
| Commit | Line | Data |
|---|---|---|
| b2441318 | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
| 1da177e4 | 2 | /* |
| a53c8fab | 3 | * Copyright IBM Corp 2000, 2011 |
| c70d0fef HC |
4 | * Author(s): Holger Smolinski <Holger.Smolinski@de.ibm.com>, |
| 5 | * Denis Joseph Barrow, | |
| 1da177e4 LT |
6 | */ |
| 7 | ||
| 144d634a | 8 | #include <linux/linkage.h> |
| cbb870c8 | 9 | #include <asm/asm-offsets.h> |
| c50c84c3 | 10 | #include <asm/nospec-insn.h> |
| eb546195 | 11 | #include <asm/sigp.h> |
| c5dd8586 | 12 | |
| c50c84c3 MS |
13 | GEN_BR_THUNK %r9 |
| 14 | ||
| ef1daec8 | 15 | # |
| 1a36a39e MS |
16 | # Issue "store status" for the current CPU to its prefix page |
| 17 | # and call passed function afterwards | |
| ef1daec8 | 18 | # |
| 1a36a39e MS |
19 | # r2 = Function to be called after store status |
| 20 | # r3 = Parameter for function | |
| ef1daec8 MH |
21 | # |
| 22 | ENTRY(store_status) | |
| 23 | /* Save register one and load save area base */ | |
| c5328901 | 24 | stg %r1,__LC_SAVE_AREA_RESTART |
| ef1daec8 | 25 | /* General purpose registers */ |
| f08b8414 MS |
26 | lghi %r1,__LC_GPREGS_SAVE_AREA |
| 27 | stmg %r0,%r15,0(%r1) | |
| 28 | mvc 8(8,%r1),__LC_SAVE_AREA_RESTART | |
| ef1daec8 | 29 | /* Control registers */ |
| f08b8414 MS |
30 | lghi %r1,__LC_CREGS_SAVE_AREA |
| 31 | stctg %c0,%c15,0(%r1) | |
| ef1daec8 | 32 | /* Access registers */ |
| f08b8414 MS |
33 | lghi %r1,__LC_AREGS_SAVE_AREA |
| 34 | stam %a0,%a15,0(%r1) | |
| ef1daec8 | 35 | /* Floating point registers */ |
| f08b8414 MS |
36 | lghi %r1,__LC_FPREGS_SAVE_AREA |
| 37 | std %f0, 0x00(%r1) | |
| 38 | std %f1, 0x08(%r1) | |
| 39 | std %f2, 0x10(%r1) | |
| 40 | std %f3, 0x18(%r1) | |
| 41 | std %f4, 0x20(%r1) | |
| 42 | std %f5, 0x28(%r1) | |
| 43 | std %f6, 0x30(%r1) | |
| 44 | std %f7, 0x38(%r1) | |
| 45 | std %f8, 0x40(%r1) | |
| 46 | std %f9, 0x48(%r1) | |
| 47 | std %f10,0x50(%r1) | |
| 48 | std %f11,0x58(%r1) | |
| 49 | std %f12,0x60(%r1) | |
| 50 | std %f13,0x68(%r1) | |
| 51 | std %f14,0x70(%r1) | |
| 52 | std %f15,0x78(%r1) | |
| ef1daec8 | 53 | /* Floating point control register */ |
| f08b8414 MS |
54 | lghi %r1,__LC_FP_CREG_SAVE_AREA |
| 55 | stfpc 0(%r1) | |
| ef1daec8 | 56 | /* CPU timer */ |
| f08b8414 MS |
57 | lghi %r1,__LC_CPU_TIMER_SAVE_AREA |
| 58 | stpt 0(%r1) | |
| 1a36a39e | 59 | /* Store prefix register */ |
| f08b8414 | 60 | lghi %r1,__LC_PREFIX_SAVE_AREA |
| 1a36a39e | 61 | stpx 0(%r1) |
| ef1daec8 | 62 | /* Clock comparator - seven bytes */ |
| f08b8414 | 63 | lghi %r1,__LC_CLOCK_COMP_SAVE_AREA |
| 1a36a39e MS |
64 | larl %r4,.Lclkcmp |
| 65 | stckc 0(%r4) | |
| 66 | mvc 1(7,%r1),1(%r4) | |
| ef1daec8 | 67 | /* Program status word */ |
| f08b8414 | 68 | lghi %r1,__LC_PSW_SAVE_AREA |
| 1a36a39e MS |
69 | epsw %r4,%r5 |
| 70 | st %r4,0(%r1) | |
| 71 | st %r5,4(%r1) | |
| f08b8414 | 72 | stg %r2,8(%r1) |
| c50c84c3 | 73 | lgr %r9,%r2 |
| 1a36a39e | 74 | lgr %r2,%r3 |
| c50c84c3 | 75 | BR_EX %r9 |
| 26a374ae | 76 | ENDPROC(store_status) |
| 60a0c68d MH |
77 | |
| 78 | .section .bss | |
| 79 | .align 8 | |
| ef1daec8 | 80 | .Lclkcmp: .quad 0x0000000000000000 |
| 60a0c68d | 81 | .previous |