[linux-block.git] / arch / s390 / kernel / processor.c

// SPDX-License-Identifier: GPL-2.0
/*
 *  Copyright IBM Corp. 2008
 *  Author(s): Martin Schwidefsky (schwidefsky@de.ibm.com)
 */

#define KMSG_COMPONENT "cpu"
#define pr_fmt(fmt) KMSG_COMPONENT ": " fmt

#include <linux/stop_machine.h>
#include <linux/cpufeature.h>
#include <linux/bitops.h>
#include <linux/kernel.h>
#include <linux/random.h>
#include <linux/sched/mm.h>
#include <linux/init.h>
#include <linux/seq_file.h>
#include <linux/mm_types.h>
#include <linux/delay.h>
#include <linux/cpu.h>
#include <linux/smp.h>
#include <asm/text-patching.h>
#include <asm/machine.h>
#include <asm/diag.h>
#include <asm/facility.h>
#include <asm/elf.h>
#include <asm/lowcore.h>
#include <asm/param.h>
#include <asm/sclp.h>
#include <asm/smp.h>

unsigned long __read_mostly elf_hwcap;
char elf_platform[ELF_PLATFORM_SIZE];

struct cpu_info {
	unsigned int cpu_mhz_dynamic;
	unsigned int cpu_mhz_static;
	struct cpuid cpu_id;
};

static DEFINE_PER_CPU(struct cpu_info, cpu_info);
static DEFINE_PER_CPU(int, cpu_relax_retry);

static bool machine_has_cpu_mhz;

void __init cpu_detect_mhz_feature(void)
{
	if (test_facility(34) && __ecag(ECAG_CPU_ATTRIBUTE, 0) != -1UL)
		machine_has_cpu_mhz = true;
}

static void update_cpu_mhz(void *arg)
{
	unsigned long mhz;
	struct cpu_info *c;

	mhz = __ecag(ECAG_CPU_ATTRIBUTE, 0);
	c = this_cpu_ptr(&cpu_info);
	c->cpu_mhz_dynamic = mhz >> 32;
	c->cpu_mhz_static = mhz & 0xffffffff;
}

void s390_update_cpu_mhz(void)
{
	s390_adjust_jiffies();
	if (machine_has_cpu_mhz)
		on_each_cpu(update_cpu_mhz, NULL, 0);
}

void notrace stop_machine_yield(const struct cpumask *cpumask)
{
	int cpu, this_cpu;

	this_cpu = smp_processor_id();
	if (__this_cpu_inc_return(cpu_relax_retry) >= spin_retry) {
		__this_cpu_write(cpu_relax_retry, 0);
		cpu = cpumask_next_wrap(this_cpu, cpumask);
		if (cpu >= nr_cpu_ids)
			return;
		if (arch_vcpu_is_preempted(cpu))
			smp_yield_cpu(cpu);
	}
}

static void do_sync_core(void *info)
{
	sync_core();
}

void text_poke_sync(void)
{
	on_each_cpu(do_sync_core, NULL, 1);
}

void text_poke_sync_lock(void)
{
	cpus_read_lock();
	text_poke_sync();
	cpus_read_unlock();
}

/*
 * cpu_init - initializes state that is per-CPU.
 */
void cpu_init(void)
{
	struct cpuid *id = this_cpu_ptr(&cpu_info.cpu_id);

	get_cpu_id(id);
	if (machine_has_cpu_mhz)
		update_cpu_mhz(NULL);
	mmgrab(&init_mm);
	current->active_mm = &init_mm;
	BUG_ON(current->mm);
	enter_lazy_tlb(&init_mm, current);
}

static void show_facilities(struct seq_file *m)
{
	unsigned int bit;

	seq_puts(m, "facilities      :");
	for_each_set_bit_inv(bit, (long *)&stfle_fac_list, MAX_FACILITY_BIT)
		seq_printf(m, " %d", bit);
	seq_putc(m, '\n');
}

static void show_cpu_summary(struct seq_file *m, void *v)
{
	static const char *hwcap_str[] = {
		[HWCAP_NR_ESAN3]	= "esan3",
		[HWCAP_NR_ZARCH]	= "zarch",
		[HWCAP_NR_STFLE]	= "stfle",
		[HWCAP_NR_MSA]		= "msa",
		[HWCAP_NR_LDISP]	= "ldisp",
		[HWCAP_NR_EIMM]		= "eimm",
		[HWCAP_NR_DFP]		= "dfp",
		[HWCAP_NR_HPAGE]	= "edat",
		[HWCAP_NR_ETF3EH]	= "etf3eh",
		[HWCAP_NR_HIGH_GPRS]	= "highgprs",
		[HWCAP_NR_TE]		= "te",
		[HWCAP_NR_VXRS]		= "vx",
		[HWCAP_NR_VXRS_BCD]	= "vxd",
		[HWCAP_NR_VXRS_EXT]	= "vxe",
		[HWCAP_NR_GS]		= "gs",
		[HWCAP_NR_VXRS_EXT2]	= "vxe2",
		[HWCAP_NR_VXRS_PDE]	= "vxp",
		[HWCAP_NR_SORT]		= "sort",
		[HWCAP_NR_DFLT]		= "dflt",
		[HWCAP_NR_VXRS_PDE2]	= "vxp2",
		[HWCAP_NR_NNPA]		= "nnpa",
		[HWCAP_NR_PCI_MIO]	= "pcimio",
		[HWCAP_NR_SIE]		= "sie",
	};
	int i, cpu;

	BUILD_BUG_ON(ARRAY_SIZE(hwcap_str) != HWCAP_NR_MAX);
	seq_printf(m, "vendor_id       : IBM/S390\n"
		   "# processors    : %i\n"
		   "bogomips per cpu: %lu.%02lu\n",
		   num_online_cpus(), loops_per_jiffy/(500000/HZ),
		   (loops_per_jiffy/(5000/HZ))%100);
	seq_printf(m, "max thread id   : %d\n", smp_cpu_mtid);
	seq_puts(m, "features\t: ");
	for (i = 0; i < ARRAY_SIZE(hwcap_str); i++)
		if (hwcap_str[i] && (elf_hwcap & (1UL << i)))
			seq_printf(m, "%s ", hwcap_str[i]);
	seq_puts(m, "\n");
	show_facilities(m);
	show_cacheinfo(m);
	for_each_online_cpu(cpu) {
		struct cpuid *id = &per_cpu(cpu_info.cpu_id, cpu);

		seq_printf(m, "processor %d: "
			   "version = %02X,  "
			   "identification = %06X,  "
			   "machine = %04X\n",
			   cpu, id->version, id->ident, id->machine);
	}
}

static int __init setup_hwcaps(void)
{
	/* instructions named N3, "backported" to esa-mode */
	elf_hwcap |= HWCAP_ESAN3;

	/* z/Architecture mode active */
	elf_hwcap |= HWCAP_ZARCH;

	/* store-facility-list-extended */
	if (test_facility(7))
		elf_hwcap |= HWCAP_STFLE;

	/* message-security assist */
	if (test_facility(17))
		elf_hwcap |= HWCAP_MSA;

	/* long-displacement */
	if (test_facility(19))
		elf_hwcap |= HWCAP_LDISP;

	/* extended-immediate */
	elf_hwcap |= HWCAP_EIMM;

	/* extended-translation facility 3 enhancement */
	if (test_facility(22) && test_facility(30))
		elf_hwcap |= HWCAP_ETF3EH;

	/* decimal floating point & perform floating point operation */
	if (test_facility(42) && test_facility(44))
		elf_hwcap |= HWCAP_DFP;

	/* huge page support */
	if (cpu_has_edat1())
		elf_hwcap |= HWCAP_HPAGE;

	/* 64-bit register support for 31-bit processes */
	elf_hwcap |= HWCAP_HIGH_GPRS;

	/* transactional execution */
	if (machine_has_tx())
		elf_hwcap |= HWCAP_TE;

	/* vector */
	if (test_facility(129)) {
		elf_hwcap |= HWCAP_VXRS;
		if (test_facility(134))
			elf_hwcap |= HWCAP_VXRS_BCD;
		if (test_facility(135))
			elf_hwcap |= HWCAP_VXRS_EXT;
		if (test_facility(148))
			elf_hwcap |= HWCAP_VXRS_EXT2;
		if (test_facility(152))
			elf_hwcap |= HWCAP_VXRS_PDE;
		if (test_facility(192))
			elf_hwcap |= HWCAP_VXRS_PDE2;
	}

	if (test_facility(150))
		elf_hwcap |= HWCAP_SORT;

	if (test_facility(151))
		elf_hwcap |= HWCAP_DFLT;

	if (test_facility(165))
		elf_hwcap |= HWCAP_NNPA;

	/* guarded storage */
	if (cpu_has_gs())
		elf_hwcap |= HWCAP_GS;

	if (test_machine_feature(MFEATURE_PCI_MIO))
		elf_hwcap |= HWCAP_PCI_MIO;

	/* virtualization support */
	if (sclp.has_sief2)
		elf_hwcap |= HWCAP_SIE;

	return 0;
}
arch_initcall(setup_hwcaps);

static int __init setup_elf_platform(void)
{
	struct cpuid cpu_id;

	get_cpu_id(&cpu_id);
	add_device_randomness(&cpu_id, sizeof(cpu_id));
	switch (cpu_id.machine) {
	default:	/* Use "z10" as default. */
		strscpy(elf_platform, "z10");
		break;
	case 0x2817:
	case 0x2818:
		strscpy(elf_platform, "z196");
		break;
	case 0x2827:
	case 0x2828:
		strscpy(elf_platform, "zEC12");
		break;
	case 0x2964:
	case 0x2965:
		strscpy(elf_platform, "z13");
		break;
	case 0x3906:
	case 0x3907:
		strscpy(elf_platform, "z14");
		break;
	case 0x8561:
	case 0x8562:
		strscpy(elf_platform, "z15");
		break;
	case 0x3931:
	case 0x3932:
		strscpy(elf_platform, "z16");
		break;
	case 0x9175:
	case 0x9176:
		strscpy(elf_platform, "z17");
		break;
	}
	return 0;
}
arch_initcall(setup_elf_platform);

static void show_cpu_topology(struct seq_file *m, unsigned long n)
{
#ifdef CONFIG_SCHED_TOPOLOGY
	seq_printf(m, "physical id     : %d\n", topology_physical_package_id(n));
	seq_printf(m, "core id         : %d\n", topology_core_id(n));
	seq_printf(m, "book id         : %d\n", topology_book_id(n));
	seq_printf(m, "drawer id       : %d\n", topology_drawer_id(n));
	seq_printf(m, "dedicated       : %d\n", topology_cpu_dedicated(n));
	seq_printf(m, "address         : %d\n", smp_cpu_get_cpu_address(n));
	seq_printf(m, "siblings        : %d\n", cpumask_weight(topology_core_cpumask(n)));
	seq_printf(m, "cpu cores       : %d\n", topology_booted_cores(n));
#endif /* CONFIG_SCHED_TOPOLOGY */
}

static void show_cpu_ids(struct seq_file *m, unsigned long n)
{
	struct cpuid *id = &per_cpu(cpu_info.cpu_id, n);

	seq_printf(m, "version         : %02X\n", id->version);
	seq_printf(m, "identification  : %06X\n", id->ident);
	seq_printf(m, "machine         : %04X\n", id->machine);
}

static void show_cpu_mhz(struct seq_file *m, unsigned long n)
{
	struct cpu_info *c = per_cpu_ptr(&cpu_info, n);

	if (!machine_has_cpu_mhz)
		return;
	seq_printf(m, "cpu MHz dynamic : %d\n", c->cpu_mhz_dynamic);
	seq_printf(m, "cpu MHz static  : %d\n", c->cpu_mhz_static);
}

/*
 * show_cpuinfo - Get information on one CPU for use by procfs.
 */
static int show_cpuinfo(struct seq_file *m, void *v)
{
	unsigned long n = (unsigned long) v - 1;
	unsigned long first = cpumask_first(cpu_online_mask);

	if (n == first)
		show_cpu_summary(m, v);
	seq_printf(m, "\ncpu number      : %ld\n", n);
	show_cpu_topology(m, n);
	show_cpu_ids(m, n);
	show_cpu_mhz(m, n);
	return 0;
}

static inline void *c_update(loff_t *pos)
{
	if (*pos)
		*pos = cpumask_next(*pos - 1, cpu_online_mask);
	else
		*pos = cpumask_first(cpu_online_mask);
	return *pos < nr_cpu_ids ? (void *)*pos + 1 : NULL;
}

static void *c_start(struct seq_file *m, loff_t *pos)
{
	cpus_read_lock();
	return c_update(pos);
}

static void *c_next(struct seq_file *m, void *v, loff_t *pos)
{
	++*pos;
	return c_update(pos);
}

static void c_stop(struct seq_file *m, void *v)
{
	cpus_read_unlock();
}

const struct seq_operations cpuinfo_op = {
	.start	= c_start,
	.next	= c_next,
	.stop	= c_stop,
	.show	= show_cpuinfo,
};
Commit	Line	Data
b2441318	1	// SPDX-License-Identifier: GPL-2.0
395d31d4	2	/*
395d31d4 MS	3	* Copyright IBM Corp. 2008
	4	* Author(s): Martin Schwidefsky (schwidefsky@de.ibm.com)
	5	*/
	6
	7	#define KMSG_COMPONENT "cpu"
	8	#define pr_fmt(fmt) KMSG_COMPONENT ": " fmt
	9
4ecf0a43	10	#include <linux/stop_machine.h>
42805261	11	#include <linux/cpufeature.h>
157467ba	12	#include <linux/bitops.h>
395d31d4	13	#include <linux/kernel.h>
f17a6d5d	14	#include <linux/random.h>
68e21be2	15	#include <linux/sched/mm.h>
395d31d4	16	#include <linux/init.h>
395d31d4	17	#include <linux/seq_file.h>
589ee628	18	#include <linux/mm_types.h>
395d31d4	19	#include <linux/delay.h>
19726cec	20	#include <linux/cpu.h>
ace76fac HC	21	#include <linux/smp.h>
ace76fac HC	22	#include <asm/text-patching.h>
a1a8da0d	23	#include <asm/machine.h>
1ec2772e	24	#include <asm/diag.h>
097a116c	25	#include <asm/facility.h>
395d31d4 MS	26	#include <asm/elf.h>
	27	#include <asm/lowcore.h>
	28	#include <asm/param.h>
f17a6d5d	29	#include <asm/sclp.h>
4d92f502	30	#include <asm/smp.h>
395d31d4	31
f17a6d5d HC	32	unsigned long __read_mostly elf_hwcap;
	33	char elf_platform[ELF_PLATFORM_SIZE];
	34
097a116c HC	35	struct cpu_info {
	36	unsigned int cpu_mhz_dynamic;
	37	unsigned int cpu_mhz_static;
	38	struct cpuid cpu_id;
	39	};
	40
	41	static DEFINE_PER_CPU(struct cpu_info, cpu_info);
38f2c691	42	static DEFINE_PER_CPU(int, cpu_relax_retry);
097a116c HC	43
	44	static bool machine_has_cpu_mhz;
	45
	46	void __init cpu_detect_mhz_feature(void)
	47	{
	48	if (test_facility(34) && __ecag(ECAG_CPU_ATTRIBUTE, 0) != -1UL)
970ba6ac	49	machine_has_cpu_mhz = true;
097a116c HC	50	}
	51
	52	static void update_cpu_mhz(void *arg)
	53	{
	54	unsigned long mhz;
	55	struct cpu_info *c;
	56
	57	mhz = __ecag(ECAG_CPU_ATTRIBUTE, 0);
	58	c = this_cpu_ptr(&cpu_info);
	59	c->cpu_mhz_dynamic = mhz >> 32;
	60	c->cpu_mhz_static = mhz & 0xffffffff;
	61	}
	62
	63	void s390_update_cpu_mhz(void)
	64	{
	65	s390_adjust_jiffies();
	66	if (machine_has_cpu_mhz)
	67	on_each_cpu(update_cpu_mhz, NULL, 0);
	68	}
94038a99	69
4ecf0a43	70	void notrace stop_machine_yield(const struct cpumask *cpumask)
4d92f502	71	{
38f2c691 MS	72	int cpu, this_cpu;
	73
	74	this_cpu = smp_processor_id();
	75	if (__this_cpu_inc_return(cpu_relax_retry) >= spin_retry) {
	76	__this_cpu_write(cpu_relax_retry, 0);
0cad4092	77	cpu = cpumask_next_wrap(this_cpu, cpumask);
38f2c691 MS	78	if (cpu >= nr_cpu_ids)
	79	return;
	80	if (arch_vcpu_is_preempted(cpu))
	81	smp_yield_cpu(cpu);
1ec2772e	82	}
4d92f502	83	}
4d92f502	84
ace76fac HC	85	static void do_sync_core(void *info)
	86	{
	87	sync_core();
	88	}
	89
	90	void text_poke_sync(void)
	91	{
	92	on_each_cpu(do_sync_core, NULL, 1);
	93	}
	94
	95	void text_poke_sync_lock(void)
	96	{
	97	cpus_read_lock();
	98	text_poke_sync();
	99	cpus_read_unlock();
	100	}
	101
94038a99 MS	102	/*
	103	* cpu_init - initializes state that is per-CPU.
	104	*/
e2741f17	105	void cpu_init(void)
94038a99	106	{
097a116c	107	struct cpuid *id = this_cpu_ptr(&cpu_info.cpu_id);
94038a99 MS	108
94038a99 MS	109	get_cpu_id(id);
097a116c HC	110	if (machine_has_cpu_mhz)
097a116c HC	111	update_cpu_mhz(NULL);
f1f10076	112	mmgrab(&init_mm);
94038a99 MS	113	current->active_mm = &init_mm;
	114	BUG_ON(current->mm);
	115	enter_lazy_tlb(&init_mm, current);
	116	}
	117
157467ba HC	118	static void show_facilities(struct seq_file *m)
	119	{
	120	unsigned int bit;
157467ba	121
157467ba	122	seq_puts(m, "facilities :");
17e89e13	123	for_each_set_bit_inv(bit, (long *)&stfle_fac_list, MAX_FACILITY_BIT)
157467ba HC	124	seq_printf(m, " %d", bit);
	125	seq_putc(m, '\n');
	126	}
	127
219a21b3	128	static void show_cpu_summary(struct seq_file m, void v)
395d31d4	129	{
fbf3c542	130	static const char *hwcap_str[] = {
95655495 HC	131	[HWCAP_NR_ESAN3] = "esan3",
	132	[HWCAP_NR_ZARCH] = "zarch",
	133	[HWCAP_NR_STFLE] = "stfle",
	134	[HWCAP_NR_MSA] = "msa",
	135	[HWCAP_NR_LDISP] = "ldisp",
	136	[HWCAP_NR_EIMM] = "eimm",
	137	[HWCAP_NR_DFP] = "dfp",
	138	[HWCAP_NR_HPAGE] = "edat",
	139	[HWCAP_NR_ETF3EH] = "etf3eh",
	140	[HWCAP_NR_HIGH_GPRS] = "highgprs",
	141	[HWCAP_NR_TE] = "te",
	142	[HWCAP_NR_VXRS] = "vx",
	143	[HWCAP_NR_VXRS_BCD] = "vxd",
	144	[HWCAP_NR_VXRS_EXT] = "vxe",
	145	[HWCAP_NR_GS] = "gs",
	146	[HWCAP_NR_VXRS_EXT2] = "vxe2",
	147	[HWCAP_NR_VXRS_PDE] = "vxp",
	148	[HWCAP_NR_SORT] = "sort",
	149	[HWCAP_NR_DFLT] = "dflt",
	150	[HWCAP_NR_VXRS_PDE2] = "vxp2",
	151	[HWCAP_NR_NNPA] = "nnpa",
	152	[HWCAP_NR_PCI_MIO] = "pcimio",
7e82523f	153	[HWCAP_NR_SIE] = "sie",
7f16d7e7	154	};
219a21b3 HC	155	int i, cpu;
219a21b3 HC	156
c68d4632	157	BUILD_BUG_ON(ARRAY_SIZE(hwcap_str) != HWCAP_NR_MAX);
219a21b3 HC	158	seq_printf(m, "vendor_id : IBM/S390\n"
	159	"# processors : %i\n"
	160	"bogomips per cpu: %lu.%02lu\n",
	161	num_online_cpus(), loops_per_jiffy/(500000/HZ),
	162	(loops_per_jiffy/(5000/HZ))%100);
10f4954a	163	seq_printf(m, "max thread id : %d\n", smp_cpu_mtid);
219a21b3 HC	164	seq_puts(m, "features\t: ");
	165	for (i = 0; i < ARRAY_SIZE(hwcap_str); i++)
	166	if (hwcap_str[i] && (elf_hwcap & (1UL << i)))
	167	seq_printf(m, "%s ", hwcap_str[i]);
219a21b3	168	seq_puts(m, "\n");
157467ba	169	show_facilities(m);
219a21b3 HC	170	show_cacheinfo(m);
219a21b3 HC	171	for_each_online_cpu(cpu) {
097a116c	172	struct cpuid *id = &per_cpu(cpu_info.cpu_id, cpu);
219a21b3 HC	173
219a21b3 HC	174	seq_printf(m, "processor %d: "
7b468488 MS	175	"version = %02X, "
	176	"identification = %06X, "
	177	"machine = %04X\n",
219a21b3	178	cpu, id->version, id->ident, id->machine);
7b468488	179	}
219a21b3 HC	180	}
219a21b3 HC	181
f17a6d5d HC	182	static int __init setup_hwcaps(void)
f17a6d5d HC	183	{
251527c9	184	/* instructions named N3, "backported" to esa-mode */
4efd417f	185	elf_hwcap \|= HWCAP_ESAN3;
251527c9 HC	186
251527c9 HC	187	/* z/Architecture mode active */
487dff56	188	elf_hwcap \|= HWCAP_ZARCH;
251527c9 HC	189
	190	/* store-facility-list-extended */
	191	if (test_facility(7))
	192	elf_hwcap \|= HWCAP_STFLE;
	193
	194	/* message-security assist */
	195	if (test_facility(17))
	196	elf_hwcap \|= HWCAP_MSA;
	197
	198	/* long-displacement */
	199	if (test_facility(19))
	200	elf_hwcap \|= HWCAP_LDISP;
	201
	202	/* extended-immediate */
4efd417f	203	elf_hwcap \|= HWCAP_EIMM;
f17a6d5d	204
449fbd71	205	/* extended-translation facility 3 enhancement */
f17a6d5d HC	206	if (test_facility(22) && test_facility(30))
	207	elf_hwcap \|= HWCAP_ETF3EH;
	208
449fbd71	209	/* decimal floating point & perform floating point operation */
98ac9169	210	if (test_facility(42) && test_facility(44))
f17a6d5d HC	211	elf_hwcap \|= HWCAP_DFP;
f17a6d5d HC	212
449fbd71	213	/* huge page support */
2e2ff71f	214	if (cpu_has_edat1())
f17a6d5d HC	215	elf_hwcap \|= HWCAP_HPAGE;
f17a6d5d HC	216
449fbd71	217	/* 64-bit register support for 31-bit processes */
f17a6d5d HC	218	elf_hwcap \|= HWCAP_HIGH_GPRS;
f17a6d5d HC	219
449fbd71	220	/* transactional execution */
e82462fb	221	if (machine_has_tx())
f17a6d5d HC	222	elf_hwcap \|= HWCAP_TE;
f17a6d5d HC	223
18564756 HC	224	/* vector */
18564756 HC	225	if (test_facility(129)) {
f17a6d5d HC	226	elf_hwcap \|= HWCAP_VXRS;
	227	if (test_facility(134))
	228	elf_hwcap \|= HWCAP_VXRS_BCD;
	229	if (test_facility(135))
	230	elf_hwcap \|= HWCAP_VXRS_EXT;
	231	if (test_facility(148))
	232	elf_hwcap \|= HWCAP_VXRS_EXT2;
	233	if (test_facility(152))
	234	elf_hwcap \|= HWCAP_VXRS_PDE;
	235	if (test_facility(192))
	236	elf_hwcap \|= HWCAP_VXRS_PDE2;
	237	}
449fbd71	238
f17a6d5d HC	239	if (test_facility(150))
f17a6d5d HC	240	elf_hwcap \|= HWCAP_SORT;
449fbd71	241
f17a6d5d HC	242	if (test_facility(151))
f17a6d5d HC	243	elf_hwcap \|= HWCAP_DFLT;
449fbd71	244
f17a6d5d HC	245	if (test_facility(165))
	246	elf_hwcap \|= HWCAP_NNPA;
	247
449fbd71	248	/* guarded storage */
42805261	249	if (cpu_has_gs())
f17a6d5d	250	elf_hwcap \|= HWCAP_GS;
449fbd71	251
a1a8da0d	252	if (test_machine_feature(MFEATURE_PCI_MIO))
f17a6d5d HC	253	elf_hwcap \|= HWCAP_PCI_MIO;
f17a6d5d HC	254
449fbd71	255	/* virtualization support */
873129ca	256	if (sclp.has_sief2)
7e82523f	257	elf_hwcap \|= HWCAP_SIE;
873129ca HC	258
	259	return 0;
	260	}
	261	arch_initcall(setup_hwcaps);
	262
	263	static int __init setup_elf_platform(void)
	264	{
	265	struct cpuid cpu_id;
	266
f17a6d5d HC	267	get_cpu_id(&cpu_id);
	268	add_device_randomness(&cpu_id, sizeof(cpu_id));
	269	switch (cpu_id.machine) {
4efd417f	270	default: /* Use "z10" as default. */
e76b8c1d	271	strscpy(elf_platform, "z10");
f17a6d5d HC	272	break;
	273	case 0x2817:
	274	case 0x2818:
e76b8c1d	275	strscpy(elf_platform, "z196");
f17a6d5d HC	276	break;
	277	case 0x2827:
	278	case 0x2828:
e76b8c1d	279	strscpy(elf_platform, "zEC12");
f17a6d5d HC	280	break;
	281	case 0x2964:
	282	case 0x2965:
e76b8c1d	283	strscpy(elf_platform, "z13");
f17a6d5d HC	284	break;
	285	case 0x3906:
	286	case 0x3907:
e76b8c1d	287	strscpy(elf_platform, "z14");
f17a6d5d HC	288	break;
	289	case 0x8561:
	290	case 0x8562:
e76b8c1d	291	strscpy(elf_platform, "z15");
f17a6d5d	292	break;
6203ac30 HC	293	case 0x3931:
6203ac30 HC	294	case 0x3932:
e76b8c1d	295	strscpy(elf_platform, "z16");
6203ac30	296	break;
8231a0e6 VG	297	case 0x9175:
8231a0e6 VG	298	case 0x9176:
e76b8c1d	299	strscpy(elf_platform, "z17");
8231a0e6	300	break;
f17a6d5d	301	}
f17a6d5d HC	302	return 0;
f17a6d5d HC	303	}
873129ca	304	arch_initcall(setup_elf_platform);
f17a6d5d	305
fb835102 AG	306	static void show_cpu_topology(struct seq_file *m, unsigned long n)
	307	{
	308	#ifdef CONFIG_SCHED_TOPOLOGY
	309	seq_printf(m, "physical id : %d\n", topology_physical_package_id(n));
	310	seq_printf(m, "core id : %d\n", topology_core_id(n));
	311	seq_printf(m, "book id : %d\n", topology_book_id(n));
	312	seq_printf(m, "drawer id : %d\n", topology_drawer_id(n));
	313	seq_printf(m, "dedicated : %d\n", topology_cpu_dedicated(n));
42d211a1	314	seq_printf(m, "address : %d\n", smp_cpu_get_cpu_address(n));
2db52dc3	315	seq_printf(m, "siblings : %d\n", cpumask_weight(topology_core_cpumask(n)));
95968497	316	seq_printf(m, "cpu cores : %d\n", topology_booted_cores(n));
fb835102 AG	317	#endif /* CONFIG_SCHED_TOPOLOGY */
	318	}
	319
	320	static void show_cpu_ids(struct seq_file *m, unsigned long n)
	321	{
	322	struct cpuid *id = &per_cpu(cpu_info.cpu_id, n);
	323
	324	seq_printf(m, "version : %02X\n", id->version);
	325	seq_printf(m, "identification : %06X\n", id->ident);
	326	seq_printf(m, "machine : %04X\n", id->machine);
	327	}
	328
097a116c HC	329	static void show_cpu_mhz(struct seq_file *m, unsigned long n)
	330	{
	331	struct cpu_info *c = per_cpu_ptr(&cpu_info, n);
	332
1b648dfd AG	333	if (!machine_has_cpu_mhz)
1b648dfd AG	334	return;
097a116c HC	335	seq_printf(m, "cpu MHz dynamic : %d\n", c->cpu_mhz_dynamic);
	336	seq_printf(m, "cpu MHz static : %d\n", c->cpu_mhz_static);
	337	}
	338
219a21b3 HC	339	/*
	340	* show_cpuinfo - Get information on one CPU for use by procfs.
	341	*/
	342	static int show_cpuinfo(struct seq_file m, void v)
	343	{
	344	unsigned long n = (unsigned long) v - 1;
872f2710	345	unsigned long first = cpumask_first(cpu_online_mask);
219a21b3	346
872f2710	347	if (n == first)
219a21b3	348	show_cpu_summary(m, v);
109ab954	349	seq_printf(m, "\ncpu number : %ld\n", n);
fb835102 AG	350	show_cpu_topology(m, n);
fb835102 AG	351	show_cpu_ids(m, n);
097a116c	352	show_cpu_mhz(m, n);
7b468488	353	return 0;
395d31d4 MS	354	}
395d31d4 MS	355
281eaa8c HC	356	static inline void c_update(loff_t pos)
	357	{
	358	if (*pos)
	359	pos = cpumask_next(pos - 1, cpu_online_mask);
872f2710 AG	360	else
872f2710 AG	361	*pos = cpumask_first(cpu_online_mask);
281eaa8c HC	362	return pos < nr_cpu_ids ? (void )*pos + 1 : NULL;
	363	}
	364
395d31d4 MS	365	static void c_start(struct seq_file m, loff_t *pos)
395d31d4 MS	366	{
a73de293	367	cpus_read_lock();
281eaa8c	368	return c_update(pos);
395d31d4 MS	369	}
	370
	371	static void c_next(struct seq_file m, void v, loff_t pos)
	372	{
	373	++*pos;
281eaa8c	374	return c_update(pos);
395d31d4 MS	375	}
	376
	377	static void c_stop(struct seq_file m, void v)
	378	{
a73de293	379	cpus_read_unlock();
395d31d4 MS	380	}
	381
	382	const struct seq_operations cpuinfo_op = {
	383	.start = c_start,
	384	.next = c_next,
	385	.stop = c_stop,
	386	.show = show_cpuinfo,
	387	};