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Merge branch 'for-4.18/hid-steam' into for-linus
[linux-2.6-block.git] / arch / s390 / kernel / perf_cpum_cf_events.c
CommitLineData
b2441318 1// SPDX-License-Identifier: GPL-2.0
c7168325
HB		 2/*
3 * Perf PMU sysfs events attributes for available CPU-measurement counters
4 *
5 */
6
7#include <linux/slab.h>
8#include <linux/perf_event.h>
9
10
11/* BEGIN: CPUM_CF COUNTER DEFINITIONS =================================== */
12
3593eb94
HB		 13CPUMF_EVENT_ATTR(cf_fvn1, CPU_CYCLES, 0x0000);
14CPUMF_EVENT_ATTR(cf_fvn1, INSTRUCTIONS, 0x0001);
15CPUMF_EVENT_ATTR(cf_fvn1, L1I_DIR_WRITES, 0x0002);
16CPUMF_EVENT_ATTR(cf_fvn1, L1I_PENALTY_CYCLES, 0x0003);
17CPUMF_EVENT_ATTR(cf_fvn1, PROBLEM_STATE_CPU_CYCLES, 0x0020);
18CPUMF_EVENT_ATTR(cf_fvn1, PROBLEM_STATE_INSTRUCTIONS, 0x0021);
19CPUMF_EVENT_ATTR(cf_fvn1, PROBLEM_STATE_L1I_DIR_WRITES, 0x0022);
20CPUMF_EVENT_ATTR(cf_fvn1, PROBLEM_STATE_L1I_PENALTY_CYCLES, 0x0023);
21CPUMF_EVENT_ATTR(cf_fvn1, PROBLEM_STATE_L1D_DIR_WRITES, 0x0024);
22CPUMF_EVENT_ATTR(cf_fvn1, PROBLEM_STATE_L1D_PENALTY_CYCLES, 0x0025);
23CPUMF_EVENT_ATTR(cf_fvn1, L1D_DIR_WRITES, 0x0004);
24CPUMF_EVENT_ATTR(cf_fvn1, L1D_PENALTY_CYCLES, 0x0005);
25CPUMF_EVENT_ATTR(cf_fvn3, CPU_CYCLES, 0x0000);
26CPUMF_EVENT_ATTR(cf_fvn3, INSTRUCTIONS, 0x0001);
27CPUMF_EVENT_ATTR(cf_fvn3, L1I_DIR_WRITES, 0x0002);
28CPUMF_EVENT_ATTR(cf_fvn3, L1I_PENALTY_CYCLES, 0x0003);
29CPUMF_EVENT_ATTR(cf_fvn3, PROBLEM_STATE_CPU_CYCLES, 0x0020);
30CPUMF_EVENT_ATTR(cf_fvn3, PROBLEM_STATE_INSTRUCTIONS, 0x0021);
31CPUMF_EVENT_ATTR(cf_fvn3, L1D_DIR_WRITES, 0x0004);
32CPUMF_EVENT_ATTR(cf_fvn3, L1D_PENALTY_CYCLES, 0x0005);
33CPUMF_EVENT_ATTR(cf_svn_generic, PRNG_FUNCTIONS, 0x0040);
34CPUMF_EVENT_ATTR(cf_svn_generic, PRNG_CYCLES, 0x0041);
35CPUMF_EVENT_ATTR(cf_svn_generic, PRNG_BLOCKED_FUNCTIONS, 0x0042);
36CPUMF_EVENT_ATTR(cf_svn_generic, PRNG_BLOCKED_CYCLES, 0x0043);
37CPUMF_EVENT_ATTR(cf_svn_generic, SHA_FUNCTIONS, 0x0044);
38CPUMF_EVENT_ATTR(cf_svn_generic, SHA_CYCLES, 0x0045);
39CPUMF_EVENT_ATTR(cf_svn_generic, SHA_BLOCKED_FUNCTIONS, 0x0046);
40CPUMF_EVENT_ATTR(cf_svn_generic, SHA_BLOCKED_CYCLES, 0x0047);
41CPUMF_EVENT_ATTR(cf_svn_generic, DEA_FUNCTIONS, 0x0048);
42CPUMF_EVENT_ATTR(cf_svn_generic, DEA_CYCLES, 0x0049);
43CPUMF_EVENT_ATTR(cf_svn_generic, DEA_BLOCKED_FUNCTIONS, 0x004a);
44CPUMF_EVENT_ATTR(cf_svn_generic, DEA_BLOCKED_CYCLES, 0x004b);
45CPUMF_EVENT_ATTR(cf_svn_generic, AES_FUNCTIONS, 0x004c);
46CPUMF_EVENT_ATTR(cf_svn_generic, AES_CYCLES, 0x004d);
47CPUMF_EVENT_ATTR(cf_svn_generic, AES_BLOCKED_FUNCTIONS, 0x004e);
48CPUMF_EVENT_ATTR(cf_svn_generic, AES_BLOCKED_CYCLES, 0x004f);
c7168325
HB		 49CPUMF_EVENT_ATTR(cf_z10, L1I_L2_SOURCED_WRITES, 0x0080);
50CPUMF_EVENT_ATTR(cf_z10, L1D_L2_SOURCED_WRITES, 0x0081);
51CPUMF_EVENT_ATTR(cf_z10, L1I_L3_LOCAL_WRITES, 0x0082);
52CPUMF_EVENT_ATTR(cf_z10, L1D_L3_LOCAL_WRITES, 0x0083);
53CPUMF_EVENT_ATTR(cf_z10, L1I_L3_REMOTE_WRITES, 0x0084);
54CPUMF_EVENT_ATTR(cf_z10, L1D_L3_REMOTE_WRITES, 0x0085);
55CPUMF_EVENT_ATTR(cf_z10, L1D_LMEM_SOURCED_WRITES, 0x0086);
56CPUMF_EVENT_ATTR(cf_z10, L1I_LMEM_SOURCED_WRITES, 0x0087);
57CPUMF_EVENT_ATTR(cf_z10, L1D_RO_EXCL_WRITES, 0x0088);
58CPUMF_EVENT_ATTR(cf_z10, L1I_CACHELINE_INVALIDATES, 0x0089);
59CPUMF_EVENT_ATTR(cf_z10, ITLB1_WRITES, 0x008a);
60CPUMF_EVENT_ATTR(cf_z10, DTLB1_WRITES, 0x008b);
61CPUMF_EVENT_ATTR(cf_z10, TLB2_PTE_WRITES, 0x008c);
62CPUMF_EVENT_ATTR(cf_z10, TLB2_CRSTE_WRITES, 0x008d);
63CPUMF_EVENT_ATTR(cf_z10, TLB2_CRSTE_HPAGE_WRITES, 0x008e);
64CPUMF_EVENT_ATTR(cf_z10, ITLB1_MISSES, 0x0091);
65CPUMF_EVENT_ATTR(cf_z10, DTLB1_MISSES, 0x0092);
66CPUMF_EVENT_ATTR(cf_z10, L2C_STORES_SENT, 0x0093);
67CPUMF_EVENT_ATTR(cf_z196, L1D_L2_SOURCED_WRITES, 0x0080);
68CPUMF_EVENT_ATTR(cf_z196, L1I_L2_SOURCED_WRITES, 0x0081);
69CPUMF_EVENT_ATTR(cf_z196, DTLB1_MISSES, 0x0082);
70CPUMF_EVENT_ATTR(cf_z196, ITLB1_MISSES, 0x0083);
71CPUMF_EVENT_ATTR(cf_z196, L2C_STORES_SENT, 0x0085);
72CPUMF_EVENT_ATTR(cf_z196, L1D_OFFBOOK_L3_SOURCED_WRITES, 0x0086);
73CPUMF_EVENT_ATTR(cf_z196, L1D_ONBOOK_L4_SOURCED_WRITES, 0x0087);
74CPUMF_EVENT_ATTR(cf_z196, L1I_ONBOOK_L4_SOURCED_WRITES, 0x0088);
75CPUMF_EVENT_ATTR(cf_z196, L1D_RO_EXCL_WRITES, 0x0089);
76CPUMF_EVENT_ATTR(cf_z196, L1D_OFFBOOK_L4_SOURCED_WRITES, 0x008a);
77CPUMF_EVENT_ATTR(cf_z196, L1I_OFFBOOK_L4_SOURCED_WRITES, 0x008b);
78CPUMF_EVENT_ATTR(cf_z196, DTLB1_HPAGE_WRITES, 0x008c);
79CPUMF_EVENT_ATTR(cf_z196, L1D_LMEM_SOURCED_WRITES, 0x008d);
80CPUMF_EVENT_ATTR(cf_z196, L1I_LMEM_SOURCED_WRITES, 0x008e);
81CPUMF_EVENT_ATTR(cf_z196, L1I_OFFBOOK_L3_SOURCED_WRITES, 0x008f);
82CPUMF_EVENT_ATTR(cf_z196, DTLB1_WRITES, 0x0090);
83CPUMF_EVENT_ATTR(cf_z196, ITLB1_WRITES, 0x0091);
84CPUMF_EVENT_ATTR(cf_z196, TLB2_PTE_WRITES, 0x0092);
85CPUMF_EVENT_ATTR(cf_z196, TLB2_CRSTE_HPAGE_WRITES, 0x0093);
86CPUMF_EVENT_ATTR(cf_z196, TLB2_CRSTE_WRITES, 0x0094);
87CPUMF_EVENT_ATTR(cf_z196, L1D_ONCHIP_L3_SOURCED_WRITES, 0x0096);
88CPUMF_EVENT_ATTR(cf_z196, L1D_OFFCHIP_L3_SOURCED_WRITES, 0x0098);
89CPUMF_EVENT_ATTR(cf_z196, L1I_ONCHIP_L3_SOURCED_WRITES, 0x0099);
90CPUMF_EVENT_ATTR(cf_z196, L1I_OFFCHIP_L3_SOURCED_WRITES, 0x009b);
91CPUMF_EVENT_ATTR(cf_zec12, DTLB1_MISSES, 0x0080);
92CPUMF_EVENT_ATTR(cf_zec12, ITLB1_MISSES, 0x0081);
93CPUMF_EVENT_ATTR(cf_zec12, L1D_L2I_SOURCED_WRITES, 0x0082);
94CPUMF_EVENT_ATTR(cf_zec12, L1I_L2I_SOURCED_WRITES, 0x0083);
95CPUMF_EVENT_ATTR(cf_zec12, L1D_L2D_SOURCED_WRITES, 0x0084);
96CPUMF_EVENT_ATTR(cf_zec12, DTLB1_WRITES, 0x0085);
97CPUMF_EVENT_ATTR(cf_zec12, L1D_LMEM_SOURCED_WRITES, 0x0087);
98CPUMF_EVENT_ATTR(cf_zec12, L1I_LMEM_SOURCED_WRITES, 0x0089);
99CPUMF_EVENT_ATTR(cf_zec12, L1D_RO_EXCL_WRITES, 0x008a);
100CPUMF_EVENT_ATTR(cf_zec12, DTLB1_HPAGE_WRITES, 0x008b);
101CPUMF_EVENT_ATTR(cf_zec12, ITLB1_WRITES, 0x008c);
102CPUMF_EVENT_ATTR(cf_zec12, TLB2_PTE_WRITES, 0x008d);
103CPUMF_EVENT_ATTR(cf_zec12, TLB2_CRSTE_HPAGE_WRITES, 0x008e);
104CPUMF_EVENT_ATTR(cf_zec12, TLB2_CRSTE_WRITES, 0x008f);
105CPUMF_EVENT_ATTR(cf_zec12, L1D_ONCHIP_L3_SOURCED_WRITES, 0x0090);
106CPUMF_EVENT_ATTR(cf_zec12, L1D_OFFCHIP_L3_SOURCED_WRITES, 0x0091);
107CPUMF_EVENT_ATTR(cf_zec12, L1D_OFFBOOK_L3_SOURCED_WRITES, 0x0092);
108CPUMF_EVENT_ATTR(cf_zec12, L1D_ONBOOK_L4_SOURCED_WRITES, 0x0093);
109CPUMF_EVENT_ATTR(cf_zec12, L1D_OFFBOOK_L4_SOURCED_WRITES, 0x0094);
110CPUMF_EVENT_ATTR(cf_zec12, TX_NC_TEND, 0x0095);
111CPUMF_EVENT_ATTR(cf_zec12, L1D_ONCHIP_L3_SOURCED_WRITES_IV, 0x0096);
112CPUMF_EVENT_ATTR(cf_zec12, L1D_OFFCHIP_L3_SOURCED_WRITES_IV, 0x0097);
113CPUMF_EVENT_ATTR(cf_zec12, L1D_OFFBOOK_L3_SOURCED_WRITES_IV, 0x0098);
114CPUMF_EVENT_ATTR(cf_zec12, L1I_ONCHIP_L3_SOURCED_WRITES, 0x0099);
115CPUMF_EVENT_ATTR(cf_zec12, L1I_OFFCHIP_L3_SOURCED_WRITES, 0x009a);
116CPUMF_EVENT_ATTR(cf_zec12, L1I_OFFBOOK_L3_SOURCED_WRITES, 0x009b);
117CPUMF_EVENT_ATTR(cf_zec12, L1I_ONBOOK_L4_SOURCED_WRITES, 0x009c);
118CPUMF_EVENT_ATTR(cf_zec12, L1I_OFFBOOK_L4_SOURCED_WRITES, 0x009d);
119CPUMF_EVENT_ATTR(cf_zec12, TX_C_TEND, 0x009e);
120CPUMF_EVENT_ATTR(cf_zec12, L1I_ONCHIP_L3_SOURCED_WRITES_IV, 0x009f);
121CPUMF_EVENT_ATTR(cf_zec12, L1I_OFFCHIP_L3_SOURCED_WRITES_IV, 0x00a0);
122CPUMF_EVENT_ATTR(cf_zec12, L1I_OFFBOOK_L3_SOURCED_WRITES_IV, 0x00a1);
123CPUMF_EVENT_ATTR(cf_zec12, TX_NC_TABORT, 0x00b1);
124CPUMF_EVENT_ATTR(cf_zec12, TX_C_TABORT_NO_SPECIAL, 0x00b2);
125CPUMF_EVENT_ATTR(cf_zec12, TX_C_TABORT_SPECIAL, 0x00b3);
5f3ba878 126CPUMF_EVENT_ATTR(cf_z13, L1D_RO_EXCL_WRITES, 0x0080);
3fc7aceb
HB		 127CPUMF_EVENT_ATTR(cf_z13, DTLB1_WRITES, 0x0081);
128CPUMF_EVENT_ATTR(cf_z13, DTLB1_MISSES, 0x0082);
129CPUMF_EVENT_ATTR(cf_z13, DTLB1_HPAGE_WRITES, 0x0083);
130CPUMF_EVENT_ATTR(cf_z13, DTLB1_GPAGE_WRITES, 0x0084);
131CPUMF_EVENT_ATTR(cf_z13, L1D_L2D_SOURCED_WRITES, 0x0085);
132CPUMF_EVENT_ATTR(cf_z13, ITLB1_WRITES, 0x0086);
133CPUMF_EVENT_ATTR(cf_z13, ITLB1_MISSES, 0x0087);
134CPUMF_EVENT_ATTR(cf_z13, L1I_L2I_SOURCED_WRITES, 0x0088);
135CPUMF_EVENT_ATTR(cf_z13, TLB2_PTE_WRITES, 0x0089);
136CPUMF_EVENT_ATTR(cf_z13, TLB2_CRSTE_HPAGE_WRITES, 0x008a);
137CPUMF_EVENT_ATTR(cf_z13, TLB2_CRSTE_WRITES, 0x008b);
138CPUMF_EVENT_ATTR(cf_z13, TX_C_TEND, 0x008c);
139CPUMF_EVENT_ATTR(cf_z13, TX_NC_TEND, 0x008d);
140CPUMF_EVENT_ATTR(cf_z13, L1C_TLB1_MISSES, 0x008f);
141CPUMF_EVENT_ATTR(cf_z13, L1D_ONCHIP_L3_SOURCED_WRITES, 0x0090);
142CPUMF_EVENT_ATTR(cf_z13, L1D_ONCHIP_L3_SOURCED_WRITES_IV, 0x0091);
143CPUMF_EVENT_ATTR(cf_z13, L1D_ONNODE_L4_SOURCED_WRITES, 0x0092);
144CPUMF_EVENT_ATTR(cf_z13, L1D_ONNODE_L3_SOURCED_WRITES_IV, 0x0093);
145CPUMF_EVENT_ATTR(cf_z13, L1D_ONNODE_L3_SOURCED_WRITES, 0x0094);
146CPUMF_EVENT_ATTR(cf_z13, L1D_ONDRAWER_L4_SOURCED_WRITES, 0x0095);
147CPUMF_EVENT_ATTR(cf_z13, L1D_ONDRAWER_L3_SOURCED_WRITES_IV, 0x0096);
148CPUMF_EVENT_ATTR(cf_z13, L1D_ONDRAWER_L3_SOURCED_WRITES, 0x0097);
149CPUMF_EVENT_ATTR(cf_z13, L1D_OFFDRAWER_SCOL_L4_SOURCED_WRITES, 0x0098);
150CPUMF_EVENT_ATTR(cf_z13, L1D_OFFDRAWER_SCOL_L3_SOURCED_WRITES_IV, 0x0099);
151CPUMF_EVENT_ATTR(cf_z13, L1D_OFFDRAWER_SCOL_L3_SOURCED_WRITES, 0x009a);
152CPUMF_EVENT_ATTR(cf_z13, L1D_OFFDRAWER_FCOL_L4_SOURCED_WRITES, 0x009b);
153CPUMF_EVENT_ATTR(cf_z13, L1D_OFFDRAWER_FCOL_L3_SOURCED_WRITES_IV, 0x009c);
154CPUMF_EVENT_ATTR(cf_z13, L1D_OFFDRAWER_FCOL_L3_SOURCED_WRITES, 0x009d);
155CPUMF_EVENT_ATTR(cf_z13, L1D_ONNODE_MEM_SOURCED_WRITES, 0x009e);
156CPUMF_EVENT_ATTR(cf_z13, L1D_ONDRAWER_MEM_SOURCED_WRITES, 0x009f);
157CPUMF_EVENT_ATTR(cf_z13, L1D_OFFDRAWER_MEM_SOURCED_WRITES, 0x00a0);
158CPUMF_EVENT_ATTR(cf_z13, L1D_ONCHIP_MEM_SOURCED_WRITES, 0x00a1);
159CPUMF_EVENT_ATTR(cf_z13, L1I_ONCHIP_L3_SOURCED_WRITES, 0x00a2);
160CPUMF_EVENT_ATTR(cf_z13, L1I_ONCHIP_L3_SOURCED_WRITES_IV, 0x00a3);
161CPUMF_EVENT_ATTR(cf_z13, L1I_ONNODE_L4_SOURCED_WRITES, 0x00a4);
162CPUMF_EVENT_ATTR(cf_z13, L1I_ONNODE_L3_SOURCED_WRITES_IV, 0x00a5);
163CPUMF_EVENT_ATTR(cf_z13, L1I_ONNODE_L3_SOURCED_WRITES, 0x00a6);
164CPUMF_EVENT_ATTR(cf_z13, L1I_ONDRAWER_L4_SOURCED_WRITES, 0x00a7);
165CPUMF_EVENT_ATTR(cf_z13, L1I_ONDRAWER_L3_SOURCED_WRITES_IV, 0x00a8);
166CPUMF_EVENT_ATTR(cf_z13, L1I_ONDRAWER_L3_SOURCED_WRITES, 0x00a9);
167CPUMF_EVENT_ATTR(cf_z13, L1I_OFFDRAWER_SCOL_L4_SOURCED_WRITES, 0x00aa);
168CPUMF_EVENT_ATTR(cf_z13, L1I_OFFDRAWER_SCOL_L3_SOURCED_WRITES_IV, 0x00ab);
169CPUMF_EVENT_ATTR(cf_z13, L1I_OFFDRAWER_SCOL_L3_SOURCED_WRITES, 0x00ac);
170CPUMF_EVENT_ATTR(cf_z13, L1I_OFFDRAWER_FCOL_L4_SOURCED_WRITES, 0x00ad);
171CPUMF_EVENT_ATTR(cf_z13, L1I_OFFDRAWER_FCOL_L3_SOURCED_WRITES_IV, 0x00ae);
172CPUMF_EVENT_ATTR(cf_z13, L1I_OFFDRAWER_FCOL_L3_SOURCED_WRITES, 0x00af);
173CPUMF_EVENT_ATTR(cf_z13, L1I_ONNODE_MEM_SOURCED_WRITES, 0x00b0);
174CPUMF_EVENT_ATTR(cf_z13, L1I_ONDRAWER_MEM_SOURCED_WRITES, 0x00b1);
175CPUMF_EVENT_ATTR(cf_z13, L1I_OFFDRAWER_MEM_SOURCED_WRITES, 0x00b2);
176CPUMF_EVENT_ATTR(cf_z13, L1I_ONCHIP_MEM_SOURCED_WRITES, 0x00b3);
177CPUMF_EVENT_ATTR(cf_z13, TX_NC_TABORT, 0x00da);
178CPUMF_EVENT_ATTR(cf_z13, TX_C_TABORT_NO_SPECIAL, 0x00db);
179CPUMF_EVENT_ATTR(cf_z13, TX_C_TABORT_SPECIAL, 0x00dc);
180CPUMF_EVENT_ATTR(cf_z13, MT_DIAG_CYCLES_ONE_THR_ACTIVE, 0x01c0);
181CPUMF_EVENT_ATTR(cf_z13, MT_DIAG_CYCLES_TWO_THR_ACTIVE, 0x01c1);
5f3ba878 182CPUMF_EVENT_ATTR(cf_z14, L1D_RO_EXCL_WRITES, 0x0080);
3593eb94
HB		 183CPUMF_EVENT_ATTR(cf_z14, DTLB2_WRITES, 0x0081);
184CPUMF_EVENT_ATTR(cf_z14, DTLB2_MISSES, 0x0082);
185CPUMF_EVENT_ATTR(cf_z14, DTLB2_HPAGE_WRITES, 0x0083);
186CPUMF_EVENT_ATTR(cf_z14, DTLB2_GPAGE_WRITES, 0x0084);
187CPUMF_EVENT_ATTR(cf_z14, L1D_L2D_SOURCED_WRITES, 0x0085);
188CPUMF_EVENT_ATTR(cf_z14, ITLB2_WRITES, 0x0086);
189CPUMF_EVENT_ATTR(cf_z14, ITLB2_MISSES, 0x0087);
190CPUMF_EVENT_ATTR(cf_z14, L1I_L2I_SOURCED_WRITES, 0x0088);
191CPUMF_EVENT_ATTR(cf_z14, TLB2_PTE_WRITES, 0x0089);
192CPUMF_EVENT_ATTR(cf_z14, TLB2_CRSTE_WRITES, 0x008a);
193CPUMF_EVENT_ATTR(cf_z14, TLB2_ENGINES_BUSY, 0x008b);
194CPUMF_EVENT_ATTR(cf_z14, TX_C_TEND, 0x008c);
195CPUMF_EVENT_ATTR(cf_z14, TX_NC_TEND, 0x008d);
196CPUMF_EVENT_ATTR(cf_z14, L1C_TLB2_MISSES, 0x008f);
197CPUMF_EVENT_ATTR(cf_z14, L1D_ONCHIP_L3_SOURCED_WRITES, 0x0090);
198CPUMF_EVENT_ATTR(cf_z14, L1D_ONCHIP_MEMORY_SOURCED_WRITES, 0x0091);
199CPUMF_EVENT_ATTR(cf_z14, L1D_ONCHIP_L3_SOURCED_WRITES_IV, 0x0092);
200CPUMF_EVENT_ATTR(cf_z14, L1D_ONCLUSTER_L3_SOURCED_WRITES, 0x0093);
201CPUMF_EVENT_ATTR(cf_z14, L1D_ONCLUSTER_MEMORY_SOURCED_WRITES, 0x0094);
202CPUMF_EVENT_ATTR(cf_z14, L1D_ONCLUSTER_L3_SOURCED_WRITES_IV, 0x0095);
203CPUMF_EVENT_ATTR(cf_z14, L1D_OFFCLUSTER_L3_SOURCED_WRITES, 0x0096);
204CPUMF_EVENT_ATTR(cf_z14, L1D_OFFCLUSTER_MEMORY_SOURCED_WRITES, 0x0097);
205CPUMF_EVENT_ATTR(cf_z14, L1D_OFFCLUSTER_L3_SOURCED_WRITES_IV, 0x0098);
206CPUMF_EVENT_ATTR(cf_z14, L1D_OFFDRAWER_L3_SOURCED_WRITES, 0x0099);
207CPUMF_EVENT_ATTR(cf_z14, L1D_OFFDRAWER_MEMORY_SOURCED_WRITES, 0x009a);
208CPUMF_EVENT_ATTR(cf_z14, L1D_OFFDRAWER_L3_SOURCED_WRITES_IV, 0x009b);
209CPUMF_EVENT_ATTR(cf_z14, L1D_ONDRAWER_L4_SOURCED_WRITES, 0x009c);
210CPUMF_EVENT_ATTR(cf_z14, L1D_OFFDRAWER_L4_SOURCED_WRITES, 0x009d);
211CPUMF_EVENT_ATTR(cf_z14, L1D_ONCHIP_L3_SOURCED_WRITES_RO, 0x009e);
212CPUMF_EVENT_ATTR(cf_z14, L1I_ONCHIP_L3_SOURCED_WRITES, 0x00a2);
213CPUMF_EVENT_ATTR(cf_z14, L1I_ONCHIP_MEMORY_SOURCED_WRITES, 0x00a3);
214CPUMF_EVENT_ATTR(cf_z14, L1I_ONCHIP_L3_SOURCED_WRITES_IV, 0x00a4);
215CPUMF_EVENT_ATTR(cf_z14, L1I_ONCLUSTER_L3_SOURCED_WRITES, 0x00a5);
216CPUMF_EVENT_ATTR(cf_z14, L1I_ONCLUSTER_MEMORY_SOURCED_WRITES, 0x00a6);
217CPUMF_EVENT_ATTR(cf_z14, L1I_ONCLUSTER_L3_SOURCED_WRITES_IV, 0x00a7);
218CPUMF_EVENT_ATTR(cf_z14, L1I_OFFCLUSTER_L3_SOURCED_WRITES, 0x00a8);
219CPUMF_EVENT_ATTR(cf_z14, L1I_OFFCLUSTER_MEMORY_SOURCED_WRITES, 0x00a9);
220CPUMF_EVENT_ATTR(cf_z14, L1I_OFFCLUSTER_L3_SOURCED_WRITES_IV, 0x00aa);
221CPUMF_EVENT_ATTR(cf_z14, L1I_OFFDRAWER_L3_SOURCED_WRITES, 0x00ab);
222CPUMF_EVENT_ATTR(cf_z14, L1I_OFFDRAWER_MEMORY_SOURCED_WRITES, 0x00ac);
223CPUMF_EVENT_ATTR(cf_z14, L1I_OFFDRAWER_L3_SOURCED_WRITES_IV, 0x00ad);
224CPUMF_EVENT_ATTR(cf_z14, L1I_ONDRAWER_L4_SOURCED_WRITES, 0x00ae);
225CPUMF_EVENT_ATTR(cf_z14, L1I_OFFDRAWER_L4_SOURCED_WRITES, 0x00af);
226CPUMF_EVENT_ATTR(cf_z14, BCD_DFP_EXECUTION_SLOTS, 0x00e0);
227CPUMF_EVENT_ATTR(cf_z14, VX_BCD_EXECUTION_SLOTS, 0x00e1);
228CPUMF_EVENT_ATTR(cf_z14, DECIMAL_INSTRUCTIONS, 0x00e2);
81507f38 229CPUMF_EVENT_ATTR(cf_z14, LAST_HOST_TRANSLATIONS, 0x00e8);
3593eb94
HB		 230CPUMF_EVENT_ATTR(cf_z14, TX_NC_TABORT, 0x00f3);
231CPUMF_EVENT_ATTR(cf_z14, TX_C_TABORT_NO_SPECIAL, 0x00f4);
232CPUMF_EVENT_ATTR(cf_z14, TX_C_TABORT_SPECIAL, 0x00f5);
233CPUMF_EVENT_ATTR(cf_z14, MT_DIAG_CYCLES_ONE_THR_ACTIVE, 0x01c0);
234CPUMF_EVENT_ATTR(cf_z14, MT_DIAG_CYCLES_TWO_THR_ACTIVE, 0x01c1);
c7168325 235
3593eb94
HB		 236static struct attribute *cpumcf_fvn1_pmu_event_attr[] __initdata = {
237 CPUMF_EVENT_PTR(cf_fvn1, CPU_CYCLES),
238 CPUMF_EVENT_PTR(cf_fvn1, INSTRUCTIONS),
239 CPUMF_EVENT_PTR(cf_fvn1, L1I_DIR_WRITES),
240 CPUMF_EVENT_PTR(cf_fvn1, L1I_PENALTY_CYCLES),
241 CPUMF_EVENT_PTR(cf_fvn1, PROBLEM_STATE_CPU_CYCLES),
242 CPUMF_EVENT_PTR(cf_fvn1, PROBLEM_STATE_INSTRUCTIONS),
243 CPUMF_EVENT_PTR(cf_fvn1, PROBLEM_STATE_L1I_DIR_WRITES),
244 CPUMF_EVENT_PTR(cf_fvn1, PROBLEM_STATE_L1I_PENALTY_CYCLES),
245 CPUMF_EVENT_PTR(cf_fvn1, PROBLEM_STATE_L1D_DIR_WRITES),
246 CPUMF_EVENT_PTR(cf_fvn1, PROBLEM_STATE_L1D_PENALTY_CYCLES),
247 CPUMF_EVENT_PTR(cf_fvn1, L1D_DIR_WRITES),
248 CPUMF_EVENT_PTR(cf_fvn1, L1D_PENALTY_CYCLES),
249 NULL,
250};
251
252static struct attribute *cpumcf_fvn3_pmu_event_attr[] __initdata = {
253 CPUMF_EVENT_PTR(cf_fvn3, CPU_CYCLES),
254 CPUMF_EVENT_PTR(cf_fvn3, INSTRUCTIONS),
255 CPUMF_EVENT_PTR(cf_fvn3, L1I_DIR_WRITES),
256 CPUMF_EVENT_PTR(cf_fvn3, L1I_PENALTY_CYCLES),
257 CPUMF_EVENT_PTR(cf_fvn3, PROBLEM_STATE_CPU_CYCLES),
258 CPUMF_EVENT_PTR(cf_fvn3, PROBLEM_STATE_INSTRUCTIONS),
259 CPUMF_EVENT_PTR(cf_fvn3, L1D_DIR_WRITES),
260 CPUMF_EVENT_PTR(cf_fvn3, L1D_PENALTY_CYCLES),
261 NULL,
262};
263
264static struct attribute *cpumcf_svn_generic_pmu_event_attr[] __initdata = {
265 CPUMF_EVENT_PTR(cf_svn_generic, PRNG_FUNCTIONS),
266 CPUMF_EVENT_PTR(cf_svn_generic, PRNG_CYCLES),
267 CPUMF_EVENT_PTR(cf_svn_generic, PRNG_BLOCKED_FUNCTIONS),
268 CPUMF_EVENT_PTR(cf_svn_generic, PRNG_BLOCKED_CYCLES),
269 CPUMF_EVENT_PTR(cf_svn_generic, SHA_FUNCTIONS),
270 CPUMF_EVENT_PTR(cf_svn_generic, SHA_CYCLES),
271 CPUMF_EVENT_PTR(cf_svn_generic, SHA_BLOCKED_FUNCTIONS),
272 CPUMF_EVENT_PTR(cf_svn_generic, SHA_BLOCKED_CYCLES),
273 CPUMF_EVENT_PTR(cf_svn_generic, DEA_FUNCTIONS),
274 CPUMF_EVENT_PTR(cf_svn_generic, DEA_CYCLES),
275 CPUMF_EVENT_PTR(cf_svn_generic, DEA_BLOCKED_FUNCTIONS),
276 CPUMF_EVENT_PTR(cf_svn_generic, DEA_BLOCKED_CYCLES),
277 CPUMF_EVENT_PTR(cf_svn_generic, AES_FUNCTIONS),
278 CPUMF_EVENT_PTR(cf_svn_generic, AES_CYCLES),
279 CPUMF_EVENT_PTR(cf_svn_generic, AES_BLOCKED_FUNCTIONS),
280 CPUMF_EVENT_PTR(cf_svn_generic, AES_BLOCKED_CYCLES),
c7168325
HB		 281 NULL,
282};
283
284static struct attribute *cpumcf_z10_pmu_event_attr[] __initdata = {
285 CPUMF_EVENT_PTR(cf_z10, L1I_L2_SOURCED_WRITES),
286 CPUMF_EVENT_PTR(cf_z10, L1D_L2_SOURCED_WRITES),
287 CPUMF_EVENT_PTR(cf_z10, L1I_L3_LOCAL_WRITES),
288 CPUMF_EVENT_PTR(cf_z10, L1D_L3_LOCAL_WRITES),
289 CPUMF_EVENT_PTR(cf_z10, L1I_L3_REMOTE_WRITES),
290 CPUMF_EVENT_PTR(cf_z10, L1D_L3_REMOTE_WRITES),
291 CPUMF_EVENT_PTR(cf_z10, L1D_LMEM_SOURCED_WRITES),
292 CPUMF_EVENT_PTR(cf_z10, L1I_LMEM_SOURCED_WRITES),
293 CPUMF_EVENT_PTR(cf_z10, L1D_RO_EXCL_WRITES),
294 CPUMF_EVENT_PTR(cf_z10, L1I_CACHELINE_INVALIDATES),
295 CPUMF_EVENT_PTR(cf_z10, ITLB1_WRITES),
296 CPUMF_EVENT_PTR(cf_z10, DTLB1_WRITES),
297 CPUMF_EVENT_PTR(cf_z10, TLB2_PTE_WRITES),
298 CPUMF_EVENT_PTR(cf_z10, TLB2_CRSTE_WRITES),
299 CPUMF_EVENT_PTR(cf_z10, TLB2_CRSTE_HPAGE_WRITES),
300 CPUMF_EVENT_PTR(cf_z10, ITLB1_MISSES),
301 CPUMF_EVENT_PTR(cf_z10, DTLB1_MISSES),
302 CPUMF_EVENT_PTR(cf_z10, L2C_STORES_SENT),
303 NULL,
304};
305
306static struct attribute *cpumcf_z196_pmu_event_attr[] __initdata = {
307 CPUMF_EVENT_PTR(cf_z196, L1D_L2_SOURCED_WRITES),
308 CPUMF_EVENT_PTR(cf_z196, L1I_L2_SOURCED_WRITES),
309 CPUMF_EVENT_PTR(cf_z196, DTLB1_MISSES),
310 CPUMF_EVENT_PTR(cf_z196, ITLB1_MISSES),
311 CPUMF_EVENT_PTR(cf_z196, L2C_STORES_SENT),
312 CPUMF_EVENT_PTR(cf_z196, L1D_OFFBOOK_L3_SOURCED_WRITES),
313 CPUMF_EVENT_PTR(cf_z196, L1D_ONBOOK_L4_SOURCED_WRITES),
314 CPUMF_EVENT_PTR(cf_z196, L1I_ONBOOK_L4_SOURCED_WRITES),
315 CPUMF_EVENT_PTR(cf_z196, L1D_RO_EXCL_WRITES),
316 CPUMF_EVENT_PTR(cf_z196, L1D_OFFBOOK_L4_SOURCED_WRITES),
317 CPUMF_EVENT_PTR(cf_z196, L1I_OFFBOOK_L4_SOURCED_WRITES),
318 CPUMF_EVENT_PTR(cf_z196, DTLB1_HPAGE_WRITES),
319 CPUMF_EVENT_PTR(cf_z196, L1D_LMEM_SOURCED_WRITES),
320 CPUMF_EVENT_PTR(cf_z196, L1I_LMEM_SOURCED_WRITES),
321 CPUMF_EVENT_PTR(cf_z196, L1I_OFFBOOK_L3_SOURCED_WRITES),
322 CPUMF_EVENT_PTR(cf_z196, DTLB1_WRITES),
323 CPUMF_EVENT_PTR(cf_z196, ITLB1_WRITES),
324 CPUMF_EVENT_PTR(cf_z196, TLB2_PTE_WRITES),
325 CPUMF_EVENT_PTR(cf_z196, TLB2_CRSTE_HPAGE_WRITES),
326 CPUMF_EVENT_PTR(cf_z196, TLB2_CRSTE_WRITES),
327 CPUMF_EVENT_PTR(cf_z196, L1D_ONCHIP_L3_SOURCED_WRITES),
328 CPUMF_EVENT_PTR(cf_z196, L1D_OFFCHIP_L3_SOURCED_WRITES),
329 CPUMF_EVENT_PTR(cf_z196, L1I_ONCHIP_L3_SOURCED_WRITES),
330 CPUMF_EVENT_PTR(cf_z196, L1I_OFFCHIP_L3_SOURCED_WRITES),
331 NULL,
332};
333
334static struct attribute *cpumcf_zec12_pmu_event_attr[] __initdata = {
335 CPUMF_EVENT_PTR(cf_zec12, DTLB1_MISSES),
336 CPUMF_EVENT_PTR(cf_zec12, ITLB1_MISSES),
337 CPUMF_EVENT_PTR(cf_zec12, L1D_L2I_SOURCED_WRITES),
338 CPUMF_EVENT_PTR(cf_zec12, L1I_L2I_SOURCED_WRITES),
339 CPUMF_EVENT_PTR(cf_zec12, L1D_L2D_SOURCED_WRITES),
340 CPUMF_EVENT_PTR(cf_zec12, DTLB1_WRITES),
341 CPUMF_EVENT_PTR(cf_zec12, L1D_LMEM_SOURCED_WRITES),
342 CPUMF_EVENT_PTR(cf_zec12, L1I_LMEM_SOURCED_WRITES),
343 CPUMF_EVENT_PTR(cf_zec12, L1D_RO_EXCL_WRITES),
344 CPUMF_EVENT_PTR(cf_zec12, DTLB1_HPAGE_WRITES),
345 CPUMF_EVENT_PTR(cf_zec12, ITLB1_WRITES),
346 CPUMF_EVENT_PTR(cf_zec12, TLB2_PTE_WRITES),
347 CPUMF_EVENT_PTR(cf_zec12, TLB2_CRSTE_HPAGE_WRITES),
348 CPUMF_EVENT_PTR(cf_zec12, TLB2_CRSTE_WRITES),
349 CPUMF_EVENT_PTR(cf_zec12, L1D_ONCHIP_L3_SOURCED_WRITES),
350 CPUMF_EVENT_PTR(cf_zec12, L1D_OFFCHIP_L3_SOURCED_WRITES),
351 CPUMF_EVENT_PTR(cf_zec12, L1D_OFFBOOK_L3_SOURCED_WRITES),
352 CPUMF_EVENT_PTR(cf_zec12, L1D_ONBOOK_L4_SOURCED_WRITES),
353 CPUMF_EVENT_PTR(cf_zec12, L1D_OFFBOOK_L4_SOURCED_WRITES),
354 CPUMF_EVENT_PTR(cf_zec12, TX_NC_TEND),
355 CPUMF_EVENT_PTR(cf_zec12, L1D_ONCHIP_L3_SOURCED_WRITES_IV),
356 CPUMF_EVENT_PTR(cf_zec12, L1D_OFFCHIP_L3_SOURCED_WRITES_IV),
357 CPUMF_EVENT_PTR(cf_zec12, L1D_OFFBOOK_L3_SOURCED_WRITES_IV),
358 CPUMF_EVENT_PTR(cf_zec12, L1I_ONCHIP_L3_SOURCED_WRITES),
359 CPUMF_EVENT_PTR(cf_zec12, L1I_OFFCHIP_L3_SOURCED_WRITES),
360 CPUMF_EVENT_PTR(cf_zec12, L1I_OFFBOOK_L3_SOURCED_WRITES),
361 CPUMF_EVENT_PTR(cf_zec12, L1I_ONBOOK_L4_SOURCED_WRITES),
362 CPUMF_EVENT_PTR(cf_zec12, L1I_OFFBOOK_L4_SOURCED_WRITES),
363 CPUMF_EVENT_PTR(cf_zec12, TX_C_TEND),
364 CPUMF_EVENT_PTR(cf_zec12, L1I_ONCHIP_L3_SOURCED_WRITES_IV),
365 CPUMF_EVENT_PTR(cf_zec12, L1I_OFFCHIP_L3_SOURCED_WRITES_IV),
366 CPUMF_EVENT_PTR(cf_zec12, L1I_OFFBOOK_L3_SOURCED_WRITES_IV),
367 CPUMF_EVENT_PTR(cf_zec12, TX_NC_TABORT),
368 CPUMF_EVENT_PTR(cf_zec12, TX_C_TABORT_NO_SPECIAL),
369 CPUMF_EVENT_PTR(cf_zec12, TX_C_TABORT_SPECIAL),
370 NULL,
371};
372
3fc7aceb 373static struct attribute *cpumcf_z13_pmu_event_attr[] __initdata = {
5f3ba878 374 CPUMF_EVENT_PTR(cf_z13, L1D_RO_EXCL_WRITES),
3fc7aceb
HB		 375 CPUMF_EVENT_PTR(cf_z13, DTLB1_WRITES),
376 CPUMF_EVENT_PTR(cf_z13, DTLB1_MISSES),
377 CPUMF_EVENT_PTR(cf_z13, DTLB1_HPAGE_WRITES),
378 CPUMF_EVENT_PTR(cf_z13, DTLB1_GPAGE_WRITES),
379 CPUMF_EVENT_PTR(cf_z13, L1D_L2D_SOURCED_WRITES),
380 CPUMF_EVENT_PTR(cf_z13, ITLB1_WRITES),
381 CPUMF_EVENT_PTR(cf_z13, ITLB1_MISSES),
382 CPUMF_EVENT_PTR(cf_z13, L1I_L2I_SOURCED_WRITES),
383 CPUMF_EVENT_PTR(cf_z13, TLB2_PTE_WRITES),
384 CPUMF_EVENT_PTR(cf_z13, TLB2_CRSTE_HPAGE_WRITES),
385 CPUMF_EVENT_PTR(cf_z13, TLB2_CRSTE_WRITES),
386 CPUMF_EVENT_PTR(cf_z13, TX_C_TEND),
387 CPUMF_EVENT_PTR(cf_z13, TX_NC_TEND),
388 CPUMF_EVENT_PTR(cf_z13, L1C_TLB1_MISSES),
389 CPUMF_EVENT_PTR(cf_z13, L1D_ONCHIP_L3_SOURCED_WRITES),
390 CPUMF_EVENT_PTR(cf_z13, L1D_ONCHIP_L3_SOURCED_WRITES_IV),
391 CPUMF_EVENT_PTR(cf_z13, L1D_ONNODE_L4_SOURCED_WRITES),
392 CPUMF_EVENT_PTR(cf_z13, L1D_ONNODE_L3_SOURCED_WRITES_IV),
393 CPUMF_EVENT_PTR(cf_z13, L1D_ONNODE_L3_SOURCED_WRITES),
394 CPUMF_EVENT_PTR(cf_z13, L1D_ONDRAWER_L4_SOURCED_WRITES),
395 CPUMF_EVENT_PTR(cf_z13, L1D_ONDRAWER_L3_SOURCED_WRITES_IV),
396 CPUMF_EVENT_PTR(cf_z13, L1D_ONDRAWER_L3_SOURCED_WRITES),
397 CPUMF_EVENT_PTR(cf_z13, L1D_OFFDRAWER_SCOL_L4_SOURCED_WRITES),
398 CPUMF_EVENT_PTR(cf_z13, L1D_OFFDRAWER_SCOL_L3_SOURCED_WRITES_IV),
399 CPUMF_EVENT_PTR(cf_z13, L1D_OFFDRAWER_SCOL_L3_SOURCED_WRITES),
400 CPUMF_EVENT_PTR(cf_z13, L1D_OFFDRAWER_FCOL_L4_SOURCED_WRITES),
401 CPUMF_EVENT_PTR(cf_z13, L1D_OFFDRAWER_FCOL_L3_SOURCED_WRITES_IV),
402 CPUMF_EVENT_PTR(cf_z13, L1D_OFFDRAWER_FCOL_L3_SOURCED_WRITES),
403 CPUMF_EVENT_PTR(cf_z13, L1D_ONNODE_MEM_SOURCED_WRITES),
404 CPUMF_EVENT_PTR(cf_z13, L1D_ONDRAWER_MEM_SOURCED_WRITES),
405 CPUMF_EVENT_PTR(cf_z13, L1D_OFFDRAWER_MEM_SOURCED_WRITES),
406 CPUMF_EVENT_PTR(cf_z13, L1D_ONCHIP_MEM_SOURCED_WRITES),
407 CPUMF_EVENT_PTR(cf_z13, L1I_ONCHIP_L3_SOURCED_WRITES),
408 CPUMF_EVENT_PTR(cf_z13, L1I_ONCHIP_L3_SOURCED_WRITES_IV),
409 CPUMF_EVENT_PTR(cf_z13, L1I_ONNODE_L4_SOURCED_WRITES),
410 CPUMF_EVENT_PTR(cf_z13, L1I_ONNODE_L3_SOURCED_WRITES_IV),
411 CPUMF_EVENT_PTR(cf_z13, L1I_ONNODE_L3_SOURCED_WRITES),
412 CPUMF_EVENT_PTR(cf_z13, L1I_ONDRAWER_L4_SOURCED_WRITES),
413 CPUMF_EVENT_PTR(cf_z13, L1I_ONDRAWER_L3_SOURCED_WRITES_IV),
414 CPUMF_EVENT_PTR(cf_z13, L1I_ONDRAWER_L3_SOURCED_WRITES),
415 CPUMF_EVENT_PTR(cf_z13, L1I_OFFDRAWER_SCOL_L4_SOURCED_WRITES),
416 CPUMF_EVENT_PTR(cf_z13, L1I_OFFDRAWER_SCOL_L3_SOURCED_WRITES_IV),
417 CPUMF_EVENT_PTR(cf_z13, L1I_OFFDRAWER_SCOL_L3_SOURCED_WRITES),
418 CPUMF_EVENT_PTR(cf_z13, L1I_OFFDRAWER_FCOL_L4_SOURCED_WRITES),
419 CPUMF_EVENT_PTR(cf_z13, L1I_OFFDRAWER_FCOL_L3_SOURCED_WRITES_IV),
420 CPUMF_EVENT_PTR(cf_z13, L1I_OFFDRAWER_FCOL_L3_SOURCED_WRITES),
421 CPUMF_EVENT_PTR(cf_z13, L1I_ONNODE_MEM_SOURCED_WRITES),
422 CPUMF_EVENT_PTR(cf_z13, L1I_ONDRAWER_MEM_SOURCED_WRITES),
423 CPUMF_EVENT_PTR(cf_z13, L1I_OFFDRAWER_MEM_SOURCED_WRITES),
424 CPUMF_EVENT_PTR(cf_z13, L1I_ONCHIP_MEM_SOURCED_WRITES),
425 CPUMF_EVENT_PTR(cf_z13, TX_NC_TABORT),
426 CPUMF_EVENT_PTR(cf_z13, TX_C_TABORT_NO_SPECIAL),
427 CPUMF_EVENT_PTR(cf_z13, TX_C_TABORT_SPECIAL),
428 CPUMF_EVENT_PTR(cf_z13, MT_DIAG_CYCLES_ONE_THR_ACTIVE),
429 CPUMF_EVENT_PTR(cf_z13, MT_DIAG_CYCLES_TWO_THR_ACTIVE),
430 NULL,
431};
432
3593eb94 433static struct attribute *cpumcf_z14_pmu_event_attr[] __initdata = {
5f3ba878 434 CPUMF_EVENT_PTR(cf_z14, L1D_RO_EXCL_WRITES),
3593eb94
HB		 435 CPUMF_EVENT_PTR(cf_z14, DTLB2_WRITES),
436 CPUMF_EVENT_PTR(cf_z14, DTLB2_MISSES),
437 CPUMF_EVENT_PTR(cf_z14, DTLB2_HPAGE_WRITES),
438 CPUMF_EVENT_PTR(cf_z14, DTLB2_GPAGE_WRITES),
439 CPUMF_EVENT_PTR(cf_z14, L1D_L2D_SOURCED_WRITES),
440 CPUMF_EVENT_PTR(cf_z14, ITLB2_WRITES),
441 CPUMF_EVENT_PTR(cf_z14, ITLB2_MISSES),
442 CPUMF_EVENT_PTR(cf_z14, L1I_L2I_SOURCED_WRITES),
443 CPUMF_EVENT_PTR(cf_z14, TLB2_PTE_WRITES),
444 CPUMF_EVENT_PTR(cf_z14, TLB2_CRSTE_WRITES),
445 CPUMF_EVENT_PTR(cf_z14, TLB2_ENGINES_BUSY),
446 CPUMF_EVENT_PTR(cf_z14, TX_C_TEND),
447 CPUMF_EVENT_PTR(cf_z14, TX_NC_TEND),
448 CPUMF_EVENT_PTR(cf_z14, L1C_TLB2_MISSES),
449 CPUMF_EVENT_PTR(cf_z14, L1D_ONCHIP_L3_SOURCED_WRITES),
450 CPUMF_EVENT_PTR(cf_z14, L1D_ONCHIP_MEMORY_SOURCED_WRITES),
451 CPUMF_EVENT_PTR(cf_z14, L1D_ONCHIP_L3_SOURCED_WRITES_IV),
452 CPUMF_EVENT_PTR(cf_z14, L1D_ONCLUSTER_L3_SOURCED_WRITES),
453 CPUMF_EVENT_PTR(cf_z14, L1D_ONCLUSTER_MEMORY_SOURCED_WRITES),
454 CPUMF_EVENT_PTR(cf_z14, L1D_ONCLUSTER_L3_SOURCED_WRITES_IV),
455 CPUMF_EVENT_PTR(cf_z14, L1D_OFFCLUSTER_L3_SOURCED_WRITES),
456 CPUMF_EVENT_PTR(cf_z14, L1D_OFFCLUSTER_MEMORY_SOURCED_WRITES),
457 CPUMF_EVENT_PTR(cf_z14, L1D_OFFCLUSTER_L3_SOURCED_WRITES_IV),
458 CPUMF_EVENT_PTR(cf_z14, L1D_OFFDRAWER_L3_SOURCED_WRITES),
459 CPUMF_EVENT_PTR(cf_z14, L1D_OFFDRAWER_MEMORY_SOURCED_WRITES),
460 CPUMF_EVENT_PTR(cf_z14, L1D_OFFDRAWER_L3_SOURCED_WRITES_IV),
461 CPUMF_EVENT_PTR(cf_z14, L1D_ONDRAWER_L4_SOURCED_WRITES),
462 CPUMF_EVENT_PTR(cf_z14, L1D_OFFDRAWER_L4_SOURCED_WRITES),
463 CPUMF_EVENT_PTR(cf_z14, L1D_ONCHIP_L3_SOURCED_WRITES_RO),
464 CPUMF_EVENT_PTR(cf_z14, L1I_ONCHIP_L3_SOURCED_WRITES),
465 CPUMF_EVENT_PTR(cf_z14, L1I_ONCHIP_MEMORY_SOURCED_WRITES),
466 CPUMF_EVENT_PTR(cf_z14, L1I_ONCHIP_L3_SOURCED_WRITES_IV),
467 CPUMF_EVENT_PTR(cf_z14, L1I_ONCLUSTER_L3_SOURCED_WRITES),
468 CPUMF_EVENT_PTR(cf_z14, L1I_ONCLUSTER_MEMORY_SOURCED_WRITES),
469 CPUMF_EVENT_PTR(cf_z14, L1I_ONCLUSTER_L3_SOURCED_WRITES_IV),
470 CPUMF_EVENT_PTR(cf_z14, L1I_OFFCLUSTER_L3_SOURCED_WRITES),
471 CPUMF_EVENT_PTR(cf_z14, L1I_OFFCLUSTER_MEMORY_SOURCED_WRITES),
472 CPUMF_EVENT_PTR(cf_z14, L1I_OFFCLUSTER_L3_SOURCED_WRITES_IV),
473 CPUMF_EVENT_PTR(cf_z14, L1I_OFFDRAWER_L3_SOURCED_WRITES),
474 CPUMF_EVENT_PTR(cf_z14, L1I_OFFDRAWER_MEMORY_SOURCED_WRITES),
475 CPUMF_EVENT_PTR(cf_z14, L1I_OFFDRAWER_L3_SOURCED_WRITES_IV),
476 CPUMF_EVENT_PTR(cf_z14, L1I_ONDRAWER_L4_SOURCED_WRITES),
477 CPUMF_EVENT_PTR(cf_z14, L1I_OFFDRAWER_L4_SOURCED_WRITES),
478 CPUMF_EVENT_PTR(cf_z14, BCD_DFP_EXECUTION_SLOTS),
479 CPUMF_EVENT_PTR(cf_z14, VX_BCD_EXECUTION_SLOTS),
480 CPUMF_EVENT_PTR(cf_z14, DECIMAL_INSTRUCTIONS),
481 CPUMF_EVENT_PTR(cf_z14, LAST_HOST_TRANSLATIONS),
482 CPUMF_EVENT_PTR(cf_z14, TX_NC_TABORT),
483 CPUMF_EVENT_PTR(cf_z14, TX_C_TABORT_NO_SPECIAL),
484 CPUMF_EVENT_PTR(cf_z14, TX_C_TABORT_SPECIAL),
485 CPUMF_EVENT_PTR(cf_z14, MT_DIAG_CYCLES_ONE_THR_ACTIVE),
486 CPUMF_EVENT_PTR(cf_z14, MT_DIAG_CYCLES_TWO_THR_ACTIVE),
487 NULL,
488};
489
c7168325
HB		 490/* END: CPUM_CF COUNTER DEFINITIONS ===================================== */
491
66a49784 492static struct attribute_group cpumcf_pmu_events_group = {
c7168325 493 .name = "events",
c7168325
HB		 494};
495
496PMU_FORMAT_ATTR(event, "config:0-63");
497
66a49784 498static struct attribute *cpumcf_pmu_format_attr[] = {
c7168325
HB		 499 &format_attr_event.attr,
500 NULL,
501};
502
66a49784 503static struct attribute_group cpumcf_pmu_format_group = {
c7168325 504 .name = "format",
66a49784 505 .attrs = cpumcf_pmu_format_attr,
c7168325
HB		 506};
507
66a49784
HB		 508static const struct attribute_group *cpumcf_pmu_attr_groups[] = {
509 &cpumcf_pmu_events_group,
510 &cpumcf_pmu_format_group,
c7168325
HB		 511 NULL,
512};
513
514
515static __init struct attribute **merge_attr(struct attribute **a,
3593eb94
HB		 516 struct attribute **b,
517 struct attribute **c)
c7168325
HB		 518{
519 struct attribute **new;
520 int j, i;
521
522 for (j = 0; a[j]; j++)
523 ;
524 for (i = 0; b[i]; i++)
525 j++;
3593eb94
HB		 526 for (i = 0; c[i]; i++)
527 j++;
c7168325
HB		 528 j++;
529
530 new = kmalloc(sizeof(struct attribute *) * j, GFP_KERNEL);
531 if (!new)
532 return NULL;
533 j = 0;
534 for (i = 0; a[i]; i++)
535 new[j++] = a[i];
536 for (i = 0; b[i]; i++)
537 new[j++] = b[i];
3593eb94
HB		 538 for (i = 0; c[i]; i++)
539 new[j++] = c[i];
c7168325
HB		 540 new[j] = NULL;
541
542 return new;
543}
544
545__init const struct attribute_group **cpumf_cf_event_group(void)
546{
3593eb94 547 struct attribute **combined, **model, **cfvn, **csvn;
3fc7aceb 548 struct attribute *none[] = { NULL };
3593eb94 549 struct cpumf_ctr_info ci;
c7168325
HB		 550 struct cpuid cpu_id;
551
3593eb94
HB		 552 /* Determine generic counters set(s) */
553 qctri(&ci);
554 switch (ci.cfvn) {
555 case 1:
556 cfvn = cpumcf_fvn1_pmu_event_attr;
557 break;
558 case 3:
559 cfvn = cpumcf_fvn3_pmu_event_attr;
560 break;
561 default:
562 cfvn = none;
563 }
564 csvn = cpumcf_svn_generic_pmu_event_attr;
565
566 /* Determine model-specific counter set(s) */
c7168325
HB		 567 get_cpu_id(&cpu_id);
568 switch (cpu_id.machine) {
569 case 0x2097:
570 case 0x2098:
571 model = cpumcf_z10_pmu_event_attr;
572 break;
573 case 0x2817:
574 case 0x2818:
575 model = cpumcf_z196_pmu_event_attr;
576 break;
577 case 0x2827:
578 case 0x2828:
579 model = cpumcf_zec12_pmu_event_attr;
580 break;
3fc7aceb
HB		 581 case 0x2964:
582 case 0x2965:
583 model = cpumcf_z13_pmu_event_attr;
584 break;
3593eb94 585 case 0x3906:
451239eb 586 case 0x3907:
3593eb94
HB		 587 model = cpumcf_z14_pmu_event_attr;
588 break;
c7168325 589 default:
3fc7aceb 590 model = none;
c7168325 591 break;
0b925159 592 }
c7168325 593
3593eb94 594 combined = merge_attr(cfvn, csvn, model);
c7168325 595 if (combined)
66a49784
HB		 596 cpumcf_pmu_events_group.attrs = combined;
597 return cpumcf_pmu_attr_groups;
c7168325 598}
Linux 6.x block layer and io_uring tree(s)