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212188a5 HB |
1 | /* |
2 | * Performance event support for s390x - CPU-measurement Counter Facility | |
3 | * | |
4 | * Copyright IBM Corp. 2012 | |
5 | * Author(s): Hendrik Brueckner <brueckner@linux.vnet.ibm.com> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License (version 2 only) | |
9 | * as published by the Free Software Foundation. | |
10 | */ | |
11 | #define KMSG_COMPONENT "cpum_cf" | |
12 | #define pr_fmt(fmt) KMSG_COMPONENT ": " fmt | |
13 | ||
14 | #include <linux/kernel.h> | |
15 | #include <linux/kernel_stat.h> | |
16 | #include <linux/perf_event.h> | |
17 | #include <linux/percpu.h> | |
18 | #include <linux/notifier.h> | |
19 | #include <linux/init.h> | |
20 | #include <linux/export.h> | |
1e3cab2f | 21 | #include <asm/ctl_reg.h> |
212188a5 HB |
22 | #include <asm/irq.h> |
23 | #include <asm/cpu_mf.h> | |
24 | ||
25 | /* CPU-measurement counter facility supports these CPU counter sets: | |
26 | * For CPU counter sets: | |
27 | * Basic counter set: 0-31 | |
28 | * Problem-state counter set: 32-63 | |
29 | * Crypto-activity counter set: 64-127 | |
30 | * Extented counter set: 128-159 | |
31 | */ | |
32 | enum cpumf_ctr_set { | |
33 | /* CPU counter sets */ | |
34 | CPUMF_CTR_SET_BASIC = 0, | |
35 | CPUMF_CTR_SET_USER = 1, | |
36 | CPUMF_CTR_SET_CRYPTO = 2, | |
37 | CPUMF_CTR_SET_EXT = 3, | |
38 | ||
39 | /* Maximum number of counter sets */ | |
40 | CPUMF_CTR_SET_MAX, | |
41 | }; | |
42 | ||
43 | #define CPUMF_LCCTL_ENABLE_SHIFT 16 | |
44 | #define CPUMF_LCCTL_ACTCTL_SHIFT 0 | |
45 | static const u64 cpumf_state_ctl[CPUMF_CTR_SET_MAX] = { | |
46 | [CPUMF_CTR_SET_BASIC] = 0x02, | |
47 | [CPUMF_CTR_SET_USER] = 0x04, | |
48 | [CPUMF_CTR_SET_CRYPTO] = 0x08, | |
49 | [CPUMF_CTR_SET_EXT] = 0x01, | |
50 | }; | |
51 | ||
52 | static void ctr_set_enable(u64 *state, int ctr_set) | |
53 | { | |
54 | *state |= cpumf_state_ctl[ctr_set] << CPUMF_LCCTL_ENABLE_SHIFT; | |
55 | } | |
56 | static void ctr_set_disable(u64 *state, int ctr_set) | |
57 | { | |
58 | *state &= ~(cpumf_state_ctl[ctr_set] << CPUMF_LCCTL_ENABLE_SHIFT); | |
59 | } | |
60 | static void ctr_set_start(u64 *state, int ctr_set) | |
61 | { | |
62 | *state |= cpumf_state_ctl[ctr_set] << CPUMF_LCCTL_ACTCTL_SHIFT; | |
63 | } | |
64 | static void ctr_set_stop(u64 *state, int ctr_set) | |
65 | { | |
66 | *state &= ~(cpumf_state_ctl[ctr_set] << CPUMF_LCCTL_ACTCTL_SHIFT); | |
67 | } | |
68 | ||
69 | /* Local CPUMF event structure */ | |
70 | struct cpu_hw_events { | |
71 | struct cpumf_ctr_info info; | |
72 | atomic_t ctr_set[CPUMF_CTR_SET_MAX]; | |
73 | u64 state, tx_state; | |
74 | unsigned int flags; | |
75 | }; | |
76 | static DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events) = { | |
77 | .ctr_set = { | |
78 | [CPUMF_CTR_SET_BASIC] = ATOMIC_INIT(0), | |
79 | [CPUMF_CTR_SET_USER] = ATOMIC_INIT(0), | |
80 | [CPUMF_CTR_SET_CRYPTO] = ATOMIC_INIT(0), | |
81 | [CPUMF_CTR_SET_EXT] = ATOMIC_INIT(0), | |
82 | }, | |
83 | .state = 0, | |
84 | .flags = 0, | |
85 | }; | |
86 | ||
87 | static int get_counter_set(u64 event) | |
88 | { | |
89 | int set = -1; | |
90 | ||
91 | if (event < 32) | |
92 | set = CPUMF_CTR_SET_BASIC; | |
93 | else if (event < 64) | |
94 | set = CPUMF_CTR_SET_USER; | |
95 | else if (event < 128) | |
96 | set = CPUMF_CTR_SET_CRYPTO; | |
97 | else if (event < 160) | |
98 | set = CPUMF_CTR_SET_EXT; | |
99 | ||
100 | return set; | |
101 | } | |
102 | ||
103 | static int validate_event(const struct hw_perf_event *hwc) | |
104 | { | |
105 | switch (hwc->config_base) { | |
106 | case CPUMF_CTR_SET_BASIC: | |
107 | case CPUMF_CTR_SET_USER: | |
108 | case CPUMF_CTR_SET_CRYPTO: | |
109 | case CPUMF_CTR_SET_EXT: | |
110 | /* check for reserved counters */ | |
111 | if ((hwc->config >= 6 && hwc->config <= 31) || | |
112 | (hwc->config >= 38 && hwc->config <= 63) || | |
113 | (hwc->config >= 80 && hwc->config <= 127)) | |
114 | return -EOPNOTSUPP; | |
115 | break; | |
116 | default: | |
117 | return -EINVAL; | |
118 | } | |
119 | ||
120 | return 0; | |
121 | } | |
122 | ||
123 | static int validate_ctr_version(const struct hw_perf_event *hwc) | |
124 | { | |
125 | struct cpu_hw_events *cpuhw; | |
126 | int err = 0; | |
127 | ||
128 | cpuhw = &get_cpu_var(cpu_hw_events); | |
129 | ||
130 | /* check required version for counter sets */ | |
131 | switch (hwc->config_base) { | |
132 | case CPUMF_CTR_SET_BASIC: | |
133 | case CPUMF_CTR_SET_USER: | |
134 | if (cpuhw->info.cfvn < 1) | |
135 | err = -EOPNOTSUPP; | |
136 | break; | |
137 | case CPUMF_CTR_SET_CRYPTO: | |
138 | case CPUMF_CTR_SET_EXT: | |
139 | if (cpuhw->info.csvn < 1) | |
140 | err = -EOPNOTSUPP; | |
141 | break; | |
142 | } | |
143 | ||
144 | put_cpu_var(cpu_hw_events); | |
145 | return err; | |
146 | } | |
147 | ||
148 | static int validate_ctr_auth(const struct hw_perf_event *hwc) | |
149 | { | |
150 | struct cpu_hw_events *cpuhw; | |
151 | u64 ctrs_state; | |
152 | int err = 0; | |
153 | ||
154 | cpuhw = &get_cpu_var(cpu_hw_events); | |
155 | ||
156 | /* check authorization for cpu counter sets */ | |
157 | ctrs_state = cpumf_state_ctl[hwc->config_base]; | |
158 | if (!(ctrs_state & cpuhw->info.auth_ctl)) | |
159 | err = -EPERM; | |
160 | ||
161 | put_cpu_var(cpu_hw_events); | |
162 | return err; | |
163 | } | |
164 | ||
165 | /* | |
166 | * Change the CPUMF state to active. | |
167 | * Enable and activate the CPU-counter sets according | |
168 | * to the per-cpu control state. | |
169 | */ | |
170 | static void cpumf_pmu_enable(struct pmu *pmu) | |
171 | { | |
172 | struct cpu_hw_events *cpuhw = &__get_cpu_var(cpu_hw_events); | |
173 | int err; | |
174 | ||
175 | if (cpuhw->flags & PMU_F_ENABLED) | |
176 | return; | |
177 | ||
178 | err = lcctl(cpuhw->state); | |
179 | if (err) { | |
180 | pr_err("Enabling the performance measuring unit " | |
af0ee94e | 181 | "failed with rc=%x\n", err); |
212188a5 HB |
182 | return; |
183 | } | |
184 | ||
185 | cpuhw->flags |= PMU_F_ENABLED; | |
186 | } | |
187 | ||
188 | /* | |
189 | * Change the CPUMF state to inactive. | |
190 | * Disable and enable (inactive) the CPU-counter sets according | |
191 | * to the per-cpu control state. | |
192 | */ | |
193 | static void cpumf_pmu_disable(struct pmu *pmu) | |
194 | { | |
195 | struct cpu_hw_events *cpuhw = &__get_cpu_var(cpu_hw_events); | |
196 | int err; | |
197 | u64 inactive; | |
198 | ||
199 | if (!(cpuhw->flags & PMU_F_ENABLED)) | |
200 | return; | |
201 | ||
202 | inactive = cpuhw->state & ~((1 << CPUMF_LCCTL_ENABLE_SHIFT) - 1); | |
203 | err = lcctl(inactive); | |
204 | if (err) { | |
205 | pr_err("Disabling the performance measuring unit " | |
af0ee94e | 206 | "failed with rc=%x\n", err); |
212188a5 HB |
207 | return; |
208 | } | |
209 | ||
210 | cpuhw->flags &= ~PMU_F_ENABLED; | |
211 | } | |
212 | ||
213 | ||
214 | /* Number of perf events counting hardware events */ | |
215 | static atomic_t num_events = ATOMIC_INIT(0); | |
216 | /* Used to avoid races in calling reserve/release_cpumf_hardware */ | |
217 | static DEFINE_MUTEX(pmc_reserve_mutex); | |
218 | ||
219 | /* CPU-measurement alerts for the counter facility */ | |
220 | static void cpumf_measurement_alert(struct ext_code ext_code, | |
221 | unsigned int alert, unsigned long unused) | |
222 | { | |
223 | struct cpu_hw_events *cpuhw; | |
224 | ||
225 | if (!(alert & CPU_MF_INT_CF_MASK)) | |
226 | return; | |
227 | ||
02456169 | 228 | kstat_cpu(smp_processor_id()).irqs[EXTINT_CMC]++; |
212188a5 HB |
229 | cpuhw = &__get_cpu_var(cpu_hw_events); |
230 | ||
231 | /* Measurement alerts are shared and might happen when the PMU | |
232 | * is not reserved. Ignore these alerts in this case. */ | |
233 | if (!(cpuhw->flags & PMU_F_RESERVED)) | |
234 | return; | |
235 | ||
236 | /* counter authorization change alert */ | |
237 | if (alert & CPU_MF_INT_CF_CACA) | |
238 | qctri(&cpuhw->info); | |
239 | ||
240 | /* loss of counter data alert */ | |
241 | if (alert & CPU_MF_INT_CF_LCDA) | |
242 | pr_err("CPU[%i] Counter data was lost\n", smp_processor_id()); | |
243 | } | |
244 | ||
245 | #define PMC_INIT 0 | |
246 | #define PMC_RELEASE 1 | |
247 | static void setup_pmc_cpu(void *flags) | |
248 | { | |
249 | struct cpu_hw_events *cpuhw = &__get_cpu_var(cpu_hw_events); | |
250 | ||
251 | switch (*((int *) flags)) { | |
252 | case PMC_INIT: | |
253 | memset(&cpuhw->info, 0, sizeof(cpuhw->info)); | |
254 | qctri(&cpuhw->info); | |
255 | cpuhw->flags |= PMU_F_RESERVED; | |
256 | break; | |
257 | ||
258 | case PMC_RELEASE: | |
259 | cpuhw->flags &= ~PMU_F_RESERVED; | |
260 | break; | |
261 | } | |
262 | ||
263 | /* Disable CPU counter sets */ | |
264 | lcctl(0); | |
265 | } | |
266 | ||
267 | /* Initialize the CPU-measurement facility */ | |
268 | static int reserve_pmc_hardware(void) | |
269 | { | |
270 | int flags = PMC_INIT; | |
271 | ||
272 | on_each_cpu(setup_pmc_cpu, &flags, 1); | |
273 | measurement_alert_subclass_register(); | |
274 | ||
275 | return 0; | |
276 | } | |
277 | ||
278 | /* Release the CPU-measurement facility */ | |
279 | static void release_pmc_hardware(void) | |
280 | { | |
281 | int flags = PMC_RELEASE; | |
282 | ||
283 | on_each_cpu(setup_pmc_cpu, &flags, 1); | |
284 | measurement_alert_subclass_unregister(); | |
285 | } | |
286 | ||
287 | /* Release the PMU if event is the last perf event */ | |
288 | static void hw_perf_event_destroy(struct perf_event *event) | |
289 | { | |
290 | if (!atomic_add_unless(&num_events, -1, 1)) { | |
291 | mutex_lock(&pmc_reserve_mutex); | |
292 | if (atomic_dec_return(&num_events) == 0) | |
293 | release_pmc_hardware(); | |
294 | mutex_unlock(&pmc_reserve_mutex); | |
295 | } | |
296 | } | |
297 | ||
298 | /* CPUMF <-> perf event mappings for kernel+userspace (basic set) */ | |
299 | static const int cpumf_generic_events_basic[] = { | |
300 | [PERF_COUNT_HW_CPU_CYCLES] = 0, | |
301 | [PERF_COUNT_HW_INSTRUCTIONS] = 1, | |
302 | [PERF_COUNT_HW_CACHE_REFERENCES] = -1, | |
303 | [PERF_COUNT_HW_CACHE_MISSES] = -1, | |
304 | [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = -1, | |
305 | [PERF_COUNT_HW_BRANCH_MISSES] = -1, | |
306 | [PERF_COUNT_HW_BUS_CYCLES] = -1, | |
307 | }; | |
308 | /* CPUMF <-> perf event mappings for userspace (problem-state set) */ | |
309 | static const int cpumf_generic_events_user[] = { | |
310 | [PERF_COUNT_HW_CPU_CYCLES] = 32, | |
311 | [PERF_COUNT_HW_INSTRUCTIONS] = 33, | |
312 | [PERF_COUNT_HW_CACHE_REFERENCES] = -1, | |
313 | [PERF_COUNT_HW_CACHE_MISSES] = -1, | |
314 | [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = -1, | |
315 | [PERF_COUNT_HW_BRANCH_MISSES] = -1, | |
316 | [PERF_COUNT_HW_BUS_CYCLES] = -1, | |
317 | }; | |
318 | ||
319 | static int __hw_perf_event_init(struct perf_event *event) | |
320 | { | |
321 | struct perf_event_attr *attr = &event->attr; | |
322 | struct hw_perf_event *hwc = &event->hw; | |
323 | int err; | |
324 | u64 ev; | |
325 | ||
326 | switch (attr->type) { | |
327 | case PERF_TYPE_RAW: | |
328 | /* Raw events are used to access counters directly, | |
329 | * hence do not permit excludes */ | |
330 | if (attr->exclude_kernel || attr->exclude_user || | |
331 | attr->exclude_hv) | |
332 | return -EOPNOTSUPP; | |
333 | ev = attr->config; | |
334 | break; | |
335 | ||
336 | case PERF_TYPE_HARDWARE: | |
337 | ev = attr->config; | |
338 | /* Count user space (problem-state) only */ | |
339 | if (!attr->exclude_user && attr->exclude_kernel) { | |
340 | if (ev >= ARRAY_SIZE(cpumf_generic_events_user)) | |
341 | return -EOPNOTSUPP; | |
342 | ev = cpumf_generic_events_user[ev]; | |
343 | ||
344 | /* No support for kernel space counters only */ | |
345 | } else if (!attr->exclude_kernel && attr->exclude_user) { | |
346 | return -EOPNOTSUPP; | |
347 | ||
348 | /* Count user and kernel space */ | |
349 | } else { | |
350 | if (ev >= ARRAY_SIZE(cpumf_generic_events_basic)) | |
351 | return -EOPNOTSUPP; | |
352 | ev = cpumf_generic_events_basic[ev]; | |
353 | } | |
354 | break; | |
355 | ||
356 | default: | |
357 | return -ENOENT; | |
358 | } | |
359 | ||
360 | if (ev == -1) | |
361 | return -ENOENT; | |
362 | ||
363 | if (ev >= PERF_CPUM_CF_MAX_CTR) | |
364 | return -EINVAL; | |
365 | ||
366 | /* The CPU measurement counter facility does not have any interrupts | |
367 | * to do sampling. Sampling must be provided by external means, | |
368 | * for example, by timers. | |
369 | */ | |
370 | if (hwc->sample_period) | |
371 | return -EINVAL; | |
372 | ||
373 | /* Use the hardware perf event structure to store the counter number | |
374 | * in 'config' member and the counter set to which the counter belongs | |
375 | * in the 'config_base'. The counter set (config_base) is then used | |
376 | * to enable/disable the counters. | |
377 | */ | |
378 | hwc->config = ev; | |
379 | hwc->config_base = get_counter_set(ev); | |
380 | ||
381 | /* Validate the counter that is assigned to this event. | |
382 | * Because the counter facility can use numerous counters at the | |
383 | * same time without constraints, it is not necessary to explicity | |
384 | * validate event groups (event->group_leader != event). | |
385 | */ | |
386 | err = validate_event(hwc); | |
387 | if (err) | |
388 | return err; | |
389 | ||
390 | /* Initialize for using the CPU-measurement counter facility */ | |
391 | if (!atomic_inc_not_zero(&num_events)) { | |
392 | mutex_lock(&pmc_reserve_mutex); | |
393 | if (atomic_read(&num_events) == 0 && reserve_pmc_hardware()) | |
394 | err = -EBUSY; | |
395 | else | |
396 | atomic_inc(&num_events); | |
397 | mutex_unlock(&pmc_reserve_mutex); | |
398 | } | |
399 | event->destroy = hw_perf_event_destroy; | |
400 | ||
401 | /* Finally, validate version and authorization of the counter set */ | |
402 | err = validate_ctr_auth(hwc); | |
403 | if (!err) | |
404 | err = validate_ctr_version(hwc); | |
405 | ||
406 | return err; | |
407 | } | |
408 | ||
409 | static int cpumf_pmu_event_init(struct perf_event *event) | |
410 | { | |
411 | int err; | |
412 | ||
413 | switch (event->attr.type) { | |
414 | case PERF_TYPE_HARDWARE: | |
415 | case PERF_TYPE_HW_CACHE: | |
416 | case PERF_TYPE_RAW: | |
417 | err = __hw_perf_event_init(event); | |
418 | break; | |
419 | default: | |
420 | return -ENOENT; | |
421 | } | |
422 | ||
423 | if (unlikely(err) && event->destroy) | |
424 | event->destroy(event); | |
425 | ||
426 | return err; | |
427 | } | |
428 | ||
429 | static int hw_perf_event_reset(struct perf_event *event) | |
430 | { | |
431 | u64 prev, new; | |
432 | int err; | |
433 | ||
434 | do { | |
435 | prev = local64_read(&event->hw.prev_count); | |
436 | err = ecctr(event->hw.config, &new); | |
437 | if (err) { | |
438 | if (err != 3) | |
439 | break; | |
440 | /* The counter is not (yet) available. This | |
441 | * might happen if the counter set to which | |
442 | * this counter belongs is in the disabled | |
443 | * state. | |
444 | */ | |
445 | new = 0; | |
446 | } | |
447 | } while (local64_cmpxchg(&event->hw.prev_count, prev, new) != prev); | |
448 | ||
449 | return err; | |
450 | } | |
451 | ||
452 | static int hw_perf_event_update(struct perf_event *event) | |
453 | { | |
454 | u64 prev, new, delta; | |
455 | int err; | |
456 | ||
457 | do { | |
458 | prev = local64_read(&event->hw.prev_count); | |
459 | err = ecctr(event->hw.config, &new); | |
460 | if (err) | |
461 | goto out; | |
462 | } while (local64_cmpxchg(&event->hw.prev_count, prev, new) != prev); | |
463 | ||
464 | delta = (prev <= new) ? new - prev | |
465 | : (-1ULL - prev) + new + 1; /* overflow */ | |
466 | local64_add(delta, &event->count); | |
467 | out: | |
468 | return err; | |
469 | } | |
470 | ||
471 | static void cpumf_pmu_read(struct perf_event *event) | |
472 | { | |
473 | if (event->hw.state & PERF_HES_STOPPED) | |
474 | return; | |
475 | ||
476 | hw_perf_event_update(event); | |
477 | } | |
478 | ||
479 | static void cpumf_pmu_start(struct perf_event *event, int flags) | |
480 | { | |
481 | struct cpu_hw_events *cpuhw = &__get_cpu_var(cpu_hw_events); | |
482 | struct hw_perf_event *hwc = &event->hw; | |
483 | ||
484 | if (WARN_ON_ONCE(!(hwc->state & PERF_HES_STOPPED))) | |
485 | return; | |
486 | ||
487 | if (WARN_ON_ONCE(hwc->config == -1)) | |
488 | return; | |
489 | ||
490 | if (flags & PERF_EF_RELOAD) | |
491 | WARN_ON_ONCE(!(hwc->state & PERF_HES_UPTODATE)); | |
492 | ||
493 | hwc->state = 0; | |
494 | ||
495 | /* (Re-)enable and activate the counter set */ | |
496 | ctr_set_enable(&cpuhw->state, hwc->config_base); | |
497 | ctr_set_start(&cpuhw->state, hwc->config_base); | |
498 | ||
499 | /* The counter set to which this counter belongs can be already active. | |
500 | * Because all counters in a set are active, the event->hw.prev_count | |
501 | * needs to be synchronized. At this point, the counter set can be in | |
502 | * the inactive or disabled state. | |
503 | */ | |
504 | hw_perf_event_reset(event); | |
505 | ||
506 | /* increment refcount for this counter set */ | |
507 | atomic_inc(&cpuhw->ctr_set[hwc->config_base]); | |
508 | } | |
509 | ||
510 | static void cpumf_pmu_stop(struct perf_event *event, int flags) | |
511 | { | |
512 | struct cpu_hw_events *cpuhw = &__get_cpu_var(cpu_hw_events); | |
513 | struct hw_perf_event *hwc = &event->hw; | |
514 | ||
515 | if (!(hwc->state & PERF_HES_STOPPED)) { | |
516 | /* Decrement reference count for this counter set and if this | |
517 | * is the last used counter in the set, clear activation | |
518 | * control and set the counter set state to inactive. | |
519 | */ | |
520 | if (!atomic_dec_return(&cpuhw->ctr_set[hwc->config_base])) | |
521 | ctr_set_stop(&cpuhw->state, hwc->config_base); | |
522 | event->hw.state |= PERF_HES_STOPPED; | |
523 | } | |
524 | ||
525 | if ((flags & PERF_EF_UPDATE) && !(hwc->state & PERF_HES_UPTODATE)) { | |
526 | hw_perf_event_update(event); | |
527 | event->hw.state |= PERF_HES_UPTODATE; | |
528 | } | |
529 | } | |
530 | ||
531 | static int cpumf_pmu_add(struct perf_event *event, int flags) | |
532 | { | |
533 | struct cpu_hw_events *cpuhw = &__get_cpu_var(cpu_hw_events); | |
534 | ||
535 | /* Check authorization for the counter set to which this | |
536 | * counter belongs. | |
537 | * For group events transaction, the authorization check is | |
538 | * done in cpumf_pmu_commit_txn(). | |
539 | */ | |
540 | if (!(cpuhw->flags & PERF_EVENT_TXN)) | |
541 | if (validate_ctr_auth(&event->hw)) | |
542 | return -EPERM; | |
543 | ||
544 | ctr_set_enable(&cpuhw->state, event->hw.config_base); | |
545 | event->hw.state = PERF_HES_UPTODATE | PERF_HES_STOPPED; | |
546 | ||
547 | if (flags & PERF_EF_START) | |
548 | cpumf_pmu_start(event, PERF_EF_RELOAD); | |
549 | ||
550 | perf_event_update_userpage(event); | |
551 | ||
552 | return 0; | |
553 | } | |
554 | ||
555 | static void cpumf_pmu_del(struct perf_event *event, int flags) | |
556 | { | |
557 | struct cpu_hw_events *cpuhw = &__get_cpu_var(cpu_hw_events); | |
558 | ||
559 | cpumf_pmu_stop(event, PERF_EF_UPDATE); | |
560 | ||
561 | /* Check if any counter in the counter set is still used. If not used, | |
562 | * change the counter set to the disabled state. This also clears the | |
563 | * content of all counters in the set. | |
564 | * | |
565 | * When a new perf event has been added but not yet started, this can | |
566 | * clear enable control and resets all counters in a set. Therefore, | |
567 | * cpumf_pmu_start() always has to reenable a counter set. | |
568 | */ | |
569 | if (!atomic_read(&cpuhw->ctr_set[event->hw.config_base])) | |
570 | ctr_set_disable(&cpuhw->state, event->hw.config_base); | |
571 | ||
572 | perf_event_update_userpage(event); | |
573 | } | |
574 | ||
575 | /* | |
576 | * Start group events scheduling transaction. | |
577 | * Set flags to perform a single test at commit time. | |
578 | */ | |
579 | static void cpumf_pmu_start_txn(struct pmu *pmu) | |
580 | { | |
581 | struct cpu_hw_events *cpuhw = &__get_cpu_var(cpu_hw_events); | |
582 | ||
583 | perf_pmu_disable(pmu); | |
584 | cpuhw->flags |= PERF_EVENT_TXN; | |
585 | cpuhw->tx_state = cpuhw->state; | |
586 | } | |
587 | ||
588 | /* | |
589 | * Stop and cancel a group events scheduling tranctions. | |
590 | * Assumes cpumf_pmu_del() is called for each successful added | |
591 | * cpumf_pmu_add() during the transaction. | |
592 | */ | |
593 | static void cpumf_pmu_cancel_txn(struct pmu *pmu) | |
594 | { | |
595 | struct cpu_hw_events *cpuhw = &__get_cpu_var(cpu_hw_events); | |
596 | ||
597 | WARN_ON(cpuhw->tx_state != cpuhw->state); | |
598 | ||
599 | cpuhw->flags &= ~PERF_EVENT_TXN; | |
600 | perf_pmu_enable(pmu); | |
601 | } | |
602 | ||
603 | /* | |
604 | * Commit the group events scheduling transaction. On success, the | |
605 | * transaction is closed. On error, the transaction is kept open | |
606 | * until cpumf_pmu_cancel_txn() is called. | |
607 | */ | |
608 | static int cpumf_pmu_commit_txn(struct pmu *pmu) | |
609 | { | |
610 | struct cpu_hw_events *cpuhw = &__get_cpu_var(cpu_hw_events); | |
611 | u64 state; | |
612 | ||
613 | /* check if the updated state can be scheduled */ | |
614 | state = cpuhw->state & ~((1 << CPUMF_LCCTL_ENABLE_SHIFT) - 1); | |
615 | state >>= CPUMF_LCCTL_ENABLE_SHIFT; | |
616 | if ((state & cpuhw->info.auth_ctl) != state) | |
617 | return -EPERM; | |
618 | ||
619 | cpuhw->flags &= ~PERF_EVENT_TXN; | |
620 | perf_pmu_enable(pmu); | |
621 | return 0; | |
622 | } | |
623 | ||
624 | /* Performance monitoring unit for s390x */ | |
625 | static struct pmu cpumf_pmu = { | |
626 | .pmu_enable = cpumf_pmu_enable, | |
627 | .pmu_disable = cpumf_pmu_disable, | |
628 | .event_init = cpumf_pmu_event_init, | |
629 | .add = cpumf_pmu_add, | |
630 | .del = cpumf_pmu_del, | |
631 | .start = cpumf_pmu_start, | |
632 | .stop = cpumf_pmu_stop, | |
633 | .read = cpumf_pmu_read, | |
634 | .start_txn = cpumf_pmu_start_txn, | |
635 | .commit_txn = cpumf_pmu_commit_txn, | |
636 | .cancel_txn = cpumf_pmu_cancel_txn, | |
637 | }; | |
638 | ||
639 | static int __cpuinit cpumf_pmu_notifier(struct notifier_block *self, | |
640 | unsigned long action, void *hcpu) | |
641 | { | |
642 | unsigned int cpu = (long) hcpu; | |
643 | int flags; | |
644 | ||
645 | switch (action & ~CPU_TASKS_FROZEN) { | |
646 | case CPU_ONLINE: | |
647 | flags = PMC_INIT; | |
648 | smp_call_function_single(cpu, setup_pmc_cpu, &flags, 1); | |
649 | break; | |
650 | case CPU_DOWN_PREPARE: | |
651 | flags = PMC_RELEASE; | |
652 | smp_call_function_single(cpu, setup_pmc_cpu, &flags, 1); | |
653 | break; | |
654 | default: | |
655 | break; | |
656 | } | |
657 | ||
658 | return NOTIFY_OK; | |
659 | } | |
660 | ||
661 | static int __init cpumf_pmu_init(void) | |
662 | { | |
663 | int rc; | |
664 | ||
665 | if (!cpum_cf_avail()) | |
666 | return -ENODEV; | |
667 | ||
668 | /* clear bit 15 of cr0 to unauthorize problem-state to | |
669 | * extract measurement counters */ | |
670 | ctl_clear_bit(0, 48); | |
671 | ||
672 | /* register handler for measurement-alert interruptions */ | |
673 | rc = register_external_interrupt(0x1407, cpumf_measurement_alert); | |
674 | if (rc) { | |
675 | pr_err("Registering for CPU-measurement alerts " | |
676 | "failed with rc=%i\n", rc); | |
677 | goto out; | |
678 | } | |
679 | ||
680 | rc = perf_pmu_register(&cpumf_pmu, "cpum_cf", PERF_TYPE_RAW); | |
681 | if (rc) { | |
682 | pr_err("Registering the cpum_cf PMU failed with rc=%i\n", rc); | |
683 | unregister_external_interrupt(0x1407, cpumf_measurement_alert); | |
684 | goto out; | |
685 | } | |
686 | perf_cpu_notifier(cpumf_pmu_notifier); | |
687 | out: | |
688 | return rc; | |
689 | } | |
690 | early_initcall(cpumf_pmu_init); |