Commit | Line | Data |
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1da177e4 | 1 | /* |
f5daba1d | 2 | * Machine check handler |
1da177e4 | 3 | * |
a53c8fab | 4 | * Copyright IBM Corp. 2000, 2009 |
f5daba1d HC |
5 | * Author(s): Ingo Adlung <adlung@de.ibm.com>, |
6 | * Martin Schwidefsky <schwidefsky@de.ibm.com>, | |
7 | * Cornelia Huck <cornelia.huck@de.ibm.com>, | |
8 | * Heiko Carstens <heiko.carstens@de.ibm.com>, | |
1da177e4 LT |
9 | */ |
10 | ||
052ff461 | 11 | #include <linux/kernel_stat.h> |
1da177e4 | 12 | #include <linux/init.h> |
1da177e4 | 13 | #include <linux/errno.h> |
81f64b87 | 14 | #include <linux/hardirq.h> |
022e4fc0 | 15 | #include <linux/time.h> |
f5daba1d | 16 | #include <linux/module.h> |
1da177e4 | 17 | #include <asm/lowcore.h> |
f5daba1d HC |
18 | #include <asm/smp.h> |
19 | #include <asm/etr.h> | |
76d4e00a | 20 | #include <asm/cputime.h> |
f5daba1d HC |
21 | #include <asm/nmi.h> |
22 | #include <asm/crw.h> | |
80703617 | 23 | #include <asm/switch_to.h> |
cad49cfc | 24 | #include <asm/ctl_reg.h> |
1da177e4 | 25 | |
77fa2245 HC |
26 | struct mcck_struct { |
27 | int kill_task; | |
28 | int channel_report; | |
29 | int warning; | |
30 | unsigned long long mcck_code; | |
31 | }; | |
32 | ||
33 | static DEFINE_PER_CPU(struct mcck_struct, cpu_mcck); | |
34 | ||
9402c95f | 35 | static void s390_handle_damage(char *msg) |
f5daba1d HC |
36 | { |
37 | smp_send_stop(); | |
38 | disabled_wait((unsigned long) __builtin_return_address(0)); | |
39 | while (1); | |
40 | } | |
41 | ||
1da177e4 | 42 | /* |
77fa2245 HC |
43 | * Main machine check handler function. Will be called with interrupts enabled |
44 | * or disabled and machine checks enabled or disabled. | |
1da177e4 | 45 | */ |
f5daba1d | 46 | void s390_handle_mcck(void) |
1da177e4 | 47 | { |
77fa2245 HC |
48 | unsigned long flags; |
49 | struct mcck_struct mcck; | |
1da177e4 | 50 | |
77fa2245 HC |
51 | /* |
52 | * Disable machine checks and get the current state of accumulated | |
53 | * machine checks. Afterwards delete the old state and enable machine | |
54 | * checks again. | |
55 | */ | |
56 | local_irq_save(flags); | |
57 | local_mcck_disable(); | |
2cb4a182 SO |
58 | mcck = *this_cpu_ptr(&cpu_mcck); |
59 | memset(this_cpu_ptr(&cpu_mcck), 0, sizeof(mcck)); | |
d3a73acb | 60 | clear_cpu_flag(CIF_MCCK_PENDING); |
77fa2245 HC |
61 | local_mcck_enable(); |
62 | local_irq_restore(flags); | |
1da177e4 | 63 | |
77fa2245 | 64 | if (mcck.channel_report) |
f5daba1d | 65 | crw_handle_channel_report(); |
7b886416 HC |
66 | /* |
67 | * A warning may remain for a prolonged period on the bare iron. | |
68 | * (actually until the machine is powered off, or the problem is gone) | |
69 | * So we just stop listening for the WARNING MCH and avoid continuously | |
70 | * being interrupted. One caveat is however, that we must do this per | |
71 | * processor and cannot use the smp version of ctl_clear_bit(). | |
72 | * On VM we only get one interrupt per virtally presented machinecheck. | |
73 | * Though one suffices, we may get one interrupt per (virtual) cpu. | |
74 | */ | |
77fa2245 | 75 | if (mcck.warning) { /* WARNING pending ? */ |
1da177e4 | 76 | static int mchchk_wng_posted = 0; |
7b886416 HC |
77 | |
78 | /* Use single cpu clear, as we cannot handle smp here. */ | |
1da177e4 LT |
79 | __ctl_clear_bit(14, 24); /* Disable WARNING MCH */ |
80 | if (xchg(&mchchk_wng_posted, 1) == 0) | |
9ec52099 | 81 | kill_cad_pid(SIGPWR, 1); |
1da177e4 | 82 | } |
77fa2245 HC |
83 | if (mcck.kill_task) { |
84 | local_irq_enable(); | |
85 | printk(KERN_EMERG "mcck: Terminating task because of machine " | |
86 | "malfunction (code 0x%016llx).\n", mcck.mcck_code); | |
87 | printk(KERN_EMERG "mcck: task: %s, pid: %d.\n", | |
88 | current->comm, current->pid); | |
89 | do_exit(SIGSEGV); | |
90 | } | |
91 | } | |
71cde587 | 92 | EXPORT_SYMBOL_GPL(s390_handle_mcck); |
77fa2245 HC |
93 | |
94 | /* | |
95 | * returns 0 if all registers could be validated | |
96 | * returns 1 otherwise | |
97 | */ | |
f5daba1d | 98 | static int notrace s390_revalidate_registers(struct mci *mci) |
77fa2245 HC |
99 | { |
100 | int kill_task; | |
77fa2245 HC |
101 | u64 zero; |
102 | void *fpt_save_area, *fpt_creg_save_area; | |
103 | ||
104 | kill_task = 0; | |
105 | zero = 0; | |
f5daba1d HC |
106 | |
107 | if (!mci->gr) { | |
77fa2245 HC |
108 | /* |
109 | * General purpose registers couldn't be restored and have | |
110 | * unknown contents. Process needs to be terminated. | |
111 | */ | |
112 | kill_task = 1; | |
f5daba1d HC |
113 | } |
114 | if (!mci->fp) { | |
77fa2245 HC |
115 | /* |
116 | * Floating point registers can't be restored and | |
117 | * therefore the process needs to be terminated. | |
118 | */ | |
119 | kill_task = 1; | |
f5daba1d | 120 | } |
5a79859a HC |
121 | fpt_save_area = &S390_lowcore.floating_pt_save_area; |
122 | fpt_creg_save_area = &S390_lowcore.fpt_creg_save_area; | |
123 | if (!mci->fc) { | |
124 | /* | |
125 | * Floating point control register can't be restored. | |
126 | * Task will be terminated. | |
127 | */ | |
128 | asm volatile("lfpc 0(%0)" : : "a" (&zero), "m" (zero)); | |
129 | kill_task = 1; | |
130 | } else | |
131 | asm volatile("lfpc 0(%0)" : : "a" (fpt_creg_save_area)); | |
132 | ||
cad49cfc HC |
133 | if (!MACHINE_HAS_VX) { |
134 | /* Revalidate floating point registers */ | |
135 | asm volatile( | |
136 | " ld 0,0(%0)\n" | |
137 | " ld 1,8(%0)\n" | |
138 | " ld 2,16(%0)\n" | |
139 | " ld 3,24(%0)\n" | |
140 | " ld 4,32(%0)\n" | |
141 | " ld 5,40(%0)\n" | |
142 | " ld 6,48(%0)\n" | |
143 | " ld 7,56(%0)\n" | |
144 | " ld 8,64(%0)\n" | |
145 | " ld 9,72(%0)\n" | |
146 | " ld 10,80(%0)\n" | |
147 | " ld 11,88(%0)\n" | |
148 | " ld 12,96(%0)\n" | |
149 | " ld 13,104(%0)\n" | |
150 | " ld 14,112(%0)\n" | |
151 | " ld 15,120(%0)\n" | |
152 | : : "a" (fpt_save_area)); | |
153 | } else { | |
154 | /* Revalidate vector registers */ | |
155 | union ctlreg0 cr0; | |
156 | ||
80703617 MS |
157 | if (!mci->vr) { |
158 | /* | |
159 | * Vector registers can't be restored and therefore | |
160 | * the process needs to be terminated. | |
161 | */ | |
162 | kill_task = 1; | |
163 | } | |
cad49cfc HC |
164 | cr0.val = S390_lowcore.cregs_save_area[0]; |
165 | cr0.afp = cr0.vx = 1; | |
166 | __ctl_load(cr0.val, 0, 0); | |
80703617 | 167 | restore_vx_regs((__vector128 *) |
cad49cfc HC |
168 | &S390_lowcore.vector_save_area); |
169 | __ctl_load(S390_lowcore.cregs_save_area[0], 0, 0); | |
80703617 | 170 | } |
77fa2245 | 171 | /* Revalidate access registers */ |
94c12cc7 MS |
172 | asm volatile( |
173 | " lam 0,15,0(%0)" | |
174 | : : "a" (&S390_lowcore.access_regs_save_area)); | |
f5daba1d | 175 | if (!mci->ar) { |
77fa2245 HC |
176 | /* |
177 | * Access registers have unknown contents. | |
178 | * Terminating task. | |
179 | */ | |
180 | kill_task = 1; | |
f5daba1d | 181 | } |
77fa2245 | 182 | /* Revalidate control registers */ |
f5daba1d | 183 | if (!mci->cr) { |
77fa2245 HC |
184 | /* |
185 | * Control registers have unknown contents. | |
186 | * Can't recover and therefore stopping machine. | |
187 | */ | |
188 | s390_handle_damage("invalid control registers."); | |
f5daba1d | 189 | } else { |
94c12cc7 MS |
190 | asm volatile( |
191 | " lctlg 0,15,0(%0)" | |
192 | : : "a" (&S390_lowcore.cregs_save_area)); | |
f5daba1d | 193 | } |
77fa2245 HC |
194 | /* |
195 | * We don't even try to revalidate the TOD register, since we simply | |
196 | * can't write something sensible into that register. | |
197 | */ | |
77fa2245 HC |
198 | /* |
199 | * See if we can revalidate the TOD programmable register with its | |
200 | * old contents (should be zero) otherwise set it to zero. | |
201 | */ | |
202 | if (!mci->pr) | |
94c12cc7 MS |
203 | asm volatile( |
204 | " sr 0,0\n" | |
205 | " sckpf" | |
206 | : : : "0", "cc"); | |
77fa2245 HC |
207 | else |
208 | asm volatile( | |
94c12cc7 MS |
209 | " l 0,0(%0)\n" |
210 | " sckpf" | |
211 | : : "a" (&S390_lowcore.tod_progreg_save_area) | |
212 | : "0", "cc"); | |
77fa2245 | 213 | /* Revalidate clock comparator register */ |
b6bed093 | 214 | set_clock_comparator(S390_lowcore.clock_comparator); |
77fa2245 HC |
215 | /* Check if old PSW is valid */ |
216 | if (!mci->wp) | |
217 | /* | |
218 | * Can't tell if we come from user or kernel mode | |
219 | * -> stopping machine. | |
220 | */ | |
221 | s390_handle_damage("old psw invalid."); | |
222 | ||
223 | if (!mci->ms || !mci->pm || !mci->ia) | |
224 | kill_task = 1; | |
225 | ||
226 | return kill_task; | |
227 | } | |
228 | ||
b73d40c6 | 229 | #define MAX_IPD_COUNT 29 |
022e4fc0 | 230 | #define MAX_IPD_TIME (5 * 60 * USEC_PER_SEC) /* 5 minutes */ |
b73d40c6 | 231 | |
f5daba1d HC |
232 | #define ED_STP_ISLAND 6 /* External damage STP island check */ |
233 | #define ED_STP_SYNC 7 /* External damage STP sync check */ | |
234 | #define ED_ETR_SYNC 12 /* External damage ETR sync check */ | |
235 | #define ED_ETR_SWITCH 13 /* External damage ETR switch to local */ | |
236 | ||
77fa2245 HC |
237 | /* |
238 | * machine check handler. | |
239 | */ | |
cc54c1e6 | 240 | void notrace s390_do_machine_check(struct pt_regs *regs) |
77fa2245 | 241 | { |
f5daba1d | 242 | static int ipd_count; |
b73d40c6 HC |
243 | static DEFINE_SPINLOCK(ipd_lock); |
244 | static unsigned long long last_ipd; | |
f5daba1d | 245 | struct mcck_struct *mcck; |
b73d40c6 | 246 | unsigned long long tmp; |
77fa2245 | 247 | struct mci *mci; |
77fa2245 HC |
248 | int umode; |
249 | ||
81f64b87 | 250 | nmi_enter(); |
420f42ec | 251 | inc_irq_stat(NMI_NMI); |
77fa2245 | 252 | mci = (struct mci *) &S390_lowcore.mcck_interruption_code; |
eb7e7d76 | 253 | mcck = this_cpu_ptr(&cpu_mcck); |
77fa2245 HC |
254 | umode = user_mode(regs); |
255 | ||
f5daba1d | 256 | if (mci->sd) { |
77fa2245 HC |
257 | /* System damage -> stopping machine */ |
258 | s390_handle_damage("received system damage machine check."); | |
f5daba1d | 259 | } |
77fa2245 HC |
260 | if (mci->pd) { |
261 | if (mci->b) { | |
262 | /* Processing backup -> verify if we can survive this */ | |
263 | u64 z_mcic, o_mcic, t_mcic; | |
77fa2245 HC |
264 | z_mcic = (1ULL<<63 | 1ULL<<59 | 1ULL<<29); |
265 | o_mcic = (1ULL<<43 | 1ULL<<42 | 1ULL<<41 | 1ULL<<40 | | |
266 | 1ULL<<36 | 1ULL<<35 | 1ULL<<34 | 1ULL<<32 | | |
267 | 1ULL<<30 | 1ULL<<21 | 1ULL<<20 | 1ULL<<17 | | |
268 | 1ULL<<16); | |
77fa2245 HC |
269 | t_mcic = *(u64 *)mci; |
270 | ||
271 | if (((t_mcic & z_mcic) != 0) || | |
272 | ((t_mcic & o_mcic) != o_mcic)) { | |
273 | s390_handle_damage("processing backup machine " | |
274 | "check with damage."); | |
275 | } | |
b73d40c6 HC |
276 | |
277 | /* | |
278 | * Nullifying exigent condition, therefore we might | |
279 | * retry this instruction. | |
280 | */ | |
b73d40c6 | 281 | spin_lock(&ipd_lock); |
1aae0560 | 282 | tmp = get_tod_clock(); |
b73d40c6 HC |
283 | if (((tmp - last_ipd) >> 12) < MAX_IPD_TIME) |
284 | ipd_count++; | |
285 | else | |
286 | ipd_count = 1; | |
b73d40c6 | 287 | last_ipd = tmp; |
b73d40c6 HC |
288 | if (ipd_count == MAX_IPD_COUNT) |
289 | s390_handle_damage("too many ipd retries."); | |
b73d40c6 | 290 | spin_unlock(&ipd_lock); |
f5daba1d | 291 | } else { |
77fa2245 HC |
292 | /* Processing damage -> stopping machine */ |
293 | s390_handle_damage("received instruction processing " | |
294 | "damage machine check."); | |
295 | } | |
296 | } | |
297 | if (s390_revalidate_registers(mci)) { | |
298 | if (umode) { | |
299 | /* | |
300 | * Couldn't restore all register contents while in | |
301 | * user mode -> mark task for termination. | |
302 | */ | |
303 | mcck->kill_task = 1; | |
304 | mcck->mcck_code = *(unsigned long long *) mci; | |
d3a73acb | 305 | set_cpu_flag(CIF_MCCK_PENDING); |
f5daba1d | 306 | } else { |
77fa2245 HC |
307 | /* |
308 | * Couldn't restore all register contents while in | |
309 | * kernel mode -> stopping machine. | |
310 | */ | |
311 | s390_handle_damage("unable to revalidate registers."); | |
f5daba1d | 312 | } |
77fa2245 | 313 | } |
d54853ef MS |
314 | if (mci->cd) { |
315 | /* Timing facility damage */ | |
316 | s390_handle_damage("TOD clock damaged"); | |
317 | } | |
d54853ef MS |
318 | if (mci->ed && mci->ec) { |
319 | /* External damage */ | |
320 | if (S390_lowcore.external_damage_code & (1U << ED_ETR_SYNC)) | |
321 | etr_sync_check(); | |
322 | if (S390_lowcore.external_damage_code & (1U << ED_ETR_SWITCH)) | |
323 | etr_switch_to_local(); | |
d2fec595 MS |
324 | if (S390_lowcore.external_damage_code & (1U << ED_STP_SYNC)) |
325 | stp_sync_check(); | |
326 | if (S390_lowcore.external_damage_code & (1U << ED_STP_ISLAND)) | |
327 | stp_island_check(); | |
d54853ef | 328 | } |
77fa2245 HC |
329 | if (mci->se) |
330 | /* Storage error uncorrected */ | |
331 | s390_handle_damage("received storage error uncorrected " | |
332 | "machine check."); | |
77fa2245 HC |
333 | if (mci->ke) |
334 | /* Storage key-error uncorrected */ | |
335 | s390_handle_damage("received storage key-error uncorrected " | |
336 | "machine check."); | |
77fa2245 HC |
337 | if (mci->ds && mci->fa) |
338 | /* Storage degradation */ | |
339 | s390_handle_damage("received storage degradation machine " | |
340 | "check."); | |
77fa2245 HC |
341 | if (mci->cp) { |
342 | /* Channel report word pending */ | |
343 | mcck->channel_report = 1; | |
d3a73acb | 344 | set_cpu_flag(CIF_MCCK_PENDING); |
77fa2245 | 345 | } |
77fa2245 HC |
346 | if (mci->w) { |
347 | /* Warning pending */ | |
348 | mcck->warning = 1; | |
d3a73acb | 349 | set_cpu_flag(CIF_MCCK_PENDING); |
77fa2245 | 350 | } |
81f64b87 | 351 | nmi_exit(); |
1da177e4 LT |
352 | } |
353 | ||
f5daba1d | 354 | static int __init machine_check_init(void) |
1da177e4 | 355 | { |
d54853ef | 356 | ctl_set_bit(14, 25); /* enable external damage MCH */ |
f5daba1d | 357 | ctl_set_bit(14, 27); /* enable system recovery MCH */ |
1da177e4 | 358 | ctl_set_bit(14, 24); /* enable warning MCH */ |
1da177e4 LT |
359 | return 0; |
360 | } | |
1da177e4 | 361 | arch_initcall(machine_check_init); |