Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
a53c8fab | 2 | * Copyright IBM Corp. 2004, 2011 |
d7b250e2 HC |
3 | * Author(s): Martin Schwidefsky <schwidefsky@de.ibm.com>, |
4 | * Holger Smolinski <Holger.Smolinski@de.ibm.com>, | |
5 | * Thomas Spatzier <tspat@de.ibm.com>, | |
1da177e4 LT |
6 | * |
7 | * This file contains interrupt related functions. | |
8 | */ | |
9 | ||
1da177e4 LT |
10 | #include <linux/kernel_stat.h> |
11 | #include <linux/interrupt.h> | |
12 | #include <linux/seq_file.h> | |
55dff522 HC |
13 | #include <linux/proc_fs.h> |
14 | #include <linux/profile.h> | |
d7b250e2 HC |
15 | #include <linux/module.h> |
16 | #include <linux/kernel.h> | |
17 | #include <linux/ftrace.h> | |
18 | #include <linux/errno.h> | |
19 | #include <linux/slab.h> | |
20 | #include <linux/cpu.h> | |
21 | #include <asm/irq_regs.h> | |
22 | #include <asm/cputime.h> | |
23 | #include <asm/lowcore.h> | |
24 | #include <asm/irq.h> | |
1f44a225 | 25 | #include <asm/hw_irq.h> |
d7b250e2 | 26 | #include "entry.h" |
1da177e4 | 27 | |
420f42ec HC |
28 | DEFINE_PER_CPU_SHARED_ALIGNED(struct irq_stat, irq_stat); |
29 | EXPORT_PER_CPU_SYMBOL_GPL(irq_stat); | |
30 | ||
052ff461 HC |
31 | struct irq_class { |
32 | char *name; | |
33 | char *desc; | |
34 | }; | |
35 | ||
420f42ec | 36 | /* |
cf2fbdd2 | 37 | * The list of "main" irq classes on s390. This is the list of interrupts |
420f42ec HC |
38 | * that appear both in /proc/stat ("intr" line) and /proc/interrupts. |
39 | * Historically only external and I/O interrupts have been part of /proc/stat. | |
40 | * We can't add the split external and I/O sub classes since the first field | |
41 | * in the "intr" line in /proc/stat is supposed to be the sum of all other | |
42 | * fields. | |
43 | * Since the external and I/O interrupt fields are already sums we would end | |
44 | * up with having a sum which accounts each interrupt twice. | |
45 | */ | |
1f44a225 MS |
46 | static const struct irq_class irqclass_main_desc[NR_IRQS_BASE] = { |
47 | [EXT_INTERRUPT] = {.name = "EXT"}, | |
48 | [IO_INTERRUPT] = {.name = "I/O"}, | |
49 | [THIN_INTERRUPT] = {.name = "AIO"}, | |
420f42ec HC |
50 | }; |
51 | ||
52 | /* | |
53 | * The list of split external and I/O interrupts that appear only in | |
54 | * /proc/interrupts. | |
55 | * In addition this list contains non external / I/O events like NMIs. | |
56 | */ | |
57 | static const struct irq_class irqclass_sub_desc[NR_ARCH_IRQS] = { | |
58 | [IRQEXT_CLK] = {.name = "CLK", .desc = "[EXT] Clock Comparator"}, | |
59 | [IRQEXT_EXC] = {.name = "EXC", .desc = "[EXT] External Call"}, | |
60 | [IRQEXT_EMS] = {.name = "EMS", .desc = "[EXT] Emergency Signal"}, | |
61 | [IRQEXT_TMR] = {.name = "TMR", .desc = "[EXT] CPU Timer"}, | |
62 | [IRQEXT_TLA] = {.name = "TAL", .desc = "[EXT] Timing Alert"}, | |
63 | [IRQEXT_PFL] = {.name = "PFL", .desc = "[EXT] Pseudo Page Fault"}, | |
64 | [IRQEXT_DSD] = {.name = "DSD", .desc = "[EXT] DASD Diag"}, | |
65 | [IRQEXT_VRT] = {.name = "VRT", .desc = "[EXT] Virtio"}, | |
66 | [IRQEXT_SCP] = {.name = "SCP", .desc = "[EXT] Service Call"}, | |
67 | [IRQEXT_IUC] = {.name = "IUC", .desc = "[EXT] IUCV"}, | |
68 | [IRQEXT_CMS] = {.name = "CMS", .desc = "[EXT] CPU-Measurement: Sampling"}, | |
69 | [IRQEXT_CMC] = {.name = "CMC", .desc = "[EXT] CPU-Measurement: Counter"}, | |
70 | [IRQEXT_CMR] = {.name = "CMR", .desc = "[EXT] CPU-Measurement: RI"}, | |
71 | [IRQIO_CIO] = {.name = "CIO", .desc = "[I/O] Common I/O Layer Interrupt"}, | |
72 | [IRQIO_QAI] = {.name = "QAI", .desc = "[I/O] QDIO Adapter Interrupt"}, | |
73 | [IRQIO_DAS] = {.name = "DAS", .desc = "[I/O] DASD"}, | |
74 | [IRQIO_C15] = {.name = "C15", .desc = "[I/O] 3215"}, | |
75 | [IRQIO_C70] = {.name = "C70", .desc = "[I/O] 3270"}, | |
76 | [IRQIO_TAP] = {.name = "TAP", .desc = "[I/O] Tape"}, | |
77 | [IRQIO_VMR] = {.name = "VMR", .desc = "[I/O] Unit Record Devices"}, | |
78 | [IRQIO_LCS] = {.name = "LCS", .desc = "[I/O] LCS"}, | |
79 | [IRQIO_CLW] = {.name = "CLW", .desc = "[I/O] CLAW"}, | |
80 | [IRQIO_CTC] = {.name = "CTC", .desc = "[I/O] CTC"}, | |
81 | [IRQIO_APB] = {.name = "APB", .desc = "[I/O] AP Bus"}, | |
82 | [IRQIO_ADM] = {.name = "ADM", .desc = "[I/O] EADM Subchannel"}, | |
83 | [IRQIO_CSC] = {.name = "CSC", .desc = "[I/O] CHSC Subchannel"}, | |
84 | [IRQIO_PCI] = {.name = "PCI", .desc = "[I/O] PCI Interrupt" }, | |
85 | [IRQIO_MSI] = {.name = "MSI", .desc = "[I/O] MSI Interrupt" }, | |
89f88337 | 86 | [IRQIO_VIR] = {.name = "VIR", .desc = "[I/O] Virtual I/O Devices"}, |
708c39db | 87 | [NMI_NMI] = {.name = "NMI", .desc = "[NMI] Machine Check"}, |
93f3b2ee | 88 | [CPU_RST] = {.name = "RST", .desc = "[CPU] CPU Restart"}, |
052ff461 HC |
89 | }; |
90 | ||
1f44a225 MS |
91 | void __init init_IRQ(void) |
92 | { | |
93 | irq_reserve_irqs(0, THIN_INTERRUPT); | |
94 | init_cio_interrupts(); | |
95 | init_airq_interrupts(); | |
96 | init_ext_interrupts(); | |
97 | } | |
98 | ||
99 | void do_IRQ(struct pt_regs *regs, int irq) | |
100 | { | |
101 | struct pt_regs *old_regs; | |
102 | ||
103 | old_regs = set_irq_regs(regs); | |
104 | irq_enter(); | |
105 | if (S390_lowcore.int_clock >= S390_lowcore.clock_comparator) | |
106 | /* Serve timer interrupts first. */ | |
107 | clock_comparator_work(); | |
108 | generic_handle_irq(irq); | |
109 | irq_exit(); | |
110 | set_irq_regs(old_regs); | |
111 | } | |
112 | ||
1da177e4 LT |
113 | /* |
114 | * show_interrupts is needed by /proc/interrupts. | |
115 | */ | |
116 | int show_interrupts(struct seq_file *p, void *v) | |
117 | { | |
420f42ec HC |
118 | int irq = *(loff_t *) v; |
119 | int cpu; | |
1da177e4 | 120 | |
8dd79cb1 | 121 | get_online_cpus(); |
420f42ec | 122 | if (irq == 0) { |
1da177e4 | 123 | seq_puts(p, " "); |
420f42ec HC |
124 | for_each_online_cpu(cpu) |
125 | seq_printf(p, "CPU%d ", cpu); | |
1da177e4 | 126 | seq_putc(p, '\n'); |
1f44a225 | 127 | goto out; |
1da177e4 | 128 | } |
420f42ec | 129 | if (irq < NR_IRQS) { |
1f44a225 MS |
130 | if (irq >= NR_IRQS_BASE) |
131 | goto out; | |
420f42ec HC |
132 | seq_printf(p, "%s: ", irqclass_main_desc[irq].name); |
133 | for_each_online_cpu(cpu) | |
1f44a225 | 134 | seq_printf(p, "%10u ", kstat_irqs_cpu(irq, cpu)); |
420f42ec | 135 | seq_putc(p, '\n'); |
1f44a225 | 136 | goto out; |
420f42ec HC |
137 | } |
138 | for (irq = 0; irq < NR_ARCH_IRQS; irq++) { | |
139 | seq_printf(p, "%s: ", irqclass_sub_desc[irq].name); | |
140 | for_each_online_cpu(cpu) | |
1f44a225 MS |
141 | seq_printf(p, "%10u ", |
142 | per_cpu(irq_stat, cpu).irqs[irq]); | |
420f42ec HC |
143 | if (irqclass_sub_desc[irq].desc) |
144 | seq_printf(p, " %s", irqclass_sub_desc[irq].desc); | |
145 | seq_putc(p, '\n'); | |
146 | } | |
1f44a225 | 147 | out: |
8dd79cb1 | 148 | put_online_cpus(); |
420f42ec | 149 | return 0; |
1da177e4 LT |
150 | } |
151 | ||
1f44a225 MS |
152 | int arch_show_interrupts(struct seq_file *p, int prec) |
153 | { | |
154 | return 0; | |
155 | } | |
156 | ||
1da177e4 LT |
157 | /* |
158 | * Switch to the asynchronous interrupt stack for softirq execution. | |
159 | */ | |
7d65f4a6 | 160 | void do_softirq_own_stack(void) |
1da177e4 | 161 | { |
7d65f4a6 FW |
162 | unsigned long old, new; |
163 | ||
164 | /* Get current stack pointer. */ | |
165 | asm volatile("la %0,0(15)" : "=a" (old)); | |
166 | /* Check against async. stack address range. */ | |
167 | new = S390_lowcore.async_stack; | |
168 | if (((new - old) >> (PAGE_SHIFT + THREAD_ORDER)) != 0) { | |
169 | /* Need to switch to the async. stack. */ | |
170 | new -= STACK_FRAME_OVERHEAD; | |
171 | ((struct stack_frame *) new)->back_chain = old; | |
172 | asm volatile(" la 15,0(%0)\n" | |
173 | " basr 14,%2\n" | |
174 | " la 15,0(%1)\n" | |
175 | : : "a" (new), "a" (old), | |
176 | "a" (__do_softirq) | |
177 | : "0", "1", "2", "3", "4", "5", "14", | |
178 | "cc", "memory" ); | |
179 | } else { | |
180 | /* We are already on the async stack. */ | |
181 | __do_softirq(); | |
1da177e4 | 182 | } |
1da177e4 | 183 | } |
55dff522 | 184 | |
d7b250e2 | 185 | /* |
89c9b66b JG |
186 | * ext_int_hash[index] is the list head for all external interrupts that hash |
187 | * to this index. | |
d7b250e2 | 188 | */ |
9e75c627 | 189 | static struct hlist_head ext_int_hash[32] ____cacheline_aligned; |
d7b250e2 HC |
190 | |
191 | struct ext_int_info { | |
d7b250e2 | 192 | ext_int_handler_t handler; |
50ce749d | 193 | struct hlist_node entry; |
89c9b66b | 194 | struct rcu_head rcu; |
50ce749d | 195 | u16 code; |
d7b250e2 HC |
196 | }; |
197 | ||
89c9b66b | 198 | /* ext_int_hash_lock protects the handler lists for external interrupts */ |
63df41d6 | 199 | static DEFINE_SPINLOCK(ext_int_hash_lock); |
89c9b66b | 200 | |
d7b250e2 HC |
201 | static inline int ext_hash(u16 code) |
202 | { | |
9e75c627 HC |
203 | BUILD_BUG_ON(!is_power_of_2(ARRAY_SIZE(ext_int_hash))); |
204 | ||
205 | return (code + (code >> 9)) & (ARRAY_SIZE(ext_int_hash) - 1); | |
d7b250e2 HC |
206 | } |
207 | ||
208 | int register_external_interrupt(u16 code, ext_int_handler_t handler) | |
209 | { | |
210 | struct ext_int_info *p; | |
89c9b66b | 211 | unsigned long flags; |
d7b250e2 HC |
212 | int index; |
213 | ||
214 | p = kmalloc(sizeof(*p), GFP_ATOMIC); | |
215 | if (!p) | |
216 | return -ENOMEM; | |
217 | p->code = code; | |
218 | p->handler = handler; | |
219 | index = ext_hash(code); | |
89c9b66b JG |
220 | |
221 | spin_lock_irqsave(&ext_int_hash_lock, flags); | |
50ce749d | 222 | hlist_add_head_rcu(&p->entry, &ext_int_hash[index]); |
89c9b66b | 223 | spin_unlock_irqrestore(&ext_int_hash_lock, flags); |
d7b250e2 HC |
224 | return 0; |
225 | } | |
226 | EXPORT_SYMBOL(register_external_interrupt); | |
227 | ||
228 | int unregister_external_interrupt(u16 code, ext_int_handler_t handler) | |
229 | { | |
89c9b66b JG |
230 | struct ext_int_info *p; |
231 | unsigned long flags; | |
232 | int index = ext_hash(code); | |
d7b250e2 | 233 | |
89c9b66b | 234 | spin_lock_irqsave(&ext_int_hash_lock, flags); |
50ce749d | 235 | hlist_for_each_entry_rcu(p, &ext_int_hash[index], entry) { |
89c9b66b | 236 | if (p->code == code && p->handler == handler) { |
50ce749d | 237 | hlist_del_rcu(&p->entry); |
bc399d6e | 238 | kfree_rcu(p, rcu); |
89c9b66b | 239 | } |
7968ca81 | 240 | } |
89c9b66b | 241 | spin_unlock_irqrestore(&ext_int_hash_lock, flags); |
d7b250e2 HC |
242 | return 0; |
243 | } | |
244 | EXPORT_SYMBOL(unregister_external_interrupt); | |
245 | ||
1f44a225 | 246 | static irqreturn_t do_ext_interrupt(int irq, void *dummy) |
d7b250e2 | 247 | { |
1f44a225 | 248 | struct pt_regs *regs = get_irq_regs(); |
48f6b00c | 249 | struct ext_code ext_code; |
d7b250e2 HC |
250 | struct ext_int_info *p; |
251 | int index; | |
252 | ||
48f6b00c | 253 | ext_code = *(struct ext_code *) ®s->int_code; |
fde15c3a | 254 | if (ext_code.code != 0x1004) |
d7b250e2 | 255 | __get_cpu_var(s390_idle).nohz_delay = 1; |
89c9b66b | 256 | |
fde15c3a | 257 | index = ext_hash(ext_code.code); |
89c9b66b | 258 | rcu_read_lock(); |
50ce749d HC |
259 | hlist_for_each_entry_rcu(p, &ext_int_hash[index], entry) { |
260 | if (unlikely(p->code != ext_code.code)) | |
261 | continue; | |
262 | p->handler(ext_code, regs->int_parm, regs->int_parm_long); | |
263 | } | |
89c9b66b | 264 | rcu_read_unlock(); |
1f44a225 | 265 | return IRQ_HANDLED; |
d7b250e2 HC |
266 | } |
267 | ||
1f44a225 MS |
268 | static struct irqaction external_interrupt = { |
269 | .name = "EXT", | |
270 | .handler = do_ext_interrupt, | |
271 | }; | |
272 | ||
273 | void __init init_ext_interrupts(void) | |
89c9b66b | 274 | { |
1f44a225 MS |
275 | int idx; |
276 | ||
277 | for (idx = 0; idx < ARRAY_SIZE(ext_int_hash); idx++) | |
50ce749d | 278 | INIT_HLIST_HEAD(&ext_int_hash[idx]); |
1f44a225 MS |
279 | |
280 | irq_set_chip_and_handler(EXT_INTERRUPT, | |
281 | &dummy_irq_chip, handle_percpu_irq); | |
282 | setup_irq(EXT_INTERRUPT, &external_interrupt); | |
89c9b66b JG |
283 | } |
284 | ||
82003c3e HC |
285 | static DEFINE_SPINLOCK(irq_subclass_lock); |
286 | static unsigned char irq_subclass_refcount[64]; | |
d7b250e2 | 287 | |
82003c3e | 288 | void irq_subclass_register(enum irq_subclass subclass) |
d7b250e2 | 289 | { |
82003c3e HC |
290 | spin_lock(&irq_subclass_lock); |
291 | if (!irq_subclass_refcount[subclass]) | |
292 | ctl_set_bit(0, subclass); | |
293 | irq_subclass_refcount[subclass]++; | |
294 | spin_unlock(&irq_subclass_lock); | |
d7b250e2 | 295 | } |
82003c3e | 296 | EXPORT_SYMBOL(irq_subclass_register); |
d7b250e2 | 297 | |
82003c3e | 298 | void irq_subclass_unregister(enum irq_subclass subclass) |
d7b250e2 | 299 | { |
82003c3e HC |
300 | spin_lock(&irq_subclass_lock); |
301 | irq_subclass_refcount[subclass]--; | |
302 | if (!irq_subclass_refcount[subclass]) | |
303 | ctl_clear_bit(0, subclass); | |
304 | spin_unlock(&irq_subclass_lock); | |
d7b250e2 | 305 | } |
82003c3e | 306 | EXPORT_SYMBOL(irq_subclass_unregister); |