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ab14de6c HC |
1 | /* |
2 | * arch/s390/kernel/base.S | |
3 | * | |
a53c8fab | 4 | * Copyright IBM Corp. 2006, 2007 |
ab14de6c HC |
5 | * Author(s): Heiko Carstens <heiko.carstens@de.ibm.com> |
6 | * Michael Holzheu <holzheu@de.ibm.com> | |
7 | */ | |
8 | ||
144d634a | 9 | #include <linux/linkage.h> |
cbb870c8 | 10 | #include <asm/asm-offsets.h> |
ab14de6c | 11 | #include <asm/ptrace.h> |
eb546195 | 12 | #include <asm/sigp.h> |
ab14de6c | 13 | |
144d634a | 14 | ENTRY(s390_base_mcck_handler) |
ab14de6c HC |
15 | basr %r13,0 |
16 | 0: lg %r15,__LC_PANIC_STACK # load panic stack | |
17 | aghi %r15,-STACK_FRAME_OVERHEAD | |
18 | larl %r1,s390_base_mcck_handler_fn | |
19 | lg %r1,0(%r1) | |
20 | ltgr %r1,%r1 | |
21 | jz 1f | |
22 | basr %r14,%r1 | |
23 | 1: la %r1,4095 | |
24 | lmg %r0,%r15,__LC_GPREGS_SAVE_AREA-4095(%r1) | |
25 | lpswe __LC_MCK_OLD_PSW | |
26 | ||
27 | .section .bss | |
144d634a | 28 | .align 8 |
ab14de6c HC |
29 | .globl s390_base_mcck_handler_fn |
30 | s390_base_mcck_handler_fn: | |
31 | .quad 0 | |
32 | .previous | |
33 | ||
144d634a | 34 | ENTRY(s390_base_ext_handler) |
c5328901 | 35 | stmg %r0,%r15,__LC_SAVE_AREA_ASYNC |
ab14de6c HC |
36 | basr %r13,0 |
37 | 0: aghi %r15,-STACK_FRAME_OVERHEAD | |
38 | larl %r1,s390_base_ext_handler_fn | |
39 | lg %r1,0(%r1) | |
40 | ltgr %r1,%r1 | |
41 | jz 1f | |
42 | basr %r14,%r1 | |
c5328901 | 43 | 1: lmg %r0,%r15,__LC_SAVE_AREA_ASYNC |
ab14de6c HC |
44 | ni __LC_EXT_OLD_PSW+1,0xfd # clear wait state bit |
45 | lpswe __LC_EXT_OLD_PSW | |
46 | ||
47 | .section .bss | |
144d634a | 48 | .align 8 |
ab14de6c HC |
49 | .globl s390_base_ext_handler_fn |
50 | s390_base_ext_handler_fn: | |
51 | .quad 0 | |
52 | .previous | |
53 | ||
144d634a | 54 | ENTRY(s390_base_pgm_handler) |
c5328901 | 55 | stmg %r0,%r15,__LC_SAVE_AREA_SYNC |
ab14de6c HC |
56 | basr %r13,0 |
57 | 0: aghi %r15,-STACK_FRAME_OVERHEAD | |
58 | larl %r1,s390_base_pgm_handler_fn | |
59 | lg %r1,0(%r1) | |
60 | ltgr %r1,%r1 | |
61 | jz 1f | |
62 | basr %r14,%r1 | |
c5328901 | 63 | lmg %r0,%r15,__LC_SAVE_AREA_SYNC |
ab14de6c HC |
64 | lpswe __LC_PGM_OLD_PSW |
65 | 1: lpswe disabled_wait_psw-0b(%r13) | |
66 | ||
67 | .align 8 | |
68 | disabled_wait_psw: | |
69 | .quad 0x0002000180000000,0x0000000000000000 + s390_base_pgm_handler | |
70 | ||
71 | .section .bss | |
144d634a | 72 | .align 8 |
ab14de6c HC |
73 | .globl s390_base_pgm_handler_fn |
74 | s390_base_pgm_handler_fn: | |
75 | .quad 0 | |
76 | .previous | |
77 | ||
9dc7356e MH |
78 | # |
79 | # Calls diag 308 subcode 1 and continues execution | |
80 | # | |
9dc7356e MH |
81 | ENTRY(diag308_reset) |
82 | larl %r4,.Lctlregs # Save control registers | |
83 | stctg %c0,%c15,0(%r4) | |
1592a8e4 MH |
84 | lg %r2,0(%r4) # Disable lowcore protection |
85 | nilh %r2,0xefff | |
86 | larl %r4,.Lctlreg0 | |
87 | stg %r2,0(%r4) | |
88 | lctlg %c0,%c0,0(%r4) | |
60a0c68d MH |
89 | larl %r4,.Lfpctl # Floating point control register |
90 | stfpc 0(%r4) | |
1592a8e4 MH |
91 | larl %r4,.Lprefix # Save prefix register |
92 | stpx 0(%r4) | |
93 | larl %r4,.Lprefix_zero # Set prefix register to 0 | |
94 | spx 0(%r4) | |
fa7c0043 MH |
95 | larl %r4,.Lcontinue_psw # Save PSW flags |
96 | epsw %r2,%r3 | |
97 | stm %r2,%r3,0(%r4) | |
9dc7356e MH |
98 | larl %r4,.Lrestart_psw # Setup restart PSW at absolute 0 |
99 | lghi %r3,0 | |
100 | lg %r4,0(%r4) # Save PSW | |
101 | sturg %r4,%r3 # Use sturg, because of large pages | |
102 | lghi %r1,1 | |
10ad34bc MS |
103 | lghi %r0,0 |
104 | diag %r0,%r1,0x308 | |
9dc7356e MH |
105 | .Lrestart_part2: |
106 | lhi %r0,0 # Load r0 with zero | |
107 | lhi %r1,2 # Use mode 2 = ESAME (dump) | |
eb546195 | 108 | sigp %r1,%r0,SIGP_SET_ARCHITECTURE # Switch to ESAME mode |
9dc7356e MH |
109 | sam64 # Switch to 64 bit addressing mode |
110 | larl %r4,.Lctlregs # Restore control registers | |
111 | lctlg %c0,%c15,0(%r4) | |
60a0c68d MH |
112 | larl %r4,.Lfpctl # Restore floating point ctl register |
113 | lfpc 0(%r4) | |
1592a8e4 MH |
114 | larl %r4,.Lprefix # Restore prefix register |
115 | spx 0(%r4) | |
fa7c0043 MH |
116 | larl %r4,.Lcontinue_psw # Restore PSW flags |
117 | lpswe 0(%r4) | |
118 | .Lcontinue: | |
9dc7356e MH |
119 | br %r14 |
120 | .align 16 | |
121 | .Lrestart_psw: | |
122 | .long 0x00080000,0x80000000 + .Lrestart_part2 | |
123 | ||
fa7c0043 MH |
124 | .section .data..nosave,"aw",@progbits |
125 | .align 8 | |
126 | .Lcontinue_psw: | |
127 | .quad 0,.Lcontinue | |
128 | .previous | |
129 | ||
9dc7356e MH |
130 | .section .bss |
131 | .align 8 | |
1592a8e4 MH |
132 | .Lctlreg0: |
133 | .quad 0 | |
9dc7356e MH |
134 | .Lctlregs: |
135 | .rept 16 | |
136 | .quad 0 | |
137 | .endr | |
60a0c68d MH |
138 | .Lfpctl: |
139 | .long 0 | |
1592a8e4 MH |
140 | .Lprefix: |
141 | .long 0 | |
142 | .Lprefix_zero: | |
143 | .long 0 | |
9dc7356e | 144 | .previous |