[linux-2.6-block.git] / arch / s390 / include / asm / processor.h

/*
 *  include/asm-s390/processor.h
 *
 *  S390 version
 *    Copyright (C) 1999 IBM Deutschland Entwicklung GmbH, IBM Corporation
 *    Author(s): Hartmut Penner (hp@de.ibm.com),
 *               Martin Schwidefsky (schwidefsky@de.ibm.com)
 *
 *  Derived from "include/asm-i386/processor.h"
 *    Copyright (C) 1994, Linus Torvalds
 */

#ifndef __ASM_S390_PROCESSOR_H
#define __ASM_S390_PROCESSOR_H

#include <linux/linkage.h>
#include <linux/irqflags.h>
#include <asm/cpu.h>
#include <asm/page.h>
#include <asm/ptrace.h>
#include <asm/setup.h>

#ifdef __KERNEL__
/*
 * Default implementation of macro that returns current
 * instruction pointer ("program counter").
 */
#define current_text_addr() ({ void *pc; asm("basr %0,0" : "=a" (pc)); pc; })

static inline void get_cpu_id(struct cpuid *ptr)
{
	asm volatile("stidp %0" : "=Q" (*ptr));
}

extern void s390_adjust_jiffies(void);
extern int get_cpu_capability(unsigned int *);
extern const struct seq_operations cpuinfo_op;
extern int sysctl_ieee_emulation_warnings;

/*
 * User space process size: 2GB for 31 bit, 4TB or 8PT for 64 bit.
 */
#ifndef __s390x__

#define TASK_SIZE		(1UL << 31)
#define TASK_UNMAPPED_BASE	(1UL << 30)

#else /* __s390x__ */

#define TASK_SIZE_OF(tsk)	((tsk)->mm->context.asce_limit)
#define TASK_UNMAPPED_BASE	(test_thread_flag(TIF_31BIT) ? \
					(1UL << 30) : (1UL << 41))
#define TASK_SIZE		TASK_SIZE_OF(current)

#endif /* __s390x__ */

#ifdef __KERNEL__

#ifndef __s390x__
#define STACK_TOP		(1UL << 31)
#define STACK_TOP_MAX		(1UL << 31)
#else /* __s390x__ */
#define STACK_TOP		(1UL << (test_thread_flag(TIF_31BIT) ? 31:42))
#define STACK_TOP_MAX		(1UL << 42)
#endif /* __s390x__ */


#endif

#define HAVE_ARCH_PICK_MMAP_LAYOUT

typedef struct {
        __u32 ar4;
} mm_segment_t;

/*
 * Thread structure
 */
struct thread_struct {
	s390_fp_regs fp_regs;
	unsigned int  acrs[NUM_ACRS];
        unsigned long ksp;              /* kernel stack pointer             */
	mm_segment_t mm_segment;
	unsigned long gmap_addr;	/* address of last gmap fault. */
	struct per_regs per_user;	/* User specified PER registers */
	struct per_event per_event;	/* Cause of the last PER trap */
        /* pfault_wait is used to block the process on a pfault event */
	unsigned long pfault_wait;
	struct list_head list;
};

typedef struct thread_struct thread_struct;

/*
 * Stack layout of a C stack frame.
 */
#ifndef __PACK_STACK
struct stack_frame {
	unsigned long back_chain;
	unsigned long empty1[5];
	unsigned long gprs[10];
	unsigned int  empty2[8];
};
#else
struct stack_frame {
	unsigned long empty1[5];
	unsigned int  empty2[8];
	unsigned long gprs[10];
	unsigned long back_chain;
};
#endif

#define ARCH_MIN_TASKALIGN	8

#define INIT_THREAD {							\
	.ksp = sizeof(init_stack) + (unsigned long) &init_stack,	\
}

/*
 * Do necessary setup to start up a new thread.
 */
#define start_thread(regs, new_psw, new_stackp) do {			\
	regs->psw.mask	= psw_user_bits | PSW_MASK_EA | PSW_MASK_BA;	\
	regs->psw.addr	= new_psw | PSW_ADDR_AMODE;			\
	regs->gprs[15]	= new_stackp;					\
} while (0)

#define start_thread31(regs, new_psw, new_stackp) do {			\
	regs->psw.mask	= psw_user_bits | PSW_MASK_BA;			\
	regs->psw.addr	= new_psw | PSW_ADDR_AMODE;			\
	regs->gprs[15]	= new_stackp;					\
	crst_table_downgrade(current->mm, 1UL << 31);			\
} while (0)

/* Forward declaration, a strange C thing */
struct task_struct;
struct mm_struct;
struct seq_file;

/* Free all resources held by a thread. */
extern void release_thread(struct task_struct *);
extern int kernel_thread(int (*fn)(void *), void * arg, unsigned long flags);

/*
 * Return saved PC of a blocked thread.
 */
extern unsigned long thread_saved_pc(struct task_struct *t);

extern void show_code(struct pt_regs *regs);

unsigned long get_wchan(struct task_struct *p);
#define task_pt_regs(tsk) ((struct pt_regs *) \
        (task_stack_page(tsk) + THREAD_SIZE) - 1)
#define KSTK_EIP(tsk)	(task_pt_regs(tsk)->psw.addr)
#define KSTK_ESP(tsk)	(task_pt_regs(tsk)->gprs[15])

static inline unsigned short stap(void)
{
	unsigned short cpu_address;

	asm volatile("stap %0" : "=m" (cpu_address));
	return cpu_address;
}

/*
 * Give up the time slice of the virtual PU.
 */
static inline void cpu_relax(void)
{
	if (MACHINE_HAS_DIAG44)
		asm volatile("diag 0,0,68");
	barrier();
}

static inline void psw_set_key(unsigned int key)
{
	asm volatile("spka 0(%0)" : : "d" (key));
}

/*
 * Set PSW to specified value.
 */
static inline void __load_psw(psw_t psw)
{
#ifndef __s390x__
	asm volatile("lpsw  %0" : : "Q" (psw) : "cc");
#else
	asm volatile("lpswe %0" : : "Q" (psw) : "cc");
#endif
}

/*
 * Set PSW mask to specified value, while leaving the
 * PSW addr pointing to the next instruction.
 */
static inline void __load_psw_mask (unsigned long mask)
{
	unsigned long addr;
	psw_t psw;

	psw.mask = mask;

#ifndef __s390x__
	asm volatile(
		"	basr	%0,0\n"
		"0:	ahi	%0,1f-0b\n"
		"	st	%0,%O1+4(%R1)\n"
		"	lpsw	%1\n"
		"1:"
		: "=&d" (addr), "=Q" (psw) : "Q" (psw) : "memory", "cc");
#else /* __s390x__ */
	asm volatile(
		"	larl	%0,1f\n"
		"	stg	%0,%O1+8(%R1)\n"
		"	lpswe	%1\n"
		"1:"
		: "=&d" (addr), "=Q" (psw) : "Q" (psw) : "memory", "cc");
#endif /* __s390x__ */
}

/*
 * Rewind PSW instruction address by specified number of bytes.
 */
static inline unsigned long __rewind_psw(psw_t psw, unsigned long ilc)
{
#ifndef __s390x__
	if (psw.addr & PSW_ADDR_AMODE)
		/* 31 bit mode */
		return (psw.addr - ilc) | PSW_ADDR_AMODE;
	/* 24 bit mode */
	return (psw.addr - ilc) & ((1UL << 24) - 1);
#else
	unsigned long mask;

	mask = (psw.mask & PSW_MASK_EA) ? -1UL :
	       (psw.mask & PSW_MASK_BA) ? (1UL << 31) - 1 :
					  (1UL << 24) - 1;
	return (psw.addr - ilc) & mask;
#endif
}
 
/*
 * Function to drop a processor into disabled wait state
 */
static inline void __noreturn disabled_wait(unsigned long code)
{
        unsigned long ctl_buf;
        psw_t dw_psw;

	dw_psw.mask = PSW_MASK_BASE | PSW_MASK_WAIT | PSW_MASK_BA | PSW_MASK_EA;
        dw_psw.addr = code;
        /* 
         * Store status and then load disabled wait psw,
         * the processor is dead afterwards
         */
#ifndef __s390x__
	asm volatile(
		"	stctl	0,0,0(%2)\n"
		"	ni	0(%2),0xef\n"	/* switch off protection */
		"	lctl	0,0,0(%2)\n"
		"	stpt	0xd8\n"		/* store timer */
		"	stckc	0xe0\n"		/* store clock comparator */
		"	stpx	0x108\n"	/* store prefix register */
		"	stam	0,15,0x120\n"	/* store access registers */
		"	std	0,0x160\n"	/* store f0 */
		"	std	2,0x168\n"	/* store f2 */
		"	std	4,0x170\n"	/* store f4 */
		"	std	6,0x178\n"	/* store f6 */
		"	stm	0,15,0x180\n"	/* store general registers */
		"	stctl	0,15,0x1c0\n"	/* store control registers */
		"	oi	0x1c0,0x10\n"	/* fake protection bit */
		"	lpsw	0(%1)"
		: "=m" (ctl_buf)
		: "a" (&dw_psw), "a" (&ctl_buf), "m" (dw_psw) : "cc");
#else /* __s390x__ */
	asm volatile(
		"	stctg	0,0,0(%2)\n"
		"	ni	4(%2),0xef\n"	/* switch off protection */
		"	lctlg	0,0,0(%2)\n"
		"	lghi	1,0x1000\n"
		"	stpt	0x328(1)\n"	/* store timer */
		"	stckc	0x330(1)\n"	/* store clock comparator */
		"	stpx	0x318(1)\n"	/* store prefix register */
		"	stam	0,15,0x340(1)\n"/* store access registers */
		"	stfpc	0x31c(1)\n"	/* store fpu control */
		"	std	0,0x200(1)\n"	/* store f0 */
		"	std	1,0x208(1)\n"	/* store f1 */
		"	std	2,0x210(1)\n"	/* store f2 */
		"	std	3,0x218(1)\n"	/* store f3 */
		"	std	4,0x220(1)\n"	/* store f4 */
		"	std	5,0x228(1)\n"	/* store f5 */
		"	std	6,0x230(1)\n"	/* store f6 */
		"	std	7,0x238(1)\n"	/* store f7 */
		"	std	8,0x240(1)\n"	/* store f8 */
		"	std	9,0x248(1)\n"	/* store f9 */
		"	std	10,0x250(1)\n"	/* store f10 */
		"	std	11,0x258(1)\n"	/* store f11 */
		"	std	12,0x260(1)\n"	/* store f12 */
		"	std	13,0x268(1)\n"	/* store f13 */
		"	std	14,0x270(1)\n"	/* store f14 */
		"	std	15,0x278(1)\n"	/* store f15 */
		"	stmg	0,15,0x280(1)\n"/* store general registers */
		"	stctg	0,15,0x380(1)\n"/* store control registers */
		"	oi	0x384(1),0x10\n"/* fake protection bit */
		"	lpswe	0(%1)"
		: "=m" (ctl_buf)
		: "a" (&dw_psw), "a" (&ctl_buf), "m" (dw_psw) : "cc", "0", "1");
#endif /* __s390x__ */
	while (1);
}

/*
 * Use to set psw mask except for the first byte which
 * won't be changed by this function.
 */
static inline void
__set_psw_mask(unsigned long mask)
{
	__load_psw_mask(mask | (arch_local_save_flags() & ~(-1UL >> 8)));
}

#define local_mcck_enable() \
	__set_psw_mask(psw_kernel_bits | PSW_MASK_DAT | PSW_MASK_MCHECK)
#define local_mcck_disable() \
	__set_psw_mask(psw_kernel_bits | PSW_MASK_DAT)

/*
 * Basic Machine Check/Program Check Handler.
 */

extern void s390_base_mcck_handler(void);
extern void s390_base_pgm_handler(void);
extern void s390_base_ext_handler(void);

extern void (*s390_base_mcck_handler_fn)(void);
extern void (*s390_base_pgm_handler_fn)(void);
extern void (*s390_base_ext_handler_fn)(void);

#define ARCH_LOW_ADDRESS_LIMIT	0x7fffffffUL

#endif

/*
 * Helper macro for exception table entries
 */
#ifndef __s390x__
#define EX_TABLE(_fault,_target)			\
	".section __ex_table,\"a\"\n"			\
	"	.align 4\n"				\
	"	.long  " #_fault "," #_target "\n"	\
	".previous\n"
#else
#define EX_TABLE(_fault,_target)			\
	".section __ex_table,\"a\"\n"			\
	"	.align 8\n"				\
	"	.quad  " #_fault "," #_target "\n"	\
	".previous\n"
#endif

#endif                                 /* __ASM_S390_PROCESSOR_H           */
Commit	Line	Data
1da177e4 LT	1	/*
	2	* include/asm-s390/processor.h
	3	*
	4	* S390 version
	5	* Copyright (C) 1999 IBM Deutschland Entwicklung GmbH, IBM Corporation
	6	* Author(s): Hartmut Penner (hp@de.ibm.com),
	7	* Martin Schwidefsky (schwidefsky@de.ibm.com)
	8	*
	9	* Derived from "include/asm-i386/processor.h"
	10	* Copyright (C) 1994, Linus Torvalds
	11	*/
	12
	13	#ifndef __ASM_S390_PROCESSOR_H
	14	#define __ASM_S390_PROCESSOR_H
	15
edd53787	16	#include <linux/linkage.h>
a0616cde	17	#include <linux/irqflags.h>
e86a6ed6	18	#include <asm/cpu.h>
25097bf1	19	#include <asm/page.h>
1da177e4	20	#include <asm/ptrace.h>
25097bf1	21	#include <asm/setup.h>
1da177e4 LT	22
	23	#ifdef __KERNEL__
	24	/*
	25	* Default implementation of macro that returns current
	26	* instruction pointer ("program counter").
	27	*/
94c12cc7	28	#define current_text_addr() ({ void *pc; asm("basr %0,0" : "=a" (pc)); pc; })
1da177e4	29
e86a6ed6	30	static inline void get_cpu_id(struct cpuid *ptr)
72960a02	31	{
987bcdac	32	asm volatile("stidp %0" : "=Q" (*ptr));
72960a02 MH	33	}
72960a02 MH	34
31ee4b2f	35	extern void s390_adjust_jiffies(void);
2fc2d1e9	36	extern int get_cpu_capability(unsigned int *);
638ad34a MS	37	extern const struct seq_operations cpuinfo_op;
638ad34a MS	38	extern int sysctl_ieee_emulation_warnings;
1da177e4	39
1da177e4	40	/*
f481bfaf	41	* User space process size: 2GB for 31 bit, 4TB or 8PT for 64 bit.
1da177e4 LT	42	*/
	43	#ifndef __s390x__
	44
5a216a20 MS	45	#define TASK_SIZE (1UL << 31)
5a216a20 MS	46	#define TASK_UNMAPPED_BASE (1UL << 30)
1da177e4 LT	47
	48	#else /* __s390x__ */
	49
f481bfaf	50	#define TASK_SIZE_OF(tsk) ((tsk)->mm->context.asce_limit)
5a216a20 MS	51	#define TASK_UNMAPPED_BASE (test_thread_flag(TIF_31BIT) ? \
	52	(1UL << 30) : (1UL << 41))
	53	#define TASK_SIZE TASK_SIZE_OF(current)
1da177e4 LT	54
	55	#endif /* __s390x__ */
	56
922a70d3 DH	57	#ifdef __KERNEL__
922a70d3 DH	58
5a216a20 MS	59	#ifndef __s390x__
5a216a20 MS	60	#define STACK_TOP (1UL << 31)
6252d702	61	#define STACK_TOP_MAX (1UL << 31)
5a216a20	62	#else /* __s390x__ */
6252d702 MS	63	#define STACK_TOP (1UL << (test_thread_flag(TIF_31BIT) ? 31:42))
6252d702 MS	64	#define STACK_TOP_MAX (1UL << 42)
5a216a20 MS	65	#endif /* __s390x__ */
5a216a20 MS	66
922a70d3 DH	67
	68	#endif
	69
1da177e4 LT	70	#define HAVE_ARCH_PICK_MMAP_LAYOUT
	71
	72	typedef struct {
	73	__u32 ar4;
	74	} mm_segment_t;
	75
	76	/*
	77	* Thread structure
	78	*/
	79	struct thread_struct {
	80	s390_fp_regs fp_regs;
	81	unsigned int acrs[NUM_ACRS];
	82	unsigned long ksp; /* kernel stack pointer */
1da177e4	83	mm_segment_t mm_segment;
e5992f2e	84	unsigned long gmap_addr; /* address of last gmap fault. */
5e9a2692 MS	85	struct per_regs per_user; /* User specified PER registers */
5e9a2692 MS	86	struct per_event per_event; /* Cause of the last PER trap */
1da177e4 LT	87	/* pfault_wait is used to block the process on a pfault event */
1da177e4 LT	88	unsigned long pfault_wait;
f2db2e6c	89	struct list_head list;
1da177e4 LT	90	};
	91
	92	typedef struct thread_struct thread_struct;
	93
	94	/*
	95	* Stack layout of a C stack frame.
	96	*/
	97	#ifndef __PACK_STACK
	98	struct stack_frame {
	99	unsigned long back_chain;
	100	unsigned long empty1[5];
	101	unsigned long gprs[10];
	102	unsigned int empty2[8];
	103	};
	104	#else
	105	struct stack_frame {
	106	unsigned long empty1[5];
	107	unsigned int empty2[8];
	108	unsigned long gprs[10];
	109	unsigned long back_chain;
	110	};
	111	#endif
	112
	113	#define ARCH_MIN_TASKALIGN 8
	114
6f3fa3f0 MS	115	#define INIT_THREAD { \
	116	.ksp = sizeof(init_stack) + (unsigned long) &init_stack, \
	117	}
1da177e4 LT	118
	119	/*
	120	* Do necessary setup to start up a new thread.
	121	*/
b50511e4 MS	122	#define start_thread(regs, new_psw, new_stackp) do { \
	123	regs->psw.mask = psw_user_bits \| PSW_MASK_EA \| PSW_MASK_BA; \
	124	regs->psw.addr = new_psw \| PSW_ADDR_AMODE; \
	125	regs->gprs[15] = new_stackp; \
63506c41 MS	126	} while (0)
63506c41 MS	127
b50511e4 MS	128	#define start_thread31(regs, new_psw, new_stackp) do { \
	129	regs->psw.mask = psw_user_bits \| PSW_MASK_BA; \
	130	regs->psw.addr = new_psw \| PSW_ADDR_AMODE; \
	131	regs->gprs[15] = new_stackp; \
	132	crst_table_downgrade(current->mm, 1UL << 31); \
1da177e4 LT	133	} while (0)
1da177e4 LT	134
1da177e4 LT	135	/* Forward declaration, a strange C thing */
	136	struct task_struct;
	137	struct mm_struct;
df5f8314	138	struct seq_file;
1da177e4 LT	139
	140	/* Free all resources held by a thread. */
	141	extern void release_thread(struct task_struct *);
	142	extern int kernel_thread(int (fn)(void ), void * arg, unsigned long flags);
	143
1da177e4 LT	144	/*
	145	* Return saved PC of a blocked thread.
	146	*/
	147	extern unsigned long thread_saved_pc(struct task_struct *t);
	148
bb11e3bd	149	extern void show_code(struct pt_regs *regs);
1da177e4 LT	150
1da177e4 LT	151	unsigned long get_wchan(struct task_struct *p);
c7584fb6	152	#define task_pt_regs(tsk) ((struct pt_regs *) \
30af7120	153	(task_stack_page(tsk) + THREAD_SIZE) - 1)
c7584fb6 AV	154	#define KSTK_EIP(tsk) (task_pt_regs(tsk)->psw.addr)
c7584fb6 AV	155	#define KSTK_ESP(tsk) (task_pt_regs(tsk)->gprs[15])
1da177e4	156
a0616cde DH	157	static inline unsigned short stap(void)
	158	{
	159	unsigned short cpu_address;
	160
	161	asm volatile("stap %0" : "=m" (cpu_address));
	162	return cpu_address;
	163	}
	164
1da177e4 LT	165	/*
	166	* Give up the time slice of the virtual PU.
	167	*/
abdba61a HC	168	static inline void cpu_relax(void)
	169	{
	170	if (MACHINE_HAS_DIAG44)
c48e0913 HC	171	asm volatile("diag 0,0,68");
c48e0913 HC	172	barrier();
abdba61a	173	}
1da177e4	174
dc74d7f9 HC	175	static inline void psw_set_key(unsigned int key)
	176	{
	177	asm volatile("spka 0(%0)" : : "d" (key));
	178	}
	179
77fa2245 HC	180	/*
	181	* Set PSW to specified value.
	182	*/
	183	static inline void __load_psw(psw_t psw)
	184	{
	185	#ifndef __s390x__
987bcdac	186	asm volatile("lpsw %0" : : "Q" (psw) : "cc");
77fa2245	187	#else
987bcdac	188	asm volatile("lpswe %0" : : "Q" (psw) : "cc");
77fa2245 HC	189	#endif
	190	}
	191
1da177e4 LT	192	/*
	193	* Set PSW mask to specified value, while leaving the
	194	* PSW addr pointing to the next instruction.
	195	*/
1da177e4 LT	196	static inline void __load_psw_mask (unsigned long mask)
	197	{
	198	unsigned long addr;
1da177e4	199	psw_t psw;
77fa2245	200
1da177e4 LT	201	psw.mask = mask;
	202
	203	#ifndef __s390x__
94c12cc7 MS	204	asm volatile(
	205	" basr %0,0\n"
	206	"0: ahi %0,1f-0b\n"
987bcdac MS	207	" st %0,%O1+4(%R1)\n"
987bcdac MS	208	" lpsw %1\n"
1da177e4	209	"1:"
987bcdac	210	: "=&d" (addr), "=Q" (psw) : "Q" (psw) : "memory", "cc");
1da177e4	211	#else /* __s390x__ */
94c12cc7 MS	212	asm volatile(
94c12cc7 MS	213	" larl %0,1f\n"
987bcdac MS	214	" stg %0,%O1+8(%R1)\n"
987bcdac MS	215	" lpswe %1\n"
1da177e4	216	"1:"
987bcdac	217	: "=&d" (addr), "=Q" (psw) : "Q" (psw) : "memory", "cc");
1da177e4 LT	218	#endif /* __s390x__ */
1da177e4 LT	219	}
ccf45caf MS	220
	221	/*
	222	* Rewind PSW instruction address by specified number of bytes.
	223	*/
	224	static inline unsigned long __rewind_psw(psw_t psw, unsigned long ilc)
	225	{
	226	#ifndef __s390x__
	227	if (psw.addr & PSW_ADDR_AMODE)
	228	/* 31 bit mode */
	229	return (psw.addr - ilc) \| PSW_ADDR_AMODE;
	230	/* 24 bit mode */
	231	return (psw.addr - ilc) & ((1UL << 24) - 1);
	232	#else
	233	unsigned long mask;
	234
	235	mask = (psw.mask & PSW_MASK_EA) ? -1UL :
	236	(psw.mask & PSW_MASK_BA) ? (1UL << 31) - 1 :
	237	(1UL << 24) - 1;
	238	return (psw.addr - ilc) & mask;
	239	#endif
	240	}
1da177e4	241
1da177e4 LT	242	/*
	243	* Function to drop a processor into disabled wait state
	244	*/
ff2d8b19	245	static inline void __noreturn disabled_wait(unsigned long code)
1da177e4	246	{
1da177e4	247	unsigned long ctl_buf;
77fa2245	248	psw_t dw_psw;
1da177e4	249
b50511e4	250	dw_psw.mask = PSW_MASK_BASE \| PSW_MASK_WAIT \| PSW_MASK_BA \| PSW_MASK_EA;
77fa2245	251	dw_psw.addr = code;
1da177e4 LT	252	/*
	253	* Store status and then load disabled wait psw,
	254	* the processor is dead afterwards
	255	*/
	256	#ifndef __s390x__
94c12cc7 MS	257	asm volatile(
	258	" stctl 0,0,0(%2)\n"
	259	" ni 0(%2),0xef\n" /* switch off protection */
	260	" lctl 0,0,0(%2)\n"
	261	" stpt 0xd8\n" /* store timer */
	262	" stckc 0xe0\n" /* store clock comparator */
	263	" stpx 0x108\n" /* store prefix register */
	264	" stam 0,15,0x120\n" /* store access registers */
	265	" std 0,0x160\n" /* store f0 */
	266	" std 2,0x168\n" /* store f2 */
	267	" std 4,0x170\n" /* store f4 */
	268	" std 6,0x178\n" /* store f6 */
	269	" stm 0,15,0x180\n" /* store general registers */
	270	" stctl 0,15,0x1c0\n" /* store control registers */
	271	" oi 0x1c0,0x10\n" /* fake protection bit */
	272	" lpsw 0(%1)"
	273	: "=m" (ctl_buf)
	274	: "a" (&dw_psw), "a" (&ctl_buf), "m" (dw_psw) : "cc");
1da177e4	275	#else /* __s390x__ */
94c12cc7 MS	276	asm volatile(
	277	" stctg 0,0,0(%2)\n"
	278	" ni 4(%2),0xef\n" /* switch off protection */
	279	" lctlg 0,0,0(%2)\n"
	280	" lghi 1,0x1000\n"
	281	" stpt 0x328(1)\n" /* store timer */
	282	" stckc 0x330(1)\n" /* store clock comparator */
	283	" stpx 0x318(1)\n" /* store prefix register */
	284	" stam 0,15,0x340(1)\n"/* store access registers */
	285	" stfpc 0x31c(1)\n" /* store fpu control */
	286	" std 0,0x200(1)\n" /* store f0 */
	287	" std 1,0x208(1)\n" /* store f1 */
	288	" std 2,0x210(1)\n" /* store f2 */
	289	" std 3,0x218(1)\n" /* store f3 */
	290	" std 4,0x220(1)\n" /* store f4 */
	291	" std 5,0x228(1)\n" /* store f5 */
	292	" std 6,0x230(1)\n" /* store f6 */
	293	" std 7,0x238(1)\n" /* store f7 */
	294	" std 8,0x240(1)\n" /* store f8 */
	295	" std 9,0x248(1)\n" /* store f9 */
	296	" std 10,0x250(1)\n" /* store f10 */
	297	" std 11,0x258(1)\n" /* store f11 */
	298	" std 12,0x260(1)\n" /* store f12 */
	299	" std 13,0x268(1)\n" /* store f13 */
	300	" std 14,0x270(1)\n" /* store f14 */
	301	" std 15,0x278(1)\n" /* store f15 */
	302	" stmg 0,15,0x280(1)\n"/* store general registers */
	303	" stctg 0,15,0x380(1)\n"/* store control registers */
	304	" oi 0x384(1),0x10\n"/* fake protection bit */
	305	" lpswe 0(%1)"
	306	: "=m" (ctl_buf)
bdd42b28	307	: "a" (&dw_psw), "a" (&ctl_buf), "m" (dw_psw) : "cc", "0", "1");
1da177e4	308	#endif /* __s390x__ */
edd53787	309	while (1);
1da177e4 LT	310	}
1da177e4 LT	311
a0616cde DH	312	/*
	313	* Use to set psw mask except for the first byte which
	314	* won't be changed by this function.
	315	*/
	316	static inline void
	317	__set_psw_mask(unsigned long mask)
	318	{
	319	__load_psw_mask(mask \| (arch_local_save_flags() & ~(-1UL >> 8)));
	320	}
	321
	322	#define local_mcck_enable() \
	323	__set_psw_mask(psw_kernel_bits \| PSW_MASK_DAT \| PSW_MASK_MCHECK)
	324	#define local_mcck_disable() \
	325	__set_psw_mask(psw_kernel_bits \| PSW_MASK_DAT)
	326
ab14de6c HC	327	/*
	328	* Basic Machine Check/Program Check Handler.
	329	*/
	330
	331	extern void s390_base_mcck_handler(void);
	332	extern void s390_base_pgm_handler(void);
	333	extern void s390_base_ext_handler(void);
	334
	335	extern void (*s390_base_mcck_handler_fn)(void);
	336	extern void (*s390_base_pgm_handler_fn)(void);
	337	extern void (*s390_base_ext_handler_fn)(void);
	338
dfd54cbc HC	339	#define ARCH_LOW_ADDRESS_LIMIT 0x7fffffffUL
dfd54cbc HC	340
1da177e4 LT	341	#endif
1da177e4 LT	342
de1a3f1c MS	343	/*
	344	* Helper macro for exception table entries
	345	*/
	346	#ifndef __s390x__
	347	#define EX_TABLE(_fault,_target) \
	348	".section __ex_table,\"a\"\n" \
	349	" .align 4\n" \
	350	" .long " #_fault "," #_target "\n" \
	351	".previous\n"
	352	#else
	353	#define EX_TABLE(_fault,_target) \
	354	".section __ex_table,\"a\"\n" \
	355	" .align 8\n" \
	356	" .quad " #_fault "," #_target "\n" \
	357	".previous\n"
	358	#endif
	359
1da177e4	360	#endif /* __ASM_S390_PROCESSOR_H */