Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * include/asm-s390/pgtable.h | |
3 | * | |
4 | * S390 version | |
5 | * Copyright (C) 1999,2000 IBM Deutschland Entwicklung GmbH, IBM Corporation | |
6 | * Author(s): Hartmut Penner (hp@de.ibm.com) | |
7 | * Ulrich Weigand (weigand@de.ibm.com) | |
8 | * Martin Schwidefsky (schwidefsky@de.ibm.com) | |
9 | * | |
10 | * Derived from "include/asm-i386/pgtable.h" | |
11 | */ | |
12 | ||
13 | #ifndef _ASM_S390_PGTABLE_H | |
14 | #define _ASM_S390_PGTABLE_H | |
15 | ||
1da177e4 LT |
16 | /* |
17 | * The Linux memory management assumes a three-level page table setup. For | |
18 | * s390 31 bit we "fold" the mid level into the top-level page table, so | |
19 | * that we physically have the same two-level page table as the s390 mmu | |
20 | * expects in 31 bit mode. For s390 64 bit we use three of the five levels | |
21 | * the hardware provides (region first and region second tables are not | |
22 | * used). | |
23 | * | |
24 | * The "pgd_xxx()" functions are trivial for a folded two-level | |
25 | * setup: the pgd is never bad, and a pmd always exists (as it's folded | |
26 | * into the pgd entry) | |
27 | * | |
28 | * This file contains the functions and defines necessary to modify and use | |
29 | * the S390 page table tree. | |
30 | */ | |
31 | #ifndef __ASSEMBLY__ | |
9789db08 | 32 | #include <linux/sched.h> |
2dcea57a | 33 | #include <linux/mm_types.h> |
5b7baf05 | 34 | #include <asm/bitops.h> |
1da177e4 LT |
35 | #include <asm/bug.h> |
36 | #include <asm/processor.h> | |
1da177e4 | 37 | |
1da177e4 LT |
38 | extern pgd_t swapper_pg_dir[] __attribute__ ((aligned (4096))); |
39 | extern void paging_init(void); | |
2b67fc46 | 40 | extern void vmem_map_init(void); |
92f842ea | 41 | extern void fault_init(void); |
1da177e4 LT |
42 | |
43 | /* | |
44 | * The S390 doesn't have any external MMU info: the kernel page | |
45 | * tables contain all the necessary information. | |
46 | */ | |
4b3073e1 | 47 | #define update_mmu_cache(vma, address, ptep) do { } while (0) |
1da177e4 LT |
48 | |
49 | /* | |
238ec4ef | 50 | * ZERO_PAGE is a global shared page that is always zero; used |
1da177e4 LT |
51 | * for zero-mapped memory areas etc.. |
52 | */ | |
238ec4ef MS |
53 | |
54 | extern unsigned long empty_zero_page; | |
55 | extern unsigned long zero_page_mask; | |
56 | ||
57 | #define ZERO_PAGE(vaddr) \ | |
58 | (virt_to_page((void *)(empty_zero_page + \ | |
59 | (((unsigned long)(vaddr)) &zero_page_mask)))) | |
60 | ||
61 | #define is_zero_pfn is_zero_pfn | |
62 | static inline int is_zero_pfn(unsigned long pfn) | |
63 | { | |
64 | extern unsigned long zero_pfn; | |
65 | unsigned long offset_from_zero_pfn = pfn - zero_pfn; | |
66 | return offset_from_zero_pfn <= (zero_page_mask >> PAGE_SHIFT); | |
67 | } | |
68 | ||
69 | #define my_zero_pfn(addr) page_to_pfn(ZERO_PAGE(addr)) | |
70 | ||
1da177e4 LT |
71 | #endif /* !__ASSEMBLY__ */ |
72 | ||
73 | /* | |
74 | * PMD_SHIFT determines the size of the area a second-level page | |
75 | * table can map | |
76 | * PGDIR_SHIFT determines what a third-level page table entry can map | |
77 | */ | |
78 | #ifndef __s390x__ | |
146e4b3c MS |
79 | # define PMD_SHIFT 20 |
80 | # define PUD_SHIFT 20 | |
81 | # define PGDIR_SHIFT 20 | |
1da177e4 | 82 | #else /* __s390x__ */ |
146e4b3c | 83 | # define PMD_SHIFT 20 |
190a1d72 | 84 | # define PUD_SHIFT 31 |
5a216a20 | 85 | # define PGDIR_SHIFT 42 |
1da177e4 LT |
86 | #endif /* __s390x__ */ |
87 | ||
88 | #define PMD_SIZE (1UL << PMD_SHIFT) | |
89 | #define PMD_MASK (~(PMD_SIZE-1)) | |
190a1d72 MS |
90 | #define PUD_SIZE (1UL << PUD_SHIFT) |
91 | #define PUD_MASK (~(PUD_SIZE-1)) | |
5a216a20 MS |
92 | #define PGDIR_SIZE (1UL << PGDIR_SHIFT) |
93 | #define PGDIR_MASK (~(PGDIR_SIZE-1)) | |
1da177e4 LT |
94 | |
95 | /* | |
96 | * entries per page directory level: the S390 is two-level, so | |
97 | * we don't really have any PMD directory physically. | |
98 | * for S390 segment-table entries are combined to one PGD | |
99 | * that leads to 1024 pte per pgd | |
100 | */ | |
146e4b3c | 101 | #define PTRS_PER_PTE 256 |
1da177e4 | 102 | #ifndef __s390x__ |
146e4b3c | 103 | #define PTRS_PER_PMD 1 |
5a216a20 | 104 | #define PTRS_PER_PUD 1 |
1da177e4 | 105 | #else /* __s390x__ */ |
146e4b3c | 106 | #define PTRS_PER_PMD 2048 |
5a216a20 | 107 | #define PTRS_PER_PUD 2048 |
1da177e4 | 108 | #endif /* __s390x__ */ |
146e4b3c | 109 | #define PTRS_PER_PGD 2048 |
1da177e4 | 110 | |
d455a369 HD |
111 | #define FIRST_USER_ADDRESS 0 |
112 | ||
1da177e4 LT |
113 | #define pte_ERROR(e) \ |
114 | printk("%s:%d: bad pte %p.\n", __FILE__, __LINE__, (void *) pte_val(e)) | |
115 | #define pmd_ERROR(e) \ | |
116 | printk("%s:%d: bad pmd %p.\n", __FILE__, __LINE__, (void *) pmd_val(e)) | |
190a1d72 MS |
117 | #define pud_ERROR(e) \ |
118 | printk("%s:%d: bad pud %p.\n", __FILE__, __LINE__, (void *) pud_val(e)) | |
1da177e4 LT |
119 | #define pgd_ERROR(e) \ |
120 | printk("%s:%d: bad pgd %p.\n", __FILE__, __LINE__, (void *) pgd_val(e)) | |
121 | ||
122 | #ifndef __ASSEMBLY__ | |
123 | /* | |
5fd9c6e2 | 124 | * The vmalloc area will always be on the topmost area of the kernel |
7d3f661e | 125 | * mapping. We reserve 96MB (31bit) / 128GB (64bit) for vmalloc, |
5fd9c6e2 CB |
126 | * which should be enough for any sane case. |
127 | * By putting vmalloc at the top, we maximise the gap between physical | |
128 | * memory and vmalloc to catch misplaced memory accesses. As a side | |
129 | * effect, this also makes sure that 64 bit module code cannot be used | |
130 | * as system call address. | |
8b62bc96 | 131 | */ |
239a6425 HC |
132 | |
133 | extern unsigned long VMALLOC_START; | |
134 | ||
1da177e4 | 135 | #ifndef __s390x__ |
239a6425 | 136 | #define VMALLOC_SIZE (96UL << 20) |
5fd9c6e2 | 137 | #define VMALLOC_END 0x7e000000UL |
0189103c | 138 | #define VMEM_MAP_END 0x80000000UL |
1da177e4 | 139 | #else /* __s390x__ */ |
7d3f661e MS |
140 | #define VMALLOC_SIZE (128UL << 30) |
141 | #define VMALLOC_END 0x3e000000000UL | |
0189103c | 142 | #define VMEM_MAP_END 0x40000000000UL |
1da177e4 LT |
143 | #endif /* __s390x__ */ |
144 | ||
0189103c HC |
145 | /* |
146 | * VMEM_MAX_PHYS is the highest physical address that can be added to the 1:1 | |
147 | * mapping. This needs to be calculated at compile time since the size of the | |
148 | * VMEM_MAP is static but the size of struct page can change. | |
149 | */ | |
522d8dc0 MS |
150 | #define VMEM_MAX_PAGES ((VMEM_MAP_END - VMALLOC_END) / sizeof(struct page)) |
151 | #define VMEM_MAX_PFN min(VMALLOC_START >> PAGE_SHIFT, VMEM_MAX_PAGES) | |
152 | #define VMEM_MAX_PHYS ((VMEM_MAX_PFN << PAGE_SHIFT) & ~((16 << 20) - 1)) | |
17f34580 | 153 | #define vmemmap ((struct page *) VMALLOC_END) |
5fd9c6e2 | 154 | |
1da177e4 LT |
155 | /* |
156 | * A 31 bit pagetable entry of S390 has following format: | |
157 | * | PFRA | | OS | | |
158 | * 0 0IP0 | |
159 | * 00000000001111111111222222222233 | |
160 | * 01234567890123456789012345678901 | |
161 | * | |
162 | * I Page-Invalid Bit: Page is not available for address-translation | |
163 | * P Page-Protection Bit: Store access not possible for page | |
164 | * | |
165 | * A 31 bit segmenttable entry of S390 has following format: | |
166 | * | P-table origin | |PTL | |
167 | * 0 IC | |
168 | * 00000000001111111111222222222233 | |
169 | * 01234567890123456789012345678901 | |
170 | * | |
171 | * I Segment-Invalid Bit: Segment is not available for address-translation | |
172 | * C Common-Segment Bit: Segment is not private (PoP 3-30) | |
173 | * PTL Page-Table-Length: Page-table length (PTL+1*16 entries -> up to 256) | |
174 | * | |
175 | * The 31 bit segmenttable origin of S390 has following format: | |
176 | * | |
177 | * |S-table origin | | STL | | |
178 | * X **GPS | |
179 | * 00000000001111111111222222222233 | |
180 | * 01234567890123456789012345678901 | |
181 | * | |
182 | * X Space-Switch event: | |
183 | * G Segment-Invalid Bit: * | |
184 | * P Private-Space Bit: Segment is not private (PoP 3-30) | |
185 | * S Storage-Alteration: | |
186 | * STL Segment-Table-Length: Segment-table length (STL+1*16 entries -> up to 2048) | |
187 | * | |
188 | * A 64 bit pagetable entry of S390 has following format: | |
6a985c61 | 189 | * | PFRA |0IPC| OS | |
1da177e4 LT |
190 | * 0000000000111111111122222222223333333333444444444455555555556666 |
191 | * 0123456789012345678901234567890123456789012345678901234567890123 | |
192 | * | |
193 | * I Page-Invalid Bit: Page is not available for address-translation | |
194 | * P Page-Protection Bit: Store access not possible for page | |
6a985c61 | 195 | * C Change-bit override: HW is not required to set change bit |
1da177e4 LT |
196 | * |
197 | * A 64 bit segmenttable entry of S390 has following format: | |
198 | * | P-table origin | TT | |
199 | * 0000000000111111111122222222223333333333444444444455555555556666 | |
200 | * 0123456789012345678901234567890123456789012345678901234567890123 | |
201 | * | |
202 | * I Segment-Invalid Bit: Segment is not available for address-translation | |
203 | * C Common-Segment Bit: Segment is not private (PoP 3-30) | |
204 | * P Page-Protection Bit: Store access not possible for page | |
205 | * TT Type 00 | |
206 | * | |
207 | * A 64 bit region table entry of S390 has following format: | |
208 | * | S-table origin | TF TTTL | |
209 | * 0000000000111111111122222222223333333333444444444455555555556666 | |
210 | * 0123456789012345678901234567890123456789012345678901234567890123 | |
211 | * | |
212 | * I Segment-Invalid Bit: Segment is not available for address-translation | |
213 | * TT Type 01 | |
214 | * TF | |
190a1d72 | 215 | * TL Table length |
1da177e4 LT |
216 | * |
217 | * The 64 bit regiontable origin of S390 has following format: | |
218 | * | region table origon | DTTL | |
219 | * 0000000000111111111122222222223333333333444444444455555555556666 | |
220 | * 0123456789012345678901234567890123456789012345678901234567890123 | |
221 | * | |
222 | * X Space-Switch event: | |
223 | * G Segment-Invalid Bit: | |
224 | * P Private-Space Bit: | |
225 | * S Storage-Alteration: | |
226 | * R Real space | |
227 | * TL Table-Length: | |
228 | * | |
229 | * A storage key has the following format: | |
230 | * | ACC |F|R|C|0| | |
231 | * 0 3 4 5 6 7 | |
232 | * ACC: access key | |
233 | * F : fetch protection bit | |
234 | * R : referenced bit | |
235 | * C : changed bit | |
236 | */ | |
237 | ||
238 | /* Hardware bits in the page table entry */ | |
6a985c61 | 239 | #define _PAGE_CO 0x100 /* HW Change-bit override */ |
83377484 MS |
240 | #define _PAGE_RO 0x200 /* HW read-only bit */ |
241 | #define _PAGE_INVALID 0x400 /* HW invalid bit */ | |
3610cce8 MS |
242 | |
243 | /* Software bits in the page table entry */ | |
83377484 MS |
244 | #define _PAGE_SWT 0x001 /* SW pte type bit t */ |
245 | #define _PAGE_SWX 0x002 /* SW pte type bit x */ | |
a08cb629 NP |
246 | #define _PAGE_SPECIAL 0x004 /* SW associated with special page */ |
247 | #define __HAVE_ARCH_PTE_SPECIAL | |
1da177e4 | 248 | |
138c9021 NP |
249 | /* Set of bits not changed in pte_modify */ |
250 | #define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_SPECIAL) | |
251 | ||
83377484 | 252 | /* Six different types of pages. */ |
9282ed92 GS |
253 | #define _PAGE_TYPE_EMPTY 0x400 |
254 | #define _PAGE_TYPE_NONE 0x401 | |
83377484 MS |
255 | #define _PAGE_TYPE_SWAP 0x403 |
256 | #define _PAGE_TYPE_FILE 0x601 /* bit 0x002 is used for offset !! */ | |
9282ed92 GS |
257 | #define _PAGE_TYPE_RO 0x200 |
258 | #define _PAGE_TYPE_RW 0x000 | |
c1821c2e GS |
259 | #define _PAGE_TYPE_EX_RO 0x202 |
260 | #define _PAGE_TYPE_EX_RW 0x002 | |
1da177e4 | 261 | |
53492b1d GS |
262 | /* |
263 | * Only four types for huge pages, using the invalid bit and protection bit | |
264 | * of a segment table entry. | |
265 | */ | |
266 | #define _HPAGE_TYPE_EMPTY 0x020 /* _SEGMENT_ENTRY_INV */ | |
267 | #define _HPAGE_TYPE_NONE 0x220 | |
268 | #define _HPAGE_TYPE_RO 0x200 /* _SEGMENT_ENTRY_RO */ | |
269 | #define _HPAGE_TYPE_RW 0x000 | |
270 | ||
83377484 MS |
271 | /* |
272 | * PTE type bits are rather complicated. handle_pte_fault uses pte_present, | |
273 | * pte_none and pte_file to find out the pte type WITHOUT holding the page | |
274 | * table lock. ptep_clear_flush on the other hand uses ptep_clear_flush to | |
275 | * invalidate a given pte. ipte sets the hw invalid bit and clears all tlbs | |
276 | * for the page. The page table entry is set to _PAGE_TYPE_EMPTY afterwards. | |
277 | * This change is done while holding the lock, but the intermediate step | |
278 | * of a previously valid pte with the hw invalid bit set can be observed by | |
279 | * handle_pte_fault. That makes it necessary that all valid pte types with | |
280 | * the hw invalid bit set must be distinguishable from the four pte types | |
281 | * empty, none, swap and file. | |
282 | * | |
283 | * irxt ipte irxt | |
284 | * _PAGE_TYPE_EMPTY 1000 -> 1000 | |
285 | * _PAGE_TYPE_NONE 1001 -> 1001 | |
286 | * _PAGE_TYPE_SWAP 1011 -> 1011 | |
287 | * _PAGE_TYPE_FILE 11?1 -> 11?1 | |
288 | * _PAGE_TYPE_RO 0100 -> 1100 | |
289 | * _PAGE_TYPE_RW 0000 -> 1000 | |
c1821c2e GS |
290 | * _PAGE_TYPE_EX_RO 0110 -> 1110 |
291 | * _PAGE_TYPE_EX_RW 0010 -> 1010 | |
83377484 | 292 | * |
c1821c2e | 293 | * pte_none is true for bits combinations 1000, 1010, 1100, 1110 |
83377484 MS |
294 | * pte_present is true for bits combinations 0000, 0010, 0100, 0110, 1001 |
295 | * pte_file is true for bits combinations 1101, 1111 | |
c1821c2e | 296 | * swap pte is 1011 and 0001, 0011, 0101, 0111 are invalid. |
83377484 MS |
297 | */ |
298 | ||
5b7baf05 CB |
299 | /* Page status table bits for virtualization */ |
300 | #define RCP_PCL_BIT 55 | |
301 | #define RCP_HR_BIT 54 | |
302 | #define RCP_HC_BIT 53 | |
303 | #define RCP_GR_BIT 50 | |
304 | #define RCP_GC_BIT 49 | |
305 | ||
15e86b0c FF |
306 | /* User dirty bit for KVM's migration feature */ |
307 | #define KVM_UD_BIT 47 | |
308 | ||
1da177e4 LT |
309 | #ifndef __s390x__ |
310 | ||
3610cce8 MS |
311 | /* Bits in the segment table address-space-control-element */ |
312 | #define _ASCE_SPACE_SWITCH 0x80000000UL /* space switch event */ | |
313 | #define _ASCE_ORIGIN_MASK 0x7ffff000UL /* segment table origin */ | |
314 | #define _ASCE_PRIVATE_SPACE 0x100 /* private space control */ | |
315 | #define _ASCE_ALT_EVENT 0x80 /* storage alteration event control */ | |
316 | #define _ASCE_TABLE_LENGTH 0x7f /* 128 x 64 entries = 8k */ | |
1da177e4 | 317 | |
3610cce8 MS |
318 | /* Bits in the segment table entry */ |
319 | #define _SEGMENT_ENTRY_ORIGIN 0x7fffffc0UL /* page table origin */ | |
80217147 | 320 | #define _SEGMENT_ENTRY_RO 0x200 /* page protection bit */ |
3610cce8 MS |
321 | #define _SEGMENT_ENTRY_INV 0x20 /* invalid segment table entry */ |
322 | #define _SEGMENT_ENTRY_COMMON 0x10 /* common segment bit */ | |
323 | #define _SEGMENT_ENTRY_PTL 0x0f /* page table length */ | |
1da177e4 | 324 | |
3610cce8 MS |
325 | #define _SEGMENT_ENTRY (_SEGMENT_ENTRY_PTL) |
326 | #define _SEGMENT_ENTRY_EMPTY (_SEGMENT_ENTRY_INV) | |
1da177e4 LT |
327 | |
328 | #else /* __s390x__ */ | |
329 | ||
3610cce8 MS |
330 | /* Bits in the segment/region table address-space-control-element */ |
331 | #define _ASCE_ORIGIN ~0xfffUL/* segment table origin */ | |
332 | #define _ASCE_PRIVATE_SPACE 0x100 /* private space control */ | |
333 | #define _ASCE_ALT_EVENT 0x80 /* storage alteration event control */ | |
334 | #define _ASCE_SPACE_SWITCH 0x40 /* space switch event */ | |
335 | #define _ASCE_REAL_SPACE 0x20 /* real space control */ | |
336 | #define _ASCE_TYPE_MASK 0x0c /* asce table type mask */ | |
337 | #define _ASCE_TYPE_REGION1 0x0c /* region first table type */ | |
338 | #define _ASCE_TYPE_REGION2 0x08 /* region second table type */ | |
339 | #define _ASCE_TYPE_REGION3 0x04 /* region third table type */ | |
340 | #define _ASCE_TYPE_SEGMENT 0x00 /* segment table type */ | |
341 | #define _ASCE_TABLE_LENGTH 0x03 /* region table length */ | |
342 | ||
343 | /* Bits in the region table entry */ | |
344 | #define _REGION_ENTRY_ORIGIN ~0xfffUL/* region/segment table origin */ | |
345 | #define _REGION_ENTRY_INV 0x20 /* invalid region table entry */ | |
346 | #define _REGION_ENTRY_TYPE_MASK 0x0c /* region/segment table type mask */ | |
347 | #define _REGION_ENTRY_TYPE_R1 0x0c /* region first table type */ | |
348 | #define _REGION_ENTRY_TYPE_R2 0x08 /* region second table type */ | |
349 | #define _REGION_ENTRY_TYPE_R3 0x04 /* region third table type */ | |
350 | #define _REGION_ENTRY_LENGTH 0x03 /* region third length */ | |
351 | ||
352 | #define _REGION1_ENTRY (_REGION_ENTRY_TYPE_R1 | _REGION_ENTRY_LENGTH) | |
353 | #define _REGION1_ENTRY_EMPTY (_REGION_ENTRY_TYPE_R1 | _REGION_ENTRY_INV) | |
354 | #define _REGION2_ENTRY (_REGION_ENTRY_TYPE_R2 | _REGION_ENTRY_LENGTH) | |
355 | #define _REGION2_ENTRY_EMPTY (_REGION_ENTRY_TYPE_R2 | _REGION_ENTRY_INV) | |
356 | #define _REGION3_ENTRY (_REGION_ENTRY_TYPE_R3 | _REGION_ENTRY_LENGTH) | |
357 | #define _REGION3_ENTRY_EMPTY (_REGION_ENTRY_TYPE_R3 | _REGION_ENTRY_INV) | |
358 | ||
1da177e4 | 359 | /* Bits in the segment table entry */ |
3610cce8 MS |
360 | #define _SEGMENT_ENTRY_ORIGIN ~0x7ffUL/* segment table origin */ |
361 | #define _SEGMENT_ENTRY_RO 0x200 /* page protection bit */ | |
362 | #define _SEGMENT_ENTRY_INV 0x20 /* invalid segment table entry */ | |
1da177e4 | 363 | |
3610cce8 MS |
364 | #define _SEGMENT_ENTRY (0) |
365 | #define _SEGMENT_ENTRY_EMPTY (_SEGMENT_ENTRY_INV) | |
366 | ||
53492b1d GS |
367 | #define _SEGMENT_ENTRY_LARGE 0x400 /* STE-format control, large page */ |
368 | #define _SEGMENT_ENTRY_CO 0x100 /* change-recording override */ | |
369 | ||
3610cce8 | 370 | #endif /* __s390x__ */ |
1da177e4 LT |
371 | |
372 | /* | |
3610cce8 MS |
373 | * A user page table pointer has the space-switch-event bit, the |
374 | * private-space-control bit and the storage-alteration-event-control | |
375 | * bit set. A kernel page table pointer doesn't need them. | |
1da177e4 | 376 | */ |
3610cce8 MS |
377 | #define _ASCE_USER_BITS (_ASCE_SPACE_SWITCH | _ASCE_PRIVATE_SPACE | \ |
378 | _ASCE_ALT_EVENT) | |
1da177e4 | 379 | |
3610cce8 | 380 | /* Bits int the storage key */ |
1da177e4 LT |
381 | #define _PAGE_CHANGED 0x02 /* HW changed bit */ |
382 | #define _PAGE_REFERENCED 0x04 /* HW referenced bit */ | |
383 | ||
1da177e4 | 384 | /* |
9282ed92 | 385 | * Page protection definitions. |
1da177e4 | 386 | */ |
9282ed92 GS |
387 | #define PAGE_NONE __pgprot(_PAGE_TYPE_NONE) |
388 | #define PAGE_RO __pgprot(_PAGE_TYPE_RO) | |
389 | #define PAGE_RW __pgprot(_PAGE_TYPE_RW) | |
c1821c2e GS |
390 | #define PAGE_EX_RO __pgprot(_PAGE_TYPE_EX_RO) |
391 | #define PAGE_EX_RW __pgprot(_PAGE_TYPE_EX_RW) | |
9282ed92 GS |
392 | |
393 | #define PAGE_KERNEL PAGE_RW | |
394 | #define PAGE_COPY PAGE_RO | |
1da177e4 LT |
395 | |
396 | /* | |
c1821c2e GS |
397 | * Dependent on the EXEC_PROTECT option s390 can do execute protection. |
398 | * Write permission always implies read permission. In theory with a | |
399 | * primary/secondary page table execute only can be implemented but | |
400 | * it would cost an additional bit in the pte to distinguish all the | |
401 | * different pte types. To avoid that execute permission currently | |
402 | * implies read permission as well. | |
1da177e4 LT |
403 | */ |
404 | /*xwr*/ | |
9282ed92 GS |
405 | #define __P000 PAGE_NONE |
406 | #define __P001 PAGE_RO | |
407 | #define __P010 PAGE_RO | |
408 | #define __P011 PAGE_RO | |
c1821c2e GS |
409 | #define __P100 PAGE_EX_RO |
410 | #define __P101 PAGE_EX_RO | |
411 | #define __P110 PAGE_EX_RO | |
412 | #define __P111 PAGE_EX_RO | |
9282ed92 GS |
413 | |
414 | #define __S000 PAGE_NONE | |
415 | #define __S001 PAGE_RO | |
416 | #define __S010 PAGE_RW | |
417 | #define __S011 PAGE_RW | |
c1821c2e GS |
418 | #define __S100 PAGE_EX_RO |
419 | #define __S101 PAGE_EX_RO | |
420 | #define __S110 PAGE_EX_RW | |
421 | #define __S111 PAGE_EX_RW | |
422 | ||
423 | #ifndef __s390x__ | |
3610cce8 | 424 | # define PxD_SHADOW_SHIFT 1 |
c1821c2e | 425 | #else /* __s390x__ */ |
3610cce8 | 426 | # define PxD_SHADOW_SHIFT 2 |
c1821c2e GS |
427 | #endif /* __s390x__ */ |
428 | ||
3610cce8 | 429 | static inline void *get_shadow_table(void *table) |
c1821c2e | 430 | { |
3610cce8 MS |
431 | unsigned long addr, offset; |
432 | struct page *page; | |
433 | ||
434 | addr = (unsigned long) table; | |
435 | offset = addr & ((PAGE_SIZE << PxD_SHADOW_SHIFT) - 1); | |
436 | page = virt_to_page((void *)(addr ^ offset)); | |
437 | return (void *)(addr_t)(page->index ? (page->index | offset) : 0UL); | |
c1821c2e | 438 | } |
1da177e4 LT |
439 | |
440 | /* | |
441 | * Certain architectures need to do special things when PTEs | |
442 | * within a page table are directly modified. Thus, the following | |
443 | * hook is made available. | |
444 | */ | |
ba8a9229 | 445 | static inline void set_pte_at(struct mm_struct *mm, unsigned long addr, |
146e4b3c | 446 | pte_t *ptep, pte_t entry) |
1da177e4 | 447 | { |
146e4b3c MS |
448 | *ptep = entry; |
449 | if (mm->context.noexec) { | |
450 | if (!(pte_val(entry) & _PAGE_INVALID) && | |
451 | (pte_val(entry) & _PAGE_SWX)) | |
452 | pte_val(entry) |= _PAGE_RO; | |
c1821c2e | 453 | else |
146e4b3c MS |
454 | pte_val(entry) = _PAGE_TYPE_EMPTY; |
455 | ptep[PTRS_PER_PTE] = entry; | |
c1821c2e | 456 | } |
1da177e4 | 457 | } |
1da177e4 LT |
458 | |
459 | /* | |
460 | * pgd/pmd/pte query functions | |
461 | */ | |
462 | #ifndef __s390x__ | |
463 | ||
4448aaf0 AB |
464 | static inline int pgd_present(pgd_t pgd) { return 1; } |
465 | static inline int pgd_none(pgd_t pgd) { return 0; } | |
466 | static inline int pgd_bad(pgd_t pgd) { return 0; } | |
1da177e4 | 467 | |
190a1d72 MS |
468 | static inline int pud_present(pud_t pud) { return 1; } |
469 | static inline int pud_none(pud_t pud) { return 0; } | |
470 | static inline int pud_bad(pud_t pud) { return 0; } | |
471 | ||
1da177e4 LT |
472 | #else /* __s390x__ */ |
473 | ||
5a216a20 MS |
474 | static inline int pgd_present(pgd_t pgd) |
475 | { | |
6252d702 MS |
476 | if ((pgd_val(pgd) & _REGION_ENTRY_TYPE_MASK) < _REGION_ENTRY_TYPE_R2) |
477 | return 1; | |
5a216a20 MS |
478 | return (pgd_val(pgd) & _REGION_ENTRY_ORIGIN) != 0UL; |
479 | } | |
480 | ||
481 | static inline int pgd_none(pgd_t pgd) | |
482 | { | |
6252d702 MS |
483 | if ((pgd_val(pgd) & _REGION_ENTRY_TYPE_MASK) < _REGION_ENTRY_TYPE_R2) |
484 | return 0; | |
5a216a20 MS |
485 | return (pgd_val(pgd) & _REGION_ENTRY_INV) != 0UL; |
486 | } | |
487 | ||
488 | static inline int pgd_bad(pgd_t pgd) | |
489 | { | |
6252d702 MS |
490 | /* |
491 | * With dynamic page table levels the pgd can be a region table | |
492 | * entry or a segment table entry. Check for the bit that are | |
493 | * invalid for either table entry. | |
494 | */ | |
5a216a20 | 495 | unsigned long mask = |
6252d702 | 496 | ~_SEGMENT_ENTRY_ORIGIN & ~_REGION_ENTRY_INV & |
5a216a20 MS |
497 | ~_REGION_ENTRY_TYPE_MASK & ~_REGION_ENTRY_LENGTH; |
498 | return (pgd_val(pgd) & mask) != 0; | |
499 | } | |
190a1d72 MS |
500 | |
501 | static inline int pud_present(pud_t pud) | |
1da177e4 | 502 | { |
6252d702 MS |
503 | if ((pud_val(pud) & _REGION_ENTRY_TYPE_MASK) < _REGION_ENTRY_TYPE_R3) |
504 | return 1; | |
0d017923 | 505 | return (pud_val(pud) & _REGION_ENTRY_ORIGIN) != 0UL; |
1da177e4 LT |
506 | } |
507 | ||
190a1d72 | 508 | static inline int pud_none(pud_t pud) |
1da177e4 | 509 | { |
6252d702 MS |
510 | if ((pud_val(pud) & _REGION_ENTRY_TYPE_MASK) < _REGION_ENTRY_TYPE_R3) |
511 | return 0; | |
0d017923 | 512 | return (pud_val(pud) & _REGION_ENTRY_INV) != 0UL; |
1da177e4 LT |
513 | } |
514 | ||
190a1d72 | 515 | static inline int pud_bad(pud_t pud) |
1da177e4 | 516 | { |
6252d702 MS |
517 | /* |
518 | * With dynamic page table levels the pud can be a region table | |
519 | * entry or a segment table entry. Check for the bit that are | |
520 | * invalid for either table entry. | |
521 | */ | |
5a216a20 | 522 | unsigned long mask = |
6252d702 | 523 | ~_SEGMENT_ENTRY_ORIGIN & ~_REGION_ENTRY_INV & |
5a216a20 MS |
524 | ~_REGION_ENTRY_TYPE_MASK & ~_REGION_ENTRY_LENGTH; |
525 | return (pud_val(pud) & mask) != 0; | |
1da177e4 LT |
526 | } |
527 | ||
3610cce8 MS |
528 | #endif /* __s390x__ */ |
529 | ||
4448aaf0 | 530 | static inline int pmd_present(pmd_t pmd) |
1da177e4 | 531 | { |
0d017923 | 532 | return (pmd_val(pmd) & _SEGMENT_ENTRY_ORIGIN) != 0UL; |
1da177e4 LT |
533 | } |
534 | ||
4448aaf0 | 535 | static inline int pmd_none(pmd_t pmd) |
1da177e4 | 536 | { |
0d017923 | 537 | return (pmd_val(pmd) & _SEGMENT_ENTRY_INV) != 0UL; |
1da177e4 LT |
538 | } |
539 | ||
4448aaf0 | 540 | static inline int pmd_bad(pmd_t pmd) |
1da177e4 | 541 | { |
3610cce8 MS |
542 | unsigned long mask = ~_SEGMENT_ENTRY_ORIGIN & ~_SEGMENT_ENTRY_INV; |
543 | return (pmd_val(pmd) & mask) != _SEGMENT_ENTRY; | |
1da177e4 LT |
544 | } |
545 | ||
4448aaf0 | 546 | static inline int pte_none(pte_t pte) |
1da177e4 | 547 | { |
83377484 | 548 | return (pte_val(pte) & _PAGE_INVALID) && !(pte_val(pte) & _PAGE_SWT); |
1da177e4 LT |
549 | } |
550 | ||
4448aaf0 | 551 | static inline int pte_present(pte_t pte) |
1da177e4 | 552 | { |
83377484 MS |
553 | unsigned long mask = _PAGE_RO | _PAGE_INVALID | _PAGE_SWT | _PAGE_SWX; |
554 | return (pte_val(pte) & mask) == _PAGE_TYPE_NONE || | |
555 | (!(pte_val(pte) & _PAGE_INVALID) && | |
556 | !(pte_val(pte) & _PAGE_SWT)); | |
1da177e4 LT |
557 | } |
558 | ||
4448aaf0 | 559 | static inline int pte_file(pte_t pte) |
1da177e4 | 560 | { |
83377484 MS |
561 | unsigned long mask = _PAGE_RO | _PAGE_INVALID | _PAGE_SWT; |
562 | return (pte_val(pte) & mask) == _PAGE_TYPE_FILE; | |
1da177e4 LT |
563 | } |
564 | ||
7e675137 NP |
565 | static inline int pte_special(pte_t pte) |
566 | { | |
a08cb629 | 567 | return (pte_val(pte) & _PAGE_SPECIAL); |
7e675137 NP |
568 | } |
569 | ||
ba8a9229 MS |
570 | #define __HAVE_ARCH_PTE_SAME |
571 | #define pte_same(a,b) (pte_val(a) == pte_val(b)) | |
1da177e4 | 572 | |
5b7baf05 CB |
573 | static inline void rcp_lock(pte_t *ptep) |
574 | { | |
575 | #ifdef CONFIG_PGSTE | |
576 | unsigned long *pgste = (unsigned long *) (ptep + PTRS_PER_PTE); | |
577 | preempt_disable(); | |
578 | while (test_and_set_bit(RCP_PCL_BIT, pgste)) | |
579 | ; | |
580 | #endif | |
581 | } | |
582 | ||
583 | static inline void rcp_unlock(pte_t *ptep) | |
584 | { | |
585 | #ifdef CONFIG_PGSTE | |
586 | unsigned long *pgste = (unsigned long *) (ptep + PTRS_PER_PTE); | |
587 | clear_bit(RCP_PCL_BIT, pgste); | |
588 | preempt_enable(); | |
589 | #endif | |
590 | } | |
591 | ||
592 | /* forward declaration for SetPageUptodate in page-flags.h*/ | |
e2b8d7af | 593 | static inline void page_clear_dirty(struct page *page, int mapped); |
5b7baf05 CB |
594 | #include <linux/page-flags.h> |
595 | ||
596 | static inline void ptep_rcp_copy(pte_t *ptep) | |
597 | { | |
598 | #ifdef CONFIG_PGSTE | |
599 | struct page *page = virt_to_page(pte_val(*ptep)); | |
600 | unsigned int skey; | |
601 | unsigned long *pgste = (unsigned long *) (ptep + PTRS_PER_PTE); | |
602 | ||
603 | skey = page_get_storage_key(page_to_phys(page)); | |
15e86b0c | 604 | if (skey & _PAGE_CHANGED) { |
c71799c1 | 605 | set_bit_simple(RCP_GC_BIT, pgste); |
15e86b0c FF |
606 | set_bit_simple(KVM_UD_BIT, pgste); |
607 | } | |
5b7baf05 | 608 | if (skey & _PAGE_REFERENCED) |
c71799c1 | 609 | set_bit_simple(RCP_GR_BIT, pgste); |
15e86b0c | 610 | if (test_and_clear_bit_simple(RCP_HC_BIT, pgste)) { |
5b7baf05 | 611 | SetPageDirty(page); |
15e86b0c FF |
612 | set_bit_simple(KVM_UD_BIT, pgste); |
613 | } | |
c71799c1 | 614 | if (test_and_clear_bit_simple(RCP_HR_BIT, pgste)) |
5b7baf05 CB |
615 | SetPageReferenced(page); |
616 | #endif | |
617 | } | |
618 | ||
1da177e4 LT |
619 | /* |
620 | * query functions pte_write/pte_dirty/pte_young only work if | |
621 | * pte_present() is true. Undefined behaviour if not.. | |
622 | */ | |
4448aaf0 | 623 | static inline int pte_write(pte_t pte) |
1da177e4 LT |
624 | { |
625 | return (pte_val(pte) & _PAGE_RO) == 0; | |
626 | } | |
627 | ||
4448aaf0 | 628 | static inline int pte_dirty(pte_t pte) |
1da177e4 LT |
629 | { |
630 | /* A pte is neither clean nor dirty on s/390. The dirty bit | |
631 | * is in the storage key. See page_test_and_clear_dirty for | |
632 | * details. | |
633 | */ | |
634 | return 0; | |
635 | } | |
636 | ||
4448aaf0 | 637 | static inline int pte_young(pte_t pte) |
1da177e4 LT |
638 | { |
639 | /* A pte is neither young nor old on s/390. The young bit | |
640 | * is in the storage key. See page_test_and_clear_young for | |
641 | * details. | |
642 | */ | |
643 | return 0; | |
644 | } | |
645 | ||
1da177e4 LT |
646 | /* |
647 | * pgd/pmd/pte modification functions | |
648 | */ | |
649 | ||
650 | #ifndef __s390x__ | |
651 | ||
190a1d72 MS |
652 | #define pgd_clear(pgd) do { } while (0) |
653 | #define pud_clear(pud) do { } while (0) | |
1da177e4 | 654 | |
1da177e4 LT |
655 | #else /* __s390x__ */ |
656 | ||
5a216a20 MS |
657 | static inline void pgd_clear_kernel(pgd_t * pgd) |
658 | { | |
6252d702 MS |
659 | if ((pgd_val(*pgd) & _REGION_ENTRY_TYPE_MASK) == _REGION_ENTRY_TYPE_R2) |
660 | pgd_val(*pgd) = _REGION2_ENTRY_EMPTY; | |
5a216a20 MS |
661 | } |
662 | ||
663 | static inline void pgd_clear(pgd_t * pgd) | |
664 | { | |
665 | pgd_t *shadow = get_shadow_table(pgd); | |
666 | ||
667 | pgd_clear_kernel(pgd); | |
668 | if (shadow) | |
669 | pgd_clear_kernel(shadow); | |
670 | } | |
190a1d72 MS |
671 | |
672 | static inline void pud_clear_kernel(pud_t *pud) | |
1da177e4 | 673 | { |
6252d702 MS |
674 | if ((pud_val(*pud) & _REGION_ENTRY_TYPE_MASK) == _REGION_ENTRY_TYPE_R3) |
675 | pud_val(*pud) = _REGION3_ENTRY_EMPTY; | |
1da177e4 LT |
676 | } |
677 | ||
6252d702 | 678 | static inline void pud_clear(pud_t *pud) |
c1821c2e | 679 | { |
190a1d72 | 680 | pud_t *shadow = get_shadow_table(pud); |
c1821c2e | 681 | |
190a1d72 MS |
682 | pud_clear_kernel(pud); |
683 | if (shadow) | |
684 | pud_clear_kernel(shadow); | |
c1821c2e GS |
685 | } |
686 | ||
146e4b3c MS |
687 | #endif /* __s390x__ */ |
688 | ||
c1821c2e | 689 | static inline void pmd_clear_kernel(pmd_t * pmdp) |
1da177e4 | 690 | { |
3610cce8 | 691 | pmd_val(*pmdp) = _SEGMENT_ENTRY_EMPTY; |
1da177e4 LT |
692 | } |
693 | ||
146e4b3c | 694 | static inline void pmd_clear(pmd_t *pmd) |
c1821c2e | 695 | { |
146e4b3c | 696 | pmd_t *shadow = get_shadow_table(pmd); |
c1821c2e | 697 | |
146e4b3c MS |
698 | pmd_clear_kernel(pmd); |
699 | if (shadow) | |
700 | pmd_clear_kernel(shadow); | |
c1821c2e GS |
701 | } |
702 | ||
4448aaf0 | 703 | static inline void pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep) |
1da177e4 | 704 | { |
9282ed92 | 705 | pte_val(*ptep) = _PAGE_TYPE_EMPTY; |
146e4b3c MS |
706 | if (mm->context.noexec) |
707 | pte_val(ptep[PTRS_PER_PTE]) = _PAGE_TYPE_EMPTY; | |
1da177e4 LT |
708 | } |
709 | ||
710 | /* | |
711 | * The following pte modification functions only work if | |
712 | * pte_present() is true. Undefined behaviour if not.. | |
713 | */ | |
4448aaf0 | 714 | static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) |
1da177e4 | 715 | { |
138c9021 | 716 | pte_val(pte) &= _PAGE_CHG_MASK; |
1da177e4 LT |
717 | pte_val(pte) |= pgprot_val(newprot); |
718 | return pte; | |
719 | } | |
720 | ||
4448aaf0 | 721 | static inline pte_t pte_wrprotect(pte_t pte) |
1da177e4 | 722 | { |
9282ed92 | 723 | /* Do not clobber _PAGE_TYPE_NONE pages! */ |
1da177e4 LT |
724 | if (!(pte_val(pte) & _PAGE_INVALID)) |
725 | pte_val(pte) |= _PAGE_RO; | |
726 | return pte; | |
727 | } | |
728 | ||
4448aaf0 | 729 | static inline pte_t pte_mkwrite(pte_t pte) |
1da177e4 LT |
730 | { |
731 | pte_val(pte) &= ~_PAGE_RO; | |
732 | return pte; | |
733 | } | |
734 | ||
4448aaf0 | 735 | static inline pte_t pte_mkclean(pte_t pte) |
1da177e4 LT |
736 | { |
737 | /* The only user of pte_mkclean is the fork() code. | |
738 | We must *not* clear the *physical* page dirty bit | |
739 | just because fork() wants to clear the dirty bit in | |
740 | *one* of the page's mappings. So we just do nothing. */ | |
741 | return pte; | |
742 | } | |
743 | ||
4448aaf0 | 744 | static inline pte_t pte_mkdirty(pte_t pte) |
1da177e4 LT |
745 | { |
746 | /* We do not explicitly set the dirty bit because the | |
747 | * sske instruction is slow. It is faster to let the | |
748 | * next instruction set the dirty bit. | |
749 | */ | |
750 | return pte; | |
751 | } | |
752 | ||
4448aaf0 | 753 | static inline pte_t pte_mkold(pte_t pte) |
1da177e4 LT |
754 | { |
755 | /* S/390 doesn't keep its dirty/referenced bit in the pte. | |
756 | * There is no point in clearing the real referenced bit. | |
757 | */ | |
758 | return pte; | |
759 | } | |
760 | ||
4448aaf0 | 761 | static inline pte_t pte_mkyoung(pte_t pte) |
1da177e4 LT |
762 | { |
763 | /* S/390 doesn't keep its dirty/referenced bit in the pte. | |
764 | * There is no point in setting the real referenced bit. | |
765 | */ | |
766 | return pte; | |
767 | } | |
768 | ||
7e675137 NP |
769 | static inline pte_t pte_mkspecial(pte_t pte) |
770 | { | |
a08cb629 | 771 | pte_val(pte) |= _PAGE_SPECIAL; |
7e675137 NP |
772 | return pte; |
773 | } | |
774 | ||
15e86b0c FF |
775 | #ifdef CONFIG_PGSTE |
776 | /* | |
777 | * Get (and clear) the user dirty bit for a PTE. | |
778 | */ | |
779 | static inline int kvm_s390_test_and_clear_page_dirty(struct mm_struct *mm, | |
780 | pte_t *ptep) | |
781 | { | |
782 | int dirty; | |
783 | unsigned long *pgste; | |
784 | struct page *page; | |
785 | unsigned int skey; | |
786 | ||
250cf776 | 787 | if (!mm->context.has_pgste) |
15e86b0c FF |
788 | return -EINVAL; |
789 | rcp_lock(ptep); | |
790 | pgste = (unsigned long *) (ptep + PTRS_PER_PTE); | |
791 | page = virt_to_page(pte_val(*ptep)); | |
792 | skey = page_get_storage_key(page_to_phys(page)); | |
793 | if (skey & _PAGE_CHANGED) { | |
794 | set_bit_simple(RCP_GC_BIT, pgste); | |
795 | set_bit_simple(KVM_UD_BIT, pgste); | |
796 | } | |
797 | if (test_and_clear_bit_simple(RCP_HC_BIT, pgste)) { | |
798 | SetPageDirty(page); | |
799 | set_bit_simple(KVM_UD_BIT, pgste); | |
800 | } | |
801 | dirty = test_and_clear_bit_simple(KVM_UD_BIT, pgste); | |
802 | if (skey & _PAGE_CHANGED) | |
e2b8d7af | 803 | page_clear_dirty(page, 1); |
15e86b0c FF |
804 | rcp_unlock(ptep); |
805 | return dirty; | |
806 | } | |
807 | #endif | |
808 | ||
ba8a9229 MS |
809 | #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG |
810 | static inline int ptep_test_and_clear_young(struct vm_area_struct *vma, | |
811 | unsigned long addr, pte_t *ptep) | |
1da177e4 | 812 | { |
5b7baf05 CB |
813 | #ifdef CONFIG_PGSTE |
814 | unsigned long physpage; | |
815 | int young; | |
816 | unsigned long *pgste; | |
817 | ||
250cf776 | 818 | if (!vma->vm_mm->context.has_pgste) |
5b7baf05 CB |
819 | return 0; |
820 | physpage = pte_val(*ptep) & PAGE_MASK; | |
821 | pgste = (unsigned long *) (ptep + PTRS_PER_PTE); | |
822 | ||
823 | young = ((page_get_storage_key(physpage) & _PAGE_REFERENCED) != 0); | |
824 | rcp_lock(ptep); | |
825 | if (young) | |
c71799c1 HC |
826 | set_bit_simple(RCP_GR_BIT, pgste); |
827 | young |= test_and_clear_bit_simple(RCP_HR_BIT, pgste); | |
5b7baf05 CB |
828 | rcp_unlock(ptep); |
829 | return young; | |
830 | #endif | |
1da177e4 LT |
831 | return 0; |
832 | } | |
833 | ||
ba8a9229 MS |
834 | #define __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH |
835 | static inline int ptep_clear_flush_young(struct vm_area_struct *vma, | |
836 | unsigned long address, pte_t *ptep) | |
1da177e4 | 837 | { |
5b7baf05 CB |
838 | /* No need to flush TLB |
839 | * On s390 reference bits are in storage key and never in TLB | |
840 | * With virtualization we handle the reference bit, without we | |
841 | * we can simply return */ | |
842 | #ifdef CONFIG_PGSTE | |
843 | return ptep_test_and_clear_young(vma, address, ptep); | |
844 | #endif | |
ba8a9229 | 845 | return 0; |
1da177e4 LT |
846 | } |
847 | ||
9282ed92 | 848 | static inline void __ptep_ipte(unsigned long address, pte_t *ptep) |
1da177e4 | 849 | { |
9282ed92 | 850 | if (!(pte_val(*ptep) & _PAGE_INVALID)) { |
1da177e4 | 851 | #ifndef __s390x__ |
146e4b3c | 852 | /* pto must point to the start of the segment table */ |
1da177e4 | 853 | pte_t *pto = (pte_t *) (((unsigned long) ptep) & 0x7ffffc00); |
9282ed92 GS |
854 | #else |
855 | /* ipte in zarch mode can do the math */ | |
856 | pte_t *pto = ptep; | |
857 | #endif | |
94c12cc7 MS |
858 | asm volatile( |
859 | " ipte %2,%3" | |
860 | : "=m" (*ptep) : "m" (*ptep), | |
861 | "a" (pto), "a" (address)); | |
1da177e4 | 862 | } |
9282ed92 GS |
863 | } |
864 | ||
146e4b3c MS |
865 | static inline void ptep_invalidate(struct mm_struct *mm, |
866 | unsigned long address, pte_t *ptep) | |
9282ed92 | 867 | { |
250cf776 | 868 | if (mm->context.has_pgste) { |
5b7baf05 CB |
869 | rcp_lock(ptep); |
870 | __ptep_ipte(address, ptep); | |
871 | ptep_rcp_copy(ptep); | |
872 | pte_val(*ptep) = _PAGE_TYPE_EMPTY; | |
873 | rcp_unlock(ptep); | |
874 | return; | |
875 | } | |
9282ed92 | 876 | __ptep_ipte(address, ptep); |
5b7baf05 CB |
877 | pte_val(*ptep) = _PAGE_TYPE_EMPTY; |
878 | if (mm->context.noexec) { | |
146e4b3c | 879 | __ptep_ipte(address, ptep + PTRS_PER_PTE); |
5b7baf05 CB |
880 | pte_val(*(ptep + PTRS_PER_PTE)) = _PAGE_TYPE_EMPTY; |
881 | } | |
f0e47c22 MS |
882 | } |
883 | ||
ba8a9229 MS |
884 | /* |
885 | * This is hard to understand. ptep_get_and_clear and ptep_clear_flush | |
886 | * both clear the TLB for the unmapped pte. The reason is that | |
887 | * ptep_get_and_clear is used in common code (e.g. change_pte_range) | |
888 | * to modify an active pte. The sequence is | |
889 | * 1) ptep_get_and_clear | |
890 | * 2) set_pte_at | |
891 | * 3) flush_tlb_range | |
892 | * On s390 the tlb needs to get flushed with the modification of the pte | |
893 | * if the pte is active. The only way how this can be implemented is to | |
894 | * have ptep_get_and_clear do the tlb flush. In exchange flush_tlb_range | |
895 | * is a nop. | |
896 | */ | |
897 | #define __HAVE_ARCH_PTEP_GET_AND_CLEAR | |
898 | #define ptep_get_and_clear(__mm, __address, __ptep) \ | |
899 | ({ \ | |
900 | pte_t __pte = *(__ptep); \ | |
050eef36 MS |
901 | (__mm)->context.flush_mm = 1; \ |
902 | if (atomic_read(&(__mm)->context.attach_count) > 1 || \ | |
ba8a9229 | 903 | (__mm) != current->active_mm) \ |
146e4b3c | 904 | ptep_invalidate(__mm, __address, __ptep); \ |
ba8a9229 MS |
905 | else \ |
906 | pte_clear((__mm), (__address), (__ptep)); \ | |
907 | __pte; \ | |
908 | }) | |
909 | ||
910 | #define __HAVE_ARCH_PTEP_CLEAR_FLUSH | |
f0e47c22 MS |
911 | static inline pte_t ptep_clear_flush(struct vm_area_struct *vma, |
912 | unsigned long address, pte_t *ptep) | |
913 | { | |
914 | pte_t pte = *ptep; | |
146e4b3c | 915 | ptep_invalidate(vma->vm_mm, address, ptep); |
1da177e4 LT |
916 | return pte; |
917 | } | |
918 | ||
ba8a9229 MS |
919 | /* |
920 | * The batched pte unmap code uses ptep_get_and_clear_full to clear the | |
921 | * ptes. Here an optimization is possible. tlb_gather_mmu flushes all | |
922 | * tlbs of an mm if it can guarantee that the ptes of the mm_struct | |
923 | * cannot be accessed while the batched unmap is running. In this case | |
924 | * full==1 and a simple pte_clear is enough. See tlb.h. | |
925 | */ | |
926 | #define __HAVE_ARCH_PTEP_GET_AND_CLEAR_FULL | |
927 | static inline pte_t ptep_get_and_clear_full(struct mm_struct *mm, | |
928 | unsigned long addr, | |
929 | pte_t *ptep, int full) | |
1da177e4 | 930 | { |
ba8a9229 MS |
931 | pte_t pte = *ptep; |
932 | ||
933 | if (full) | |
934 | pte_clear(mm, addr, ptep); | |
935 | else | |
146e4b3c | 936 | ptep_invalidate(mm, addr, ptep); |
ba8a9229 | 937 | return pte; |
1da177e4 LT |
938 | } |
939 | ||
ba8a9229 MS |
940 | #define __HAVE_ARCH_PTEP_SET_WRPROTECT |
941 | #define ptep_set_wrprotect(__mm, __addr, __ptep) \ | |
942 | ({ \ | |
943 | pte_t __pte = *(__ptep); \ | |
944 | if (pte_write(__pte)) { \ | |
050eef36 MS |
945 | (__mm)->context.flush_mm = 1; \ |
946 | if (atomic_read(&(__mm)->context.attach_count) > 1 || \ | |
ba8a9229 | 947 | (__mm) != current->active_mm) \ |
146e4b3c | 948 | ptep_invalidate(__mm, __addr, __ptep); \ |
ba8a9229 MS |
949 | set_pte_at(__mm, __addr, __ptep, pte_wrprotect(__pte)); \ |
950 | } \ | |
951 | }) | |
952 | ||
953 | #define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS | |
f0e47c22 MS |
954 | #define ptep_set_access_flags(__vma, __addr, __ptep, __entry, __dirty) \ |
955 | ({ \ | |
956 | int __changed = !pte_same(*(__ptep), __entry); \ | |
957 | if (__changed) { \ | |
146e4b3c | 958 | ptep_invalidate((__vma)->vm_mm, __addr, __ptep); \ |
f0e47c22 MS |
959 | set_pte_at((__vma)->vm_mm, __addr, __ptep, __entry); \ |
960 | } \ | |
961 | __changed; \ | |
8dab5241 | 962 | }) |
1da177e4 LT |
963 | |
964 | /* | |
965 | * Test and clear dirty bit in storage key. | |
966 | * We can't clear the changed bit atomically. This is a potential | |
967 | * race against modification of the referenced bit. This function | |
968 | * should therefore only be called if it is not mapped in any | |
969 | * address space. | |
970 | */ | |
ba8a9229 | 971 | #define __HAVE_ARCH_PAGE_TEST_DIRTY |
6c210482 | 972 | static inline int page_test_dirty(struct page *page) |
2dcea57a | 973 | { |
6c210482 MS |
974 | return (page_get_storage_key(page_to_phys(page)) & _PAGE_CHANGED) != 0; |
975 | } | |
2dcea57a | 976 | |
ba8a9229 | 977 | #define __HAVE_ARCH_PAGE_CLEAR_DIRTY |
e2b8d7af | 978 | static inline void page_clear_dirty(struct page *page, int mapped) |
6c210482 | 979 | { |
e2b8d7af | 980 | page_set_storage_key(page_to_phys(page), PAGE_DEFAULT_KEY, mapped); |
2dcea57a | 981 | } |
1da177e4 LT |
982 | |
983 | /* | |
984 | * Test and clear referenced bit in storage key. | |
985 | */ | |
ba8a9229 | 986 | #define __HAVE_ARCH_PAGE_TEST_AND_CLEAR_YOUNG |
2dcea57a HC |
987 | static inline int page_test_and_clear_young(struct page *page) |
988 | { | |
0b2b6e1d | 989 | unsigned long physpage = page_to_phys(page); |
2dcea57a HC |
990 | int ccode; |
991 | ||
0b2b6e1d HC |
992 | asm volatile( |
993 | " rrbe 0,%1\n" | |
994 | " ipm %0\n" | |
995 | " srl %0,28\n" | |
2dcea57a HC |
996 | : "=d" (ccode) : "a" (physpage) : "cc" ); |
997 | return ccode & 2; | |
998 | } | |
1da177e4 LT |
999 | |
1000 | /* | |
1001 | * Conversion functions: convert a page and protection to a page entry, | |
1002 | * and a page entry and page directory to the page they refer to. | |
1003 | */ | |
1004 | static inline pte_t mk_pte_phys(unsigned long physpage, pgprot_t pgprot) | |
1005 | { | |
1006 | pte_t __pte; | |
1007 | pte_val(__pte) = physpage + pgprot_val(pgprot); | |
1008 | return __pte; | |
1009 | } | |
1010 | ||
2dcea57a HC |
1011 | static inline pte_t mk_pte(struct page *page, pgprot_t pgprot) |
1012 | { | |
0b2b6e1d | 1013 | unsigned long physpage = page_to_phys(page); |
1da177e4 | 1014 | |
2dcea57a HC |
1015 | return mk_pte_phys(physpage, pgprot); |
1016 | } | |
1017 | ||
190a1d72 MS |
1018 | #define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD-1)) |
1019 | #define pud_index(address) (((address) >> PUD_SHIFT) & (PTRS_PER_PUD-1)) | |
1020 | #define pmd_index(address) (((address) >> PMD_SHIFT) & (PTRS_PER_PMD-1)) | |
1021 | #define pte_index(address) (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE-1)) | |
1da177e4 | 1022 | |
190a1d72 MS |
1023 | #define pgd_offset(mm, address) ((mm)->pgd + pgd_index(address)) |
1024 | #define pgd_offset_k(address) pgd_offset(&init_mm, address) | |
1da177e4 | 1025 | |
190a1d72 | 1026 | #ifndef __s390x__ |
1da177e4 | 1027 | |
190a1d72 MS |
1028 | #define pmd_deref(pmd) (pmd_val(pmd) & _SEGMENT_ENTRY_ORIGIN) |
1029 | #define pud_deref(pmd) ({ BUG(); 0UL; }) | |
1030 | #define pgd_deref(pmd) ({ BUG(); 0UL; }) | |
46a82b2d | 1031 | |
190a1d72 MS |
1032 | #define pud_offset(pgd, address) ((pud_t *) pgd) |
1033 | #define pmd_offset(pud, address) ((pmd_t *) pud + pmd_index(address)) | |
1da177e4 | 1034 | |
190a1d72 | 1035 | #else /* __s390x__ */ |
1da177e4 | 1036 | |
190a1d72 MS |
1037 | #define pmd_deref(pmd) (pmd_val(pmd) & _SEGMENT_ENTRY_ORIGIN) |
1038 | #define pud_deref(pud) (pud_val(pud) & _REGION_ENTRY_ORIGIN) | |
5a216a20 | 1039 | #define pgd_deref(pgd) (pgd_val(pgd) & _REGION_ENTRY_ORIGIN) |
1da177e4 | 1040 | |
5a216a20 MS |
1041 | static inline pud_t *pud_offset(pgd_t *pgd, unsigned long address) |
1042 | { | |
6252d702 MS |
1043 | pud_t *pud = (pud_t *) pgd; |
1044 | if ((pgd_val(*pgd) & _REGION_ENTRY_TYPE_MASK) == _REGION_ENTRY_TYPE_R2) | |
1045 | pud = (pud_t *) pgd_deref(*pgd); | |
5a216a20 MS |
1046 | return pud + pud_index(address); |
1047 | } | |
1da177e4 | 1048 | |
190a1d72 | 1049 | static inline pmd_t *pmd_offset(pud_t *pud, unsigned long address) |
1da177e4 | 1050 | { |
6252d702 MS |
1051 | pmd_t *pmd = (pmd_t *) pud; |
1052 | if ((pud_val(*pud) & _REGION_ENTRY_TYPE_MASK) == _REGION_ENTRY_TYPE_R3) | |
1053 | pmd = (pmd_t *) pud_deref(*pud); | |
190a1d72 | 1054 | return pmd + pmd_index(address); |
1da177e4 LT |
1055 | } |
1056 | ||
190a1d72 | 1057 | #endif /* __s390x__ */ |
1da177e4 | 1058 | |
190a1d72 MS |
1059 | #define pfn_pte(pfn,pgprot) mk_pte_phys(__pa((pfn) << PAGE_SHIFT),(pgprot)) |
1060 | #define pte_pfn(x) (pte_val(x) >> PAGE_SHIFT) | |
1061 | #define pte_page(x) pfn_to_page(pte_pfn(x)) | |
1da177e4 | 1062 | |
190a1d72 | 1063 | #define pmd_page(pmd) pfn_to_page(pmd_val(pmd) >> PAGE_SHIFT) |
1da177e4 | 1064 | |
190a1d72 MS |
1065 | /* Find an entry in the lowest level page table.. */ |
1066 | #define pte_offset(pmd, addr) ((pte_t *) pmd_deref(*(pmd)) + pte_index(addr)) | |
1067 | #define pte_offset_kernel(pmd, address) pte_offset(pmd,address) | |
1da177e4 LT |
1068 | #define pte_offset_map(pmd, address) pte_offset_kernel(pmd, address) |
1069 | #define pte_offset_map_nested(pmd, address) pte_offset_kernel(pmd, address) | |
1070 | #define pte_unmap(pte) do { } while (0) | |
1071 | #define pte_unmap_nested(pte) do { } while (0) | |
1072 | ||
1073 | /* | |
1074 | * 31 bit swap entry format: | |
1075 | * A page-table entry has some bits we have to treat in a special way. | |
1076 | * Bits 0, 20 and bit 23 have to be zero, otherwise an specification | |
1077 | * exception will occur instead of a page translation exception. The | |
1078 | * specifiation exception has the bad habit not to store necessary | |
1079 | * information in the lowcore. | |
1080 | * Bit 21 and bit 22 are the page invalid bit and the page protection | |
1081 | * bit. We set both to indicate a swapped page. | |
1082 | * Bit 30 and 31 are used to distinguish the different page types. For | |
1083 | * a swapped page these bits need to be zero. | |
1084 | * This leaves the bits 1-19 and bits 24-29 to store type and offset. | |
1085 | * We use the 5 bits from 25-29 for the type and the 20 bits from 1-19 | |
1086 | * plus 24 for the offset. | |
1087 | * 0| offset |0110|o|type |00| | |
1088 | * 0 0000000001111111111 2222 2 22222 33 | |
1089 | * 0 1234567890123456789 0123 4 56789 01 | |
1090 | * | |
1091 | * 64 bit swap entry format: | |
1092 | * A page-table entry has some bits we have to treat in a special way. | |
1093 | * Bits 52 and bit 55 have to be zero, otherwise an specification | |
1094 | * exception will occur instead of a page translation exception. The | |
1095 | * specifiation exception has the bad habit not to store necessary | |
1096 | * information in the lowcore. | |
1097 | * Bit 53 and bit 54 are the page invalid bit and the page protection | |
1098 | * bit. We set both to indicate a swapped page. | |
1099 | * Bit 62 and 63 are used to distinguish the different page types. For | |
1100 | * a swapped page these bits need to be zero. | |
1101 | * This leaves the bits 0-51 and bits 56-61 to store type and offset. | |
1102 | * We use the 5 bits from 57-61 for the type and the 53 bits from 0-51 | |
1103 | * plus 56 for the offset. | |
1104 | * | offset |0110|o|type |00| | |
1105 | * 0000000000111111111122222222223333333333444444444455 5555 5 55566 66 | |
1106 | * 0123456789012345678901234567890123456789012345678901 2345 6 78901 23 | |
1107 | */ | |
1108 | #ifndef __s390x__ | |
1109 | #define __SWP_OFFSET_MASK (~0UL >> 12) | |
1110 | #else | |
1111 | #define __SWP_OFFSET_MASK (~0UL >> 11) | |
1112 | #endif | |
4448aaf0 | 1113 | static inline pte_t mk_swap_pte(unsigned long type, unsigned long offset) |
1da177e4 LT |
1114 | { |
1115 | pte_t pte; | |
1116 | offset &= __SWP_OFFSET_MASK; | |
9282ed92 | 1117 | pte_val(pte) = _PAGE_TYPE_SWAP | ((type & 0x1f) << 2) | |
1da177e4 LT |
1118 | ((offset & 1UL) << 7) | ((offset & ~1UL) << 11); |
1119 | return pte; | |
1120 | } | |
1121 | ||
1122 | #define __swp_type(entry) (((entry).val >> 2) & 0x1f) | |
1123 | #define __swp_offset(entry) (((entry).val >> 11) | (((entry).val >> 7) & 1)) | |
1124 | #define __swp_entry(type,offset) ((swp_entry_t) { pte_val(mk_swap_pte((type),(offset))) }) | |
1125 | ||
1126 | #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) | |
1127 | #define __swp_entry_to_pte(x) ((pte_t) { (x).val }) | |
1128 | ||
1129 | #ifndef __s390x__ | |
1130 | # define PTE_FILE_MAX_BITS 26 | |
1131 | #else /* __s390x__ */ | |
1132 | # define PTE_FILE_MAX_BITS 59 | |
1133 | #endif /* __s390x__ */ | |
1134 | ||
1135 | #define pte_to_pgoff(__pte) \ | |
1136 | ((((__pte).pte >> 12) << 7) + (((__pte).pte >> 1) & 0x7f)) | |
1137 | ||
1138 | #define pgoff_to_pte(__off) \ | |
1139 | ((pte_t) { ((((__off) & 0x7f) << 1) + (((__off) >> 7) << 12)) \ | |
9282ed92 | 1140 | | _PAGE_TYPE_FILE }) |
1da177e4 LT |
1141 | |
1142 | #endif /* !__ASSEMBLY__ */ | |
1143 | ||
1144 | #define kern_addr_valid(addr) (1) | |
1145 | ||
17f34580 HC |
1146 | extern int vmem_add_mapping(unsigned long start, unsigned long size); |
1147 | extern int vmem_remove_mapping(unsigned long start, unsigned long size); | |
402b0862 | 1148 | extern int s390_enable_sie(void); |
f4eb07c1 | 1149 | |
1da177e4 LT |
1150 | /* |
1151 | * No page table caches to initialise | |
1152 | */ | |
1153 | #define pgtable_cache_init() do { } while (0) | |
1154 | ||
1da177e4 LT |
1155 | #include <asm-generic/pgtable.h> |
1156 | ||
1157 | #endif /* _S390_PAGE_H */ |