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mm: remove kern_addr_valid() completely
[linux-block.git] / arch / s390 / include / asm / pgtable.h
CommitLineData
b2441318 1/* SPDX-License-Identifier: GPL-2.0 */
1da177e4 2/*
1da177e4 3 * S390 version
a53c8fab 4 * Copyright IBM Corp. 1999, 2000
1da177e4
LT		 5 * Author(s): Hartmut Penner (hp@de.ibm.com)
6 * Ulrich Weigand (weigand@de.ibm.com)
7 * Martin Schwidefsky (schwidefsky@de.ibm.com)
8 *
9 * Derived from "include/asm-i386/pgtable.h"
10 */
11
12#ifndef _ASM_S390_PGTABLE_H
13#define _ASM_S390_PGTABLE_H
14
9789db08 15#include <linux/sched.h>
2dcea57a 16#include <linux/mm_types.h>
abf09bed 17#include <linux/page-flags.h>
527e30b4 18#include <linux/radix-tree.h>
37cd944c 19#include <linux/atomic.h>
0c4f2623 20#include <asm/sections.h>
1da177e4 21#include <asm/bug.h>
b2fa47e6 22#include <asm/page.h>
214d9bbc 23#include <asm/uv.h>
1da177e4 24
0ccb32c9 25extern pgd_t swapper_pg_dir[];
1da177e4 26extern void paging_init(void);
0290c9e3 27extern unsigned long s390_invalid_asce;
1da177e4 28
37cd944c
HC		 29enum {
30 PG_DIRECT_MAP_4K = 0,
31 PG_DIRECT_MAP_1M,
32 PG_DIRECT_MAP_2G,
33 PG_DIRECT_MAP_MAX
34};
35
36extern atomic_long_t direct_pages_count[PG_DIRECT_MAP_MAX];
37
38static inline void update_page_count(int level, long count)
39{
40 if (IS_ENABLED(CONFIG_PROC_FS))
41 atomic_long_add(count, &direct_pages_count[level]);
42}
43
44struct seq_file;
45void arch_report_meminfo(struct seq_file *m);
46
1da177e4
LT		 47/*
48 * The S390 doesn't have any external MMU info: the kernel page
49 * tables contain all the necessary information.
50 */
4b3073e1 51#define update_mmu_cache(vma, address, ptep) do { } while (0)
b113da65 52#define update_mmu_cache_pmd(vma, address, ptep) do { } while (0)
1da177e4
LT		 53
54/*
238ec4ef 55 * ZERO_PAGE is a global shared page that is always zero; used
1da177e4
LT		 56 * for zero-mapped memory areas etc..
57 */
238ec4ef
MS		 58
59extern unsigned long empty_zero_page;
60extern unsigned long zero_page_mask;
61
62#define ZERO_PAGE(vaddr) \
63 (virt_to_page((void *)(empty_zero_page + \
64 (((unsigned long)(vaddr)) &zero_page_mask))))
816422ad 65#define __HAVE_COLOR_ZERO_PAGE
238ec4ef 66
4f2e2903 67/* TODO: s390 cannot support io_remap_pfn_range... */
1da177e4 68
1da177e4 69#define pte_ERROR(e) \
bb50655b 70 pr_err("%s:%d: bad pte %016lx.\n", __FILE__, __LINE__, pte_val(e))
1da177e4 71#define pmd_ERROR(e) \
bb50655b 72 pr_err("%s:%d: bad pmd %016lx.\n", __FILE__, __LINE__, pmd_val(e))
190a1d72 73#define pud_ERROR(e) \
bb50655b 74 pr_err("%s:%d: bad pud %016lx.\n", __FILE__, __LINE__, pud_val(e))
1aea9b3f 75#define p4d_ERROR(e) \
bb50655b 76 pr_err("%s:%d: bad p4d %016lx.\n", __FILE__, __LINE__, p4d_val(e))
1da177e4 77#define pgd_ERROR(e) \
bb50655b 78 pr_err("%s:%d: bad pgd %016lx.\n", __FILE__, __LINE__, pgd_val(e))
1da177e4 79
1da177e4 80/*
a1c843b8 81 * The vmalloc and module area will always be on the topmost area of the
fc67c880
HC		 82 * kernel mapping. 512GB are reserved for vmalloc by default.
83 * At the top of the vmalloc area a 2GB area is reserved where modules
84 * will reside. That makes sure that inter module branches always
85 * happen without trampolines and in addition the placement within a
86 * 2GB frame is branch prediction unit friendly.
8b62bc96 87 */
0c4f2623
VG		 88extern unsigned long __bootdata_preserved(VMALLOC_START);
89extern unsigned long __bootdata_preserved(VMALLOC_END);
fc67c880 90#define VMALLOC_DEFAULT_SIZE ((512UL << 30) - MODULES_LEN)
0c4f2623
VG		 91extern struct page *__bootdata_preserved(vmemmap);
92extern unsigned long __bootdata_preserved(vmemmap_size);
239a6425 93
14045ebf 94#define VMEM_MAX_PHYS ((unsigned long) vmemmap)
5fd9c6e2 95
0c4f2623
VG		 96extern unsigned long __bootdata_preserved(MODULES_VADDR);
97extern unsigned long __bootdata_preserved(MODULES_END);
c972cc60
HC		 98#define MODULES_VADDR MODULES_VADDR
99#define MODULES_END MODULES_END
100#define MODULES_LEN (1UL << 31)
c972cc60 101
c933146a
HC		 102static inline int is_module_addr(void *addr)
103{
c933146a
HC		 104 BUILD_BUG_ON(MODULES_LEN > (1UL << 31));
105 if (addr < (void *)MODULES_VADDR)
106 return 0;
107 if (addr > (void *)MODULES_END)
108 return 0;
c933146a
HC		 109 return 1;
110}
111
1da177e4 112/*
1da177e4 113 * A 64 bit pagetable entry of S390 has following format:
6a985c61 114 * | PFRA |0IPC| OS |
1da177e4
LT		 115 * 0000000000111111111122222222223333333333444444444455555555556666
116 * 0123456789012345678901234567890123456789012345678901234567890123
117 *
118 * I Page-Invalid Bit: Page is not available for address-translation
119 * P Page-Protection Bit: Store access not possible for page
6a985c61 120 * C Change-bit override: HW is not required to set change bit
1da177e4
LT		 121 *
122 * A 64 bit segmenttable entry of S390 has following format:
123 * | P-table origin | TT
124 * 0000000000111111111122222222223333333333444444444455555555556666
125 * 0123456789012345678901234567890123456789012345678901234567890123
126 *
127 * I Segment-Invalid Bit: Segment is not available for address-translation
128 * C Common-Segment Bit: Segment is not private (PoP 3-30)
129 * P Page-Protection Bit: Store access not possible for page
130 * TT Type 00
131 *
132 * A 64 bit region table entry of S390 has following format:
133 * | S-table origin | TF TTTL
134 * 0000000000111111111122222222223333333333444444444455555555556666
135 * 0123456789012345678901234567890123456789012345678901234567890123
136 *
137 * I Segment-Invalid Bit: Segment is not available for address-translation
138 * TT Type 01
139 * TF
190a1d72 140 * TL Table length
1da177e4
LT		 141 *
142 * The 64 bit regiontable origin of S390 has following format:
143 * | region table origon | DTTL
144 * 0000000000111111111122222222223333333333444444444455555555556666
145 * 0123456789012345678901234567890123456789012345678901234567890123
146 *
147 * X Space-Switch event:
148 * G Segment-Invalid Bit:
149 * P Private-Space Bit:
150 * S Storage-Alteration:
151 * R Real space
152 * TL Table-Length:
153 *
154 * A storage key has the following format:
155 * | ACC |F|R|C|0|
156 * 0 3 4 5 6 7
157 * ACC: access key
158 * F : fetch protection bit
159 * R : referenced bit
160 * C : changed bit
161 */
162
163/* Hardware bits in the page table entry */
57d7f939 164#define _PAGE_NOEXEC 0x100 /* HW no-execute bit */
e5098611 165#define _PAGE_PROTECT 0x200 /* HW read-only bit */
83377484 166#define _PAGE_INVALID 0x400 /* HW invalid bit */
e5098611 167#define _PAGE_LARGE 0x800 /* Bit to mark a large pte */
3610cce8
MS		 168
169/* Software bits in the page table entry */
e5098611 170#define _PAGE_PRESENT 0x001 /* SW pte present bit */
e5098611
MS		 171#define _PAGE_YOUNG 0x004 /* SW pte young bit */
172#define _PAGE_DIRTY 0x008 /* SW pte dirty bit */
0944fe3f
MS		 173#define _PAGE_READ 0x010 /* SW pte read bit */
174#define _PAGE_WRITE 0x020 /* SW pte write bit */
175#define _PAGE_SPECIAL 0x040 /* SW associated with special page */
b31288fa 176#define _PAGE_UNUSED 0x080 /* SW bit for pgste usage state */
1da177e4 177
5614dd92
MS		 178#ifdef CONFIG_MEM_SOFT_DIRTY
179#define _PAGE_SOFT_DIRTY 0x002 /* SW pte soft dirty bit */
180#else
181#define _PAGE_SOFT_DIRTY 0x000
182#endif
183
92cd58bd
DH		 184#define _PAGE_SWP_EXCLUSIVE _PAGE_LARGE /* SW pte exclusive swap bit */
185
138c9021 186/* Set of bits not changed in pte_modify */
6a5c1482 187#define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_SPECIAL | _PAGE_DIRTY | \
5614dd92 188 _PAGE_YOUNG | _PAGE_SOFT_DIRTY)
53492b1d 189
83377484 190/*
6e76d4b2
KS		 191 * handle_pte_fault uses pte_present and pte_none to find out the pte type
192 * WITHOUT holding the page table lock. The _PAGE_PRESENT bit is used to
193 * distinguish present from not-present ptes. It is changed only with the page
194 * table lock held.
83377484 195 *
e5098611 196 * The following table gives the different possible bit combinations for
a1c843b8
MS		 197 * the pte hardware and software bits in the last 12 bits of a pte
198 * (. unassigned bit, x don't care, t swap type):
83377484 199 *
0944fe3f
MS		 200 * 842100000000
201 * 000084210000
202 * 000000008421
a1c843b8
MS		 203 * .IR.uswrdy.p
204 * empty .10.00000000
205 * swap .11..ttttt.0
206 * prot-none, clean, old .11.xx0000.1
207 * prot-none, clean, young .11.xx0001.1
bc29b7ac
GS		 208 * prot-none, dirty, old .11.xx0010.1
209 * prot-none, dirty, young .11.xx0011.1
a1c843b8
MS		 210 * read-only, clean, old .11.xx0100.1
211 * read-only, clean, young .01.xx0101.1
212 * read-only, dirty, old .11.xx0110.1
213 * read-only, dirty, young .01.xx0111.1
214 * read-write, clean, old .11.xx1100.1
215 * read-write, clean, young .01.xx1101.1
216 * read-write, dirty, old .10.xx1110.1
217 * read-write, dirty, young .00.xx1111.1
218 * HW-bits: R read-only, I invalid
219 * SW-bits: p present, y young, d dirty, r read, w write, s special,
220 * u unused, l large
e5098611 221 *
a1c843b8
MS		 222 * pte_none is true for the bit pattern .10.00000000, pte == 0x400
223 * pte_swap is true for the bit pattern .11..ooooo.0, (pte & 0x201) == 0x200
224 * pte_present is true for the bit pattern .xx.xxxxxx.1, (pte & 0x001) == 0x001
83377484
MS		 225 */
226
3610cce8 227/* Bits in the segment/region table address-space-control-element */
8457d775 228#define _ASCE_ORIGIN ~0xfffUL/* region/segment table origin */
3610cce8
MS		 229#define _ASCE_PRIVATE_SPACE 0x100 /* private space control */
230#define _ASCE_ALT_EVENT 0x80 /* storage alteration event control */
231#define _ASCE_SPACE_SWITCH 0x40 /* space switch event */
232#define _ASCE_REAL_SPACE 0x20 /* real space control */
233#define _ASCE_TYPE_MASK 0x0c /* asce table type mask */
234#define _ASCE_TYPE_REGION1 0x0c /* region first table type */
235#define _ASCE_TYPE_REGION2 0x08 /* region second table type */
236#define _ASCE_TYPE_REGION3 0x04 /* region third table type */
237#define _ASCE_TYPE_SEGMENT 0x00 /* segment table type */
238#define _ASCE_TABLE_LENGTH 0x03 /* region table length */
239
240/* Bits in the region table entry */
241#define _REGION_ENTRY_ORIGIN ~0xfffUL/* region/segment table origin */
e5098611 242#define _REGION_ENTRY_PROTECT 0x200 /* region protection bit */
57d7f939 243#define _REGION_ENTRY_NOEXEC 0x100 /* region no-execute bit */
4be130a0 244#define _REGION_ENTRY_OFFSET 0xc0 /* region table offset */
e5098611 245#define _REGION_ENTRY_INVALID 0x20 /* invalid region table entry */
c9f62152 246#define _REGION_ENTRY_TYPE_MASK 0x0c /* region table type mask */
3610cce8
MS		 247#define _REGION_ENTRY_TYPE_R1 0x0c /* region first table type */
248#define _REGION_ENTRY_TYPE_R2 0x08 /* region second table type */
249#define _REGION_ENTRY_TYPE_R3 0x04 /* region third table type */
250#define _REGION_ENTRY_LENGTH 0x03 /* region third length */
251
252#define _REGION1_ENTRY (_REGION_ENTRY_TYPE_R1 | _REGION_ENTRY_LENGTH)
e5098611 253#define _REGION1_ENTRY_EMPTY (_REGION_ENTRY_TYPE_R1 | _REGION_ENTRY_INVALID)
3610cce8 254#define _REGION2_ENTRY (_REGION_ENTRY_TYPE_R2 | _REGION_ENTRY_LENGTH)
e5098611 255#define _REGION2_ENTRY_EMPTY (_REGION_ENTRY_TYPE_R2 | _REGION_ENTRY_INVALID)
3610cce8 256#define _REGION3_ENTRY (_REGION_ENTRY_TYPE_R3 | _REGION_ENTRY_LENGTH)
e5098611 257#define _REGION3_ENTRY_EMPTY (_REGION_ENTRY_TYPE_R3 | _REGION_ENTRY_INVALID)
3610cce8 258
9e20b4da 259#define _REGION3_ENTRY_ORIGIN_LARGE ~0x7fffffffUL /* large page address */
2dffdcba
HC		 260#define _REGION3_ENTRY_DIRTY 0x2000 /* SW region dirty bit */
261#define _REGION3_ENTRY_YOUNG 0x1000 /* SW region young bit */
262#define _REGION3_ENTRY_LARGE 0x0400 /* RTTE-format control, large page */
263#define _REGION3_ENTRY_READ 0x0002 /* SW region read bit */
264#define _REGION3_ENTRY_WRITE 0x0001 /* SW region write bit */
265
266#ifdef CONFIG_MEM_SOFT_DIRTY
267#define _REGION3_ENTRY_SOFT_DIRTY 0x4000 /* SW region soft dirty bit */
268#else
269#define _REGION3_ENTRY_SOFT_DIRTY 0x0000 /* SW region soft dirty bit */
270#endif
271
1aea9b3f 272#define _REGION_ENTRY_BITS 0xfffffffffffff22fUL
d08de8e2 273
1da177e4 274/* Bits in the segment table entry */
58b7e200 275#define _SEGMENT_ENTRY_BITS 0xfffffffffffffe33UL
58b7e200
JF		 276#define _SEGMENT_ENTRY_HARDWARE_BITS 0xfffffffffffffe30UL
277#define _SEGMENT_ENTRY_HARDWARE_BITS_LARGE 0xfffffffffff00730UL
ea81531d 278#define _SEGMENT_ENTRY_ORIGIN_LARGE ~0xfffffUL /* large page address */
8457d775
HC		 279#define _SEGMENT_ENTRY_ORIGIN ~0x7ffUL/* page table origin */
280#define _SEGMENT_ENTRY_PROTECT 0x200 /* segment protection bit */
281#define _SEGMENT_ENTRY_NOEXEC 0x100 /* segment no-execute bit */
e5098611 282#define _SEGMENT_ENTRY_INVALID 0x20 /* invalid segment table entry */
c9f62152 283#define _SEGMENT_ENTRY_TYPE_MASK 0x0c /* segment table type mask */
1da177e4 284
3610cce8 285#define _SEGMENT_ENTRY (0)
e5098611 286#define _SEGMENT_ENTRY_EMPTY (_SEGMENT_ENTRY_INVALID)
3610cce8 287
152125b7
MS		 288#define _SEGMENT_ENTRY_DIRTY 0x2000 /* SW segment dirty bit */
289#define _SEGMENT_ENTRY_YOUNG 0x1000 /* SW segment young bit */
152125b7 290#define _SEGMENT_ENTRY_LARGE 0x0400 /* STE-format control, large page */
bc29b7ac
GS		 291#define _SEGMENT_ENTRY_WRITE 0x0002 /* SW segment write bit */
292#define _SEGMENT_ENTRY_READ 0x0001 /* SW segment read bit */
0944fe3f 293
5614dd92
MS		 294#ifdef CONFIG_MEM_SOFT_DIRTY
295#define _SEGMENT_ENTRY_SOFT_DIRTY 0x4000 /* SW segment soft dirty bit */
296#else
297#define _SEGMENT_ENTRY_SOFT_DIRTY 0x0000 /* SW segment soft dirty bit */
298#endif
299
c67da7c7
HC		 300#define _CRST_ENTRIES 2048 /* number of region/segment table entries */
301#define _PAGE_ENTRIES 256 /* number of page table entries */
302
303#define _CRST_TABLE_SIZE (_CRST_ENTRIES * 8)
304#define _PAGE_TABLE_SIZE (_PAGE_ENTRIES * 8)
305
306#define _REGION1_SHIFT 53
307#define _REGION2_SHIFT 42
308#define _REGION3_SHIFT 31
309#define _SEGMENT_SHIFT 20
310
311#define _REGION1_INDEX (0x7ffUL << _REGION1_SHIFT)
312#define _REGION2_INDEX (0x7ffUL << _REGION2_SHIFT)
313#define _REGION3_INDEX (0x7ffUL << _REGION3_SHIFT)
314#define _SEGMENT_INDEX (0x7ffUL << _SEGMENT_SHIFT)
315#define _PAGE_INDEX (0xffUL << _PAGE_SHIFT)
316
317#define _REGION1_SIZE (1UL << _REGION1_SHIFT)
318#define _REGION2_SIZE (1UL << _REGION2_SHIFT)
319#define _REGION3_SIZE (1UL << _REGION3_SHIFT)
320#define _SEGMENT_SIZE (1UL << _SEGMENT_SHIFT)
321
322#define _REGION1_MASK (~(_REGION1_SIZE - 1))
323#define _REGION2_MASK (~(_REGION2_SIZE - 1))
324#define _REGION3_MASK (~(_REGION3_SIZE - 1))
325#define _SEGMENT_MASK (~(_SEGMENT_SIZE - 1))
326
327#define PMD_SHIFT _SEGMENT_SHIFT
328#define PUD_SHIFT _REGION3_SHIFT
329#define P4D_SHIFT _REGION2_SHIFT
330#define PGDIR_SHIFT _REGION1_SHIFT
331
332#define PMD_SIZE _SEGMENT_SIZE
333#define PUD_SIZE _REGION3_SIZE
334#define P4D_SIZE _REGION2_SIZE
335#define PGDIR_SIZE _REGION1_SIZE
336
337#define PMD_MASK _SEGMENT_MASK
338#define PUD_MASK _REGION3_MASK
339#define P4D_MASK _REGION2_MASK
340#define PGDIR_MASK _REGION1_MASK
341
342#define PTRS_PER_PTE _PAGE_ENTRIES
343#define PTRS_PER_PMD _CRST_ENTRIES
344#define PTRS_PER_PUD _CRST_ENTRIES
345#define PTRS_PER_P4D _CRST_ENTRIES
346#define PTRS_PER_PGD _CRST_ENTRIES
347
0944fe3f 348/*
2dffdcba
HC		 349 * Segment table and region3 table entry encoding
350 * (R = read-only, I = invalid, y = young bit):
bc29b7ac 351 * dy..R...I...wr
152125b7
MS		 352 * prot-none, clean, old 00..1...1...00
353 * prot-none, clean, young 01..1...1...00
354 * prot-none, dirty, old 10..1...1...00
355 * prot-none, dirty, young 11..1...1...00
bc29b7ac
GS		 356 * read-only, clean, old 00..1...1...01
357 * read-only, clean, young 01..1...0...01
358 * read-only, dirty, old 10..1...1...01
359 * read-only, dirty, young 11..1...0...01
152125b7
MS		 360 * read-write, clean, old 00..1...1...11
361 * read-write, clean, young 01..1...0...11
362 * read-write, dirty, old 10..0...1...11
363 * read-write, dirty, young 11..0...0...11
0944fe3f
MS		 364 * The segment table origin is used to distinguish empty (origin==0) from
365 * read-write, old segment table entries (origin!=0)
a1c843b8
MS		 366 * HW-bits: R read-only, I invalid
367 * SW-bits: y young, d dirty, r read, w write
0944fe3f 368 */
e5098611 369
6c61cfe9 370/* Page status table bits for virtualization */
0d0dafc1
MS		 371#define PGSTE_ACC_BITS 0xf000000000000000UL
372#define PGSTE_FP_BIT 0x0800000000000000UL
373#define PGSTE_PCL_BIT 0x0080000000000000UL
374#define PGSTE_HR_BIT 0x0040000000000000UL
375#define PGSTE_HC_BIT 0x0020000000000000UL
376#define PGSTE_GR_BIT 0x0004000000000000UL
377#define PGSTE_GC_BIT 0x0002000000000000UL
0a61b222
MS		 378#define PGSTE_UC_BIT 0x0000800000000000UL /* user dirty (migration) */
379#define PGSTE_IN_BIT 0x0000400000000000UL /* IPTE notify bit */
4be130a0 380#define PGSTE_VSIE_BIT 0x0000200000000000UL /* ref'd in a shadow table */
6c61cfe9 381
b31288fa 382/* Guest Page State used for virtualization */
2d42f947 383#define _PGSTE_GPS_ZERO 0x0000000080000000UL
cd774b90 384#define _PGSTE_GPS_NODAT 0x0000000040000000UL
2d42f947
CI		 385#define _PGSTE_GPS_USAGE_MASK 0x0000000003000000UL
386#define _PGSTE_GPS_USAGE_STABLE 0x0000000000000000UL
387#define _PGSTE_GPS_USAGE_UNUSED 0x0000000001000000UL
388#define _PGSTE_GPS_USAGE_POT_VOLATILE 0x0000000002000000UL
389#define _PGSTE_GPS_USAGE_VOLATILE _PGSTE_GPS_USAGE_MASK
b31288fa 390
1da177e4 391/*
3610cce8
MS		 392 * A user page table pointer has the space-switch-event bit, the
393 * private-space-control bit and the storage-alteration-event-control
394 * bit set. A kernel page table pointer doesn't need them.
1da177e4 395 */
3610cce8
MS		 396#define _ASCE_USER_BITS (_ASCE_SPACE_SWITCH | _ASCE_PRIVATE_SPACE | \
397 _ASCE_ALT_EVENT)
1da177e4 398
1da177e4 399/*
9282ed92 400 * Page protection definitions.
1da177e4 401 */
bc29b7ac 402#define PAGE_NONE __pgprot(_PAGE_PRESENT | _PAGE_INVALID | _PAGE_PROTECT)
57d7f939
MS		 403#define PAGE_RO __pgprot(_PAGE_PRESENT | _PAGE_READ | \
404 _PAGE_NOEXEC | _PAGE_INVALID | _PAGE_PROTECT)
405#define PAGE_RX __pgprot(_PAGE_PRESENT | _PAGE_READ | \
0944fe3f 406 _PAGE_INVALID | _PAGE_PROTECT)
57d7f939
MS		 407#define PAGE_RW __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \
408 _PAGE_NOEXEC | _PAGE_INVALID | _PAGE_PROTECT)
409#define PAGE_RWX __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \
0944fe3f
MS		 410 _PAGE_INVALID | _PAGE_PROTECT)
411
412#define PAGE_SHARED __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \
57d7f939 413 _PAGE_YOUNG | _PAGE_DIRTY | _PAGE_NOEXEC)
0944fe3f 414#define PAGE_KERNEL __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \
57d7f939 415 _PAGE_YOUNG | _PAGE_DIRTY | _PAGE_NOEXEC)
0944fe3f 416#define PAGE_KERNEL_RO __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_YOUNG | \
57d7f939
MS		 417 _PAGE_PROTECT | _PAGE_NOEXEC)
418#define PAGE_KERNEL_EXEC __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \
419 _PAGE_YOUNG | _PAGE_DIRTY)
1da177e4
LT		 420
421/*
043d0708
MS		 422 * On s390 the page table entry has an invalid bit and a read-only bit.
423 * Read permission implies execute permission and write permission
424 * implies read permission.
1da177e4
LT		 425 */
426 /*xwr*/
1da177e4 427
106c992a
GS		 428/*
429 * Segment entry (large page) protection definitions.
430 */
e5098611
MS		 431#define SEGMENT_NONE __pgprot(_SEGMENT_ENTRY_INVALID | \
432 _SEGMENT_ENTRY_PROTECT)
57d7f939
MS		 433#define SEGMENT_RO __pgprot(_SEGMENT_ENTRY_PROTECT | \
434 _SEGMENT_ENTRY_READ | \
435 _SEGMENT_ENTRY_NOEXEC)
436#define SEGMENT_RX __pgprot(_SEGMENT_ENTRY_PROTECT | \
152125b7 437 _SEGMENT_ENTRY_READ)
57d7f939
MS		 438#define SEGMENT_RW __pgprot(_SEGMENT_ENTRY_READ | \
439 _SEGMENT_ENTRY_WRITE | \
440 _SEGMENT_ENTRY_NOEXEC)
441#define SEGMENT_RWX __pgprot(_SEGMENT_ENTRY_READ | \
152125b7 442 _SEGMENT_ENTRY_WRITE)
2dffdcba
HC		 443#define SEGMENT_KERNEL __pgprot(_SEGMENT_ENTRY | \
444 _SEGMENT_ENTRY_LARGE | \
445 _SEGMENT_ENTRY_READ | \
446 _SEGMENT_ENTRY_WRITE | \
447 _SEGMENT_ENTRY_YOUNG | \
57d7f939
MS		 448 _SEGMENT_ENTRY_DIRTY | \
449 _SEGMENT_ENTRY_NOEXEC)
2dffdcba
HC		 450#define SEGMENT_KERNEL_RO __pgprot(_SEGMENT_ENTRY | \
451 _SEGMENT_ENTRY_LARGE | \
452 _SEGMENT_ENTRY_READ | \
453 _SEGMENT_ENTRY_YOUNG | \
57d7f939
MS		 454 _SEGMENT_ENTRY_PROTECT | \
455 _SEGMENT_ENTRY_NOEXEC)
d58106c3
VG		 456#define SEGMENT_KERNEL_EXEC __pgprot(_SEGMENT_ENTRY | \
457 _SEGMENT_ENTRY_LARGE | \
458 _SEGMENT_ENTRY_READ | \
459 _SEGMENT_ENTRY_WRITE | \
460 _SEGMENT_ENTRY_YOUNG | \
461 _SEGMENT_ENTRY_DIRTY)
2dffdcba
HC		 462
463/*
464 * Region3 entry (large page) protection definitions.
465 */
466
467#define REGION3_KERNEL __pgprot(_REGION_ENTRY_TYPE_R3 | \
468 _REGION3_ENTRY_LARGE | \
469 _REGION3_ENTRY_READ | \
470 _REGION3_ENTRY_WRITE | \
471 _REGION3_ENTRY_YOUNG | \
57d7f939
MS		 472 _REGION3_ENTRY_DIRTY | \
473 _REGION_ENTRY_NOEXEC)
2dffdcba
HC		 474#define REGION3_KERNEL_RO __pgprot(_REGION_ENTRY_TYPE_R3 | \
475 _REGION3_ENTRY_LARGE | \
476 _REGION3_ENTRY_READ | \
477 _REGION3_ENTRY_YOUNG | \
57d7f939
MS		 478 _REGION_ENTRY_PROTECT | \
479 _REGION_ENTRY_NOEXEC)
106c992a 480
e12e4044
MS		 481static inline bool mm_p4d_folded(struct mm_struct *mm)
482{
483 return mm->context.asce_limit <= _REGION1_SIZE;
484}
485#define mm_p4d_folded(mm) mm_p4d_folded(mm)
486
487static inline bool mm_pud_folded(struct mm_struct *mm)
488{
489 return mm->context.asce_limit <= _REGION2_SIZE;
490}
491#define mm_pud_folded(mm) mm_pud_folded(mm)
492
493static inline bool mm_pmd_folded(struct mm_struct *mm)
494{
495 return mm->context.asce_limit <= _REGION3_SIZE;
496}
497#define mm_pmd_folded(mm) mm_pmd_folded(mm)
498
b2fa47e6
MS		 499static inline int mm_has_pgste(struct mm_struct *mm)
500{
501#ifdef CONFIG_PGSTE
502 if (unlikely(mm->context.has_pgste))
503 return 1;
504#endif
505 return 0;
506}
65eef335 507
214d9bbc
CI		 508static inline int mm_is_protected(struct mm_struct *mm)
509{
510#ifdef CONFIG_PGSTE
07fbdf7f 511 if (unlikely(atomic_read(&mm->context.protected_count)))
214d9bbc
CI		 512 return 1;
513#endif
514 return 0;
515}
516
0b46e0a3
MS		 517static inline int mm_alloc_pgste(struct mm_struct *mm)
518{
519#ifdef CONFIG_PGSTE
520 if (unlikely(mm->context.alloc_pgste))
521 return 1;
522#endif
523 return 0;
524}
525
f29111f1
HC		 526static inline pte_t clear_pte_bit(pte_t pte, pgprot_t prot)
527{
528 return __pte(pte_val(pte) & ~pgprot_val(prot));
529}
530
531static inline pte_t set_pte_bit(pte_t pte, pgprot_t prot)
532{
533 return __pte(pte_val(pte) | pgprot_val(prot));
534}
535
536static inline pmd_t clear_pmd_bit(pmd_t pmd, pgprot_t prot)
537{
538 return __pmd(pmd_val(pmd) & ~pgprot_val(prot));
539}
540
541static inline pmd_t set_pmd_bit(pmd_t pmd, pgprot_t prot)
542{
543 return __pmd(pmd_val(pmd) | pgprot_val(prot));
544}
545
546static inline pud_t clear_pud_bit(pud_t pud, pgprot_t prot)
547{
548 return __pud(pud_val(pud) & ~pgprot_val(prot));
549}
550
551static inline pud_t set_pud_bit(pud_t pud, pgprot_t prot)
552{
553 return __pud(pud_val(pud) | pgprot_val(prot));
554}
555
2faee8ff
DD		 556/*
557 * In the case that a guest uses storage keys
558 * faults should no longer be backed by zero pages
559 */
fa41ba0d 560#define mm_forbids_zeropage mm_has_pgste
55531b74 561static inline int mm_uses_skeys(struct mm_struct *mm)
65eef335
DD		 562{
563#ifdef CONFIG_PGSTE
55531b74 564 if (mm->context.uses_skeys)
65eef335
DD		 565 return 1;
566#endif
567 return 0;
568}
569
4ccccc52
HC		 570static inline void csp(unsigned int *ptr, unsigned int old, unsigned int new)
571{
53c1c250 572 union register_pair r1 = { .even = old, .odd = new, };
4ccccc52
HC		 573 unsigned long address = (unsigned long)ptr | 1;
574
575 asm volatile(
53c1c250
HC		 576 " csp %[r1],%[address]"
577 : [r1] "+&d" (r1.pair), "+m" (*ptr)
578 : [address] "d" (address)
4ccccc52
HC		 579 : "cc");
580}
581
e8a97e42
HC		 582static inline void cspg(unsigned long *ptr, unsigned long old, unsigned long new)
583{
53c1c250 584 union register_pair r1 = { .even = old, .odd = new, };
e8a97e42
HC		 585 unsigned long address = (unsigned long)ptr | 1;
586
587 asm volatile(
731efc96 588 " cspg %[r1],%[address]"
53c1c250
HC		 589 : [r1] "+&d" (r1.pair), "+m" (*ptr)
590 : [address] "d" (address)
e8a97e42
HC		 591 : "cc");
592}
593
594#define CRDTE_DTT_PAGE 0x00UL
595#define CRDTE_DTT_SEGMENT 0x10UL
596#define CRDTE_DTT_REGION3 0x14UL
597#define CRDTE_DTT_REGION2 0x18UL
598#define CRDTE_DTT_REGION1 0x1cUL
599
600static inline void crdte(unsigned long old, unsigned long new,
273cd173 601 unsigned long *table, unsigned long dtt,
e8a97e42
HC		 602 unsigned long address, unsigned long asce)
603{
53c1c250 604 union register_pair r1 = { .even = old, .odd = new, };
273cd173 605 union register_pair r2 = { .even = __pa(table) | dtt, .odd = address, };
e8a97e42 606
53c1c250
HC		 607 asm volatile(".insn rrf,0xb98f0000,%[r1],%[r2],%[asce],0"
608 : [r1] "+&d" (r1.pair)
609 : [r2] "d" (r2.pair), [asce] "a" (asce)
e8a97e42
HC		 610 : "memory", "cc");
611}
612
1da177e4 613/*
cc18b460 614 * pgd/p4d/pud/pmd/pte query functions
1da177e4 615 */
cc18b460
HC		 616static inline int pgd_folded(pgd_t pgd)
617{
618 return (pgd_val(pgd) & _REGION_ENTRY_TYPE_MASK) < _REGION_ENTRY_TYPE_R1;
619}
620
5a216a20
MS		 621static inline int pgd_present(pgd_t pgd)
622{
cc18b460 623 if (pgd_folded(pgd))
6252d702 624 return 1;
5a216a20
MS		 625 return (pgd_val(pgd) & _REGION_ENTRY_ORIGIN) != 0UL;
626}
627
628static inline int pgd_none(pgd_t pgd)
629{
cc18b460 630 if (pgd_folded(pgd))
6252d702 631 return 0;
e5098611 632 return (pgd_val(pgd) & _REGION_ENTRY_INVALID) != 0UL;
5a216a20
MS		 633}
634
635static inline int pgd_bad(pgd_t pgd)
636{
c9f62152
MS		 637 if ((pgd_val(pgd) & _REGION_ENTRY_TYPE_MASK) < _REGION_ENTRY_TYPE_R1)
638 return 0;
639 return (pgd_val(pgd) & ~_REGION_ENTRY_BITS) != 0;
5a216a20 640}
190a1d72 641
d0e2eb0a
VG		 642static inline unsigned long pgd_pfn(pgd_t pgd)
643{
644 unsigned long origin_mask;
645
646 origin_mask = _REGION_ENTRY_ORIGIN;
647 return (pgd_val(pgd) & origin_mask) >> PAGE_SHIFT;
648}
649
cc18b460
HC		 650static inline int p4d_folded(p4d_t p4d)
651{
652 return (p4d_val(p4d) & _REGION_ENTRY_TYPE_MASK) < _REGION_ENTRY_TYPE_R2;
653}
654
1aea9b3f
MS		 655static inline int p4d_present(p4d_t p4d)
656{
cc18b460 657 if (p4d_folded(p4d))
1aea9b3f
MS		 658 return 1;
659 return (p4d_val(p4d) & _REGION_ENTRY_ORIGIN) != 0UL;
660}
661
662static inline int p4d_none(p4d_t p4d)
663{
cc18b460 664 if (p4d_folded(p4d))
1aea9b3f
MS		 665 return 0;
666 return p4d_val(p4d) == _REGION2_ENTRY_EMPTY;
667}
668
669static inline unsigned long p4d_pfn(p4d_t p4d)
670{
671 unsigned long origin_mask;
672
673 origin_mask = _REGION_ENTRY_ORIGIN;
674 return (p4d_val(p4d) & origin_mask) >> PAGE_SHIFT;
675}
676
cc18b460
HC		 677static inline int pud_folded(pud_t pud)
678{
679 return (pud_val(pud) & _REGION_ENTRY_TYPE_MASK) < _REGION_ENTRY_TYPE_R3;
680}
681
190a1d72 682static inline int pud_present(pud_t pud)
1da177e4 683{
cc18b460 684 if (pud_folded(pud))
6252d702 685 return 1;
0d017923 686 return (pud_val(pud) & _REGION_ENTRY_ORIGIN) != 0UL;
1da177e4
LT		 687}
688
190a1d72 689static inline int pud_none(pud_t pud)
1da177e4 690{
cc18b460 691 if (pud_folded(pud))
6252d702 692 return 0;
d08de8e2 693 return pud_val(pud) == _REGION3_ENTRY_EMPTY;
1da177e4
LT		 694}
695
8d2109f2 696#define pud_leaf pud_large
18da2369
HC		 697static inline int pud_large(pud_t pud)
698{
699 if ((pud_val(pud) & _REGION_ENTRY_TYPE_MASK) != _REGION_ENTRY_TYPE_R3)
700 return 0;
701 return !!(pud_val(pud) & _REGION3_ENTRY_LARGE);
702}
703
8d2109f2 704#define pmd_leaf pmd_large
d08de8e2
GS		 705static inline int pmd_large(pmd_t pmd)
706{
707 return (pmd_val(pmd) & _SEGMENT_ENTRY_LARGE) != 0;
708}
709
710static inline int pmd_bad(pmd_t pmd)
711{
1c27a4bc 712 if ((pmd_val(pmd) & _SEGMENT_ENTRY_TYPE_MASK) > 0 || pmd_large(pmd))
c9f62152 713 return 1;
d08de8e2
GS		 714 return (pmd_val(pmd) & ~_SEGMENT_ENTRY_BITS) != 0;
715}
716
190a1d72 717static inline int pud_bad(pud_t pud)
1da177e4 718{
c9f62152
MS		 719 unsigned long type = pud_val(pud) & _REGION_ENTRY_TYPE_MASK;
720
1c27a4bc 721 if (type > _REGION_ENTRY_TYPE_R3 || pud_large(pud))
c9f62152
MS		 722 return 1;
723 if (type < _REGION_ENTRY_TYPE_R3)
724 return 0;
d08de8e2 725 return (pud_val(pud) & ~_REGION_ENTRY_BITS) != 0;
1da177e4
LT		 726}
727
1aea9b3f
MS		 728static inline int p4d_bad(p4d_t p4d)
729{
c9f62152
MS		 730 unsigned long type = p4d_val(p4d) & _REGION_ENTRY_TYPE_MASK;
731
732 if (type > _REGION_ENTRY_TYPE_R2)
733 return 1;
734 if (type < _REGION_ENTRY_TYPE_R2)
735 return 0;
1aea9b3f
MS		 736 return (p4d_val(p4d) & ~_REGION_ENTRY_BITS) != 0;
737}
738
4448aaf0 739static inline int pmd_present(pmd_t pmd)
1da177e4 740{
54397bb0 741 return pmd_val(pmd) != _SEGMENT_ENTRY_EMPTY;
1da177e4
LT		 742}
743
4448aaf0 744static inline int pmd_none(pmd_t pmd)
1da177e4 745{
54397bb0 746 return pmd_val(pmd) == _SEGMENT_ENTRY_EMPTY;
1da177e4
LT		 747}
748
e4e40e02 749#define pmd_write pmd_write
1ae1c1d0
GS		 750static inline int pmd_write(pmd_t pmd)
751{
152125b7
MS		 752 return (pmd_val(pmd) & _SEGMENT_ENTRY_WRITE) != 0;
753}
754
582b4e55
GS		 755#define pud_write pud_write
756static inline int pud_write(pud_t pud)
757{
758 return (pud_val(pud) & _REGION3_ENTRY_WRITE) != 0;
759}
760
152125b7
MS		 761static inline int pmd_dirty(pmd_t pmd)
762{
2d1fc1eb 763 return (pmd_val(pmd) & _SEGMENT_ENTRY_DIRTY) != 0;
1ae1c1d0
GS		 764}
765
766static inline int pmd_young(pmd_t pmd)
767{
2d1fc1eb 768 return (pmd_val(pmd) & _SEGMENT_ENTRY_YOUNG) != 0;
1ae1c1d0
GS		 769}
770
e5098611 771static inline int pte_present(pte_t pte)
1da177e4 772{
e5098611
MS		 773 /* Bit pattern: (pte & 0x001) == 0x001 */
774 return (pte_val(pte) & _PAGE_PRESENT) != 0;
1da177e4
LT		 775}
776
e5098611 777static inline int pte_none(pte_t pte)
1da177e4 778{
e5098611
MS		 779 /* Bit pattern: pte == 0x400 */
780 return pte_val(pte) == _PAGE_INVALID;
1da177e4
LT		 781}
782
b31288fa
KW		 783static inline int pte_swap(pte_t pte)
784{
a1c843b8
MS		 785 /* Bit pattern: (pte & 0x201) == 0x200 */
786 return (pte_val(pte) & (_PAGE_PROTECT | _PAGE_PRESENT))
787 == _PAGE_PROTECT;
b31288fa
KW		 788}
789
7e675137
NP		 790static inline int pte_special(pte_t pte)
791{
a08cb629 792 return (pte_val(pte) & _PAGE_SPECIAL);
7e675137
NP		 793}
794
ba8a9229 795#define __HAVE_ARCH_PTE_SAME
b2fa47e6
MS		 796static inline int pte_same(pte_t a, pte_t b)
797{
798 return pte_val(a) == pte_val(b);
799}
1da177e4 800
b54565b8
MS		 801#ifdef CONFIG_NUMA_BALANCING
802static inline int pte_protnone(pte_t pte)
803{
804 return pte_present(pte) && !(pte_val(pte) & _PAGE_READ);
805}
806
807static inline int pmd_protnone(pmd_t pmd)
808{
809 /* pmd_large(pmd) implies pmd_present(pmd) */
810 return pmd_large(pmd) && !(pmd_val(pmd) & _SEGMENT_ENTRY_READ);
811}
812#endif
813
92cd58bd
DH		 814#define __HAVE_ARCH_PTE_SWP_EXCLUSIVE
815static inline int pte_swp_exclusive(pte_t pte)
816{
817 return pte_val(pte) & _PAGE_SWP_EXCLUSIVE;
818}
819
820static inline pte_t pte_swp_mkexclusive(pte_t pte)
821{
822 return set_pte_bit(pte, __pgprot(_PAGE_SWP_EXCLUSIVE));
823}
824
825static inline pte_t pte_swp_clear_exclusive(pte_t pte)
826{
827 return clear_pte_bit(pte, __pgprot(_PAGE_SWP_EXCLUSIVE));
828}
829
5614dd92
MS		 830static inline int pte_soft_dirty(pte_t pte)
831{
832 return pte_val(pte) & _PAGE_SOFT_DIRTY;
833}
834#define pte_swp_soft_dirty pte_soft_dirty
835
836static inline pte_t pte_mksoft_dirty(pte_t pte)
837{
4a366f51 838 return set_pte_bit(pte, __pgprot(_PAGE_SOFT_DIRTY));
5614dd92
MS		 839}
840#define pte_swp_mksoft_dirty pte_mksoft_dirty
841
842static inline pte_t pte_clear_soft_dirty(pte_t pte)
843{
4a366f51 844 return clear_pte_bit(pte, __pgprot(_PAGE_SOFT_DIRTY));
5614dd92
MS		 845}
846#define pte_swp_clear_soft_dirty pte_clear_soft_dirty
847
848static inline int pmd_soft_dirty(pmd_t pmd)
849{
850 return pmd_val(pmd) & _SEGMENT_ENTRY_SOFT_DIRTY;
851}
852
853static inline pmd_t pmd_mksoft_dirty(pmd_t pmd)
854{
4a366f51 855 return set_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_SOFT_DIRTY));
5614dd92
MS		 856}
857
858static inline pmd_t pmd_clear_soft_dirty(pmd_t pmd)
859{
4a366f51 860 return clear_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_SOFT_DIRTY));
5614dd92
MS		 861}
862
1da177e4
LT		 863/*
864 * query functions pte_write/pte_dirty/pte_young only work if
865 * pte_present() is true. Undefined behaviour if not..
866 */
4448aaf0 867static inline int pte_write(pte_t pte)
1da177e4 868{
e5098611 869 return (pte_val(pte) & _PAGE_WRITE) != 0;
1da177e4
LT		 870}
871
4448aaf0 872static inline int pte_dirty(pte_t pte)
1da177e4 873{
e5098611 874 return (pte_val(pte) & _PAGE_DIRTY) != 0;
1da177e4
LT		 875}
876
4448aaf0 877static inline int pte_young(pte_t pte)
1da177e4 878{
0944fe3f 879 return (pte_val(pte) & _PAGE_YOUNG) != 0;
1da177e4
LT		 880}
881
b31288fa
KW		 882#define __HAVE_ARCH_PTE_UNUSED
883static inline int pte_unused(pte_t pte)
884{
885 return pte_val(pte) & _PAGE_UNUSED;
886}
887
d460bb6c
NS		 888/*
889 * Extract the pgprot value from the given pte while at the same time making it
890 * usable for kernel address space mappings where fault driven dirty and
891 * young/old accounting is not supported, i.e _PAGE_PROTECT and _PAGE_INVALID
892 * must not be set.
893 */
894static inline pgprot_t pte_pgprot(pte_t pte)
895{
896 unsigned long pte_flags = pte_val(pte) & _PAGE_CHG_MASK;
897
898 if (pte_write(pte))
899 pte_flags |= pgprot_val(PAGE_KERNEL);
900 else
901 pte_flags |= pgprot_val(PAGE_KERNEL_RO);
902 pte_flags |= pte_val(pte) & mio_wb_bit_mask;
903
904 return __pgprot(pte_flags);
905}
906
1da177e4
LT		 907/*
908 * pgd/pmd/pte modification functions
909 */
910
e2aaae2d
HC		 911static inline void set_pgd(pgd_t *pgdp, pgd_t pgd)
912{
913 WRITE_ONCE(*pgdp, pgd);
914}
915
916static inline void set_p4d(p4d_t *p4dp, p4d_t p4d)
917{
918 WRITE_ONCE(*p4dp, p4d);
919}
920
921static inline void set_pud(pud_t *pudp, pud_t pud)
922{
923 WRITE_ONCE(*pudp, pud);
924}
925
926static inline void set_pmd(pmd_t *pmdp, pmd_t pmd)
927{
928 WRITE_ONCE(*pmdp, pmd);
929}
930
931static inline void set_pte(pte_t *ptep, pte_t pte)
932{
933 WRITE_ONCE(*ptep, pte);
934}
935
b2fa47e6 936static inline void pgd_clear(pgd_t *pgd)
5a216a20 937{
1aea9b3f 938 if ((pgd_val(*pgd) & _REGION_ENTRY_TYPE_MASK) == _REGION_ENTRY_TYPE_R1)
b8e3b379 939 set_pgd(pgd, __pgd(_REGION1_ENTRY_EMPTY));
1aea9b3f
MS		 940}
941
942static inline void p4d_clear(p4d_t *p4d)
943{
944 if ((p4d_val(*p4d) & _REGION_ENTRY_TYPE_MASK) == _REGION_ENTRY_TYPE_R2)
b8e3b379 945 set_p4d(p4d, __p4d(_REGION2_ENTRY_EMPTY));
5a216a20
MS		 946}
947
b2fa47e6 948static inline void pud_clear(pud_t *pud)
1da177e4 949{
6252d702 950 if ((pud_val(*pud) & _REGION_ENTRY_TYPE_MASK) == _REGION_ENTRY_TYPE_R3)
b8e3b379 951 set_pud(pud, __pud(_REGION3_ENTRY_EMPTY));
1da177e4
LT		 952}
953
b2fa47e6 954static inline void pmd_clear(pmd_t *pmdp)
1da177e4 955{
b8e3b379 956 set_pmd(pmdp, __pmd(_SEGMENT_ENTRY_EMPTY));
1da177e4
LT		 957}
958
4448aaf0 959static inline void pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
1da177e4 960{
b8e3b379 961 set_pte(ptep, __pte(_PAGE_INVALID));
1da177e4
LT		 962}
963
964/*
965 * The following pte modification functions only work if
966 * pte_present() is true. Undefined behaviour if not..
967 */
4448aaf0 968static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
1da177e4 969{
4a366f51
HC		 970 pte = clear_pte_bit(pte, __pgprot(~_PAGE_CHG_MASK));
971 pte = set_pte_bit(pte, newprot);
0944fe3f 972 /*
57d7f939
MS		 973 * newprot for PAGE_NONE, PAGE_RO, PAGE_RX, PAGE_RW and PAGE_RWX
974 * has the invalid bit set, clear it again for readable, young pages
0944fe3f
MS		 975 */
976 if ((pte_val(pte) & _PAGE_YOUNG) && (pte_val(pte) & _PAGE_READ))
4a366f51 977 pte = clear_pte_bit(pte, __pgprot(_PAGE_INVALID));
0944fe3f 978 /*
57d7f939
MS		 979 * newprot for PAGE_RO, PAGE_RX, PAGE_RW and PAGE_RWX has the page
980 * protection bit set, clear it again for writable, dirty pages
0944fe3f 981 */
e5098611 982 if ((pte_val(pte) & _PAGE_DIRTY) && (pte_val(pte) & _PAGE_WRITE))
4a366f51 983 pte = clear_pte_bit(pte, __pgprot(_PAGE_PROTECT));
1da177e4
LT		 984 return pte;
985}
986
4448aaf0 987static inline pte_t pte_wrprotect(pte_t pte)
1da177e4 988{
4a366f51
HC		 989 pte = clear_pte_bit(pte, __pgprot(_PAGE_WRITE));
990 return set_pte_bit(pte, __pgprot(_PAGE_PROTECT));
1da177e4
LT		 991}
992
4448aaf0 993static inline pte_t pte_mkwrite(pte_t pte)
1da177e4 994{
4a366f51 995 pte = set_pte_bit(pte, __pgprot(_PAGE_WRITE));
e5098611 996 if (pte_val(pte) & _PAGE_DIRTY)
4a366f51 997 pte = clear_pte_bit(pte, __pgprot(_PAGE_PROTECT));
1da177e4
LT		 998 return pte;
999}
1000
4448aaf0 1001static inline pte_t pte_mkclean(pte_t pte)
1da177e4 1002{
4a366f51
HC		 1003 pte = clear_pte_bit(pte, __pgprot(_PAGE_DIRTY));
1004 return set_pte_bit(pte, __pgprot(_PAGE_PROTECT));
1da177e4
LT		 1005}
1006
4448aaf0 1007static inline pte_t pte_mkdirty(pte_t pte)
1da177e4 1008{
4a366f51 1009 pte = set_pte_bit(pte, __pgprot(_PAGE_DIRTY | _PAGE_SOFT_DIRTY));
e5098611 1010 if (pte_val(pte) & _PAGE_WRITE)
4a366f51 1011 pte = clear_pte_bit(pte, __pgprot(_PAGE_PROTECT));
1da177e4
LT		 1012 return pte;
1013}
1014
4448aaf0 1015static inline pte_t pte_mkold(pte_t pte)
1da177e4 1016{
4a366f51
HC		 1017 pte = clear_pte_bit(pte, __pgprot(_PAGE_YOUNG));
1018 return set_pte_bit(pte, __pgprot(_PAGE_INVALID));
1da177e4
LT		 1019}
1020
4448aaf0 1021static inline pte_t pte_mkyoung(pte_t pte)
1da177e4 1022{
4a366f51 1023 pte = set_pte_bit(pte, __pgprot(_PAGE_YOUNG));
0944fe3f 1024 if (pte_val(pte) & _PAGE_READ)
4a366f51 1025 pte = clear_pte_bit(pte, __pgprot(_PAGE_INVALID));
1da177e4
LT		 1026 return pte;
1027}
1028
7e675137
NP		 1029static inline pte_t pte_mkspecial(pte_t pte)
1030{
4a366f51 1031 return set_pte_bit(pte, __pgprot(_PAGE_SPECIAL));
7e675137
NP		 1032}
1033
84afdcee
HC		 1034#ifdef CONFIG_HUGETLB_PAGE
1035static inline pte_t pte_mkhuge(pte_t pte)
1036{
4a366f51 1037 return set_pte_bit(pte, __pgprot(_PAGE_LARGE));
84afdcee
HC		 1038}
1039#endif
1040
34eeaf37
MS		 1041#define IPTE_GLOBAL 0
1042#define IPTE_LOCAL 1
53e857f3 1043
118bd31b 1044#define IPTE_NODAT 0x400
28c807e5 1045#define IPTE_GUEST_ASCE 0x800
118bd31b 1046
6818b542
HC		 1047static __always_inline void __ptep_ipte(unsigned long address, pte_t *ptep,
1048 unsigned long opt, unsigned long asce,
1049 int local)
1b948d6c 1050{
273cd173 1051 unsigned long pto = __pa(ptep);
1b948d6c 1052
118bd31b
MS		 1053 if (__builtin_constant_p(opt) && opt == 0) {
1054 /* Invalidation + TLB flush for the pte */
1055 asm volatile(
731efc96 1056 " ipte %[r1],%[r2],0,%[m4]"
118bd31b
MS		 1057 : "+m" (*ptep) : [r1] "a" (pto), [r2] "a" (address),
1058 [m4] "i" (local));
1059 return;
1060 }
1061
1062 /* Invalidate ptes with options + TLB flush of the ptes */
28c807e5 1063 opt = opt | (asce & _ASCE_ORIGIN);
1b948d6c 1064 asm volatile(
731efc96 1065 " ipte %[r1],%[r2],%[r3],%[m4]"
118bd31b
MS		 1066 : [r2] "+a" (address), [r3] "+a" (opt)
1067 : [r1] "a" (pto), [m4] "i" (local) : "memory");
1b948d6c
MS		 1068}
1069
6818b542
HC		 1070static __always_inline void __ptep_ipte_range(unsigned long address, int nr,
1071 pte_t *ptep, int local)
cfb0b241 1072{
273cd173 1073 unsigned long pto = __pa(ptep);
cfb0b241 1074
34eeaf37 1075 /* Invalidate a range of ptes + TLB flush of the ptes */
cfb0b241
HC		 1076 do {
1077 asm volatile(
731efc96 1078 " ipte %[r1],%[r2],%[r3],%[m4]"
34eeaf37
MS		 1079 : [r2] "+a" (address), [r3] "+a" (nr)
1080 : [r1] "a" (pto), [m4] "i" (local) : "memory");
cfb0b241
HC		 1081 } while (nr != 255);
1082}
1083
0a61b222 1084/*
ebde765c
MS		 1085 * This is hard to understand. ptep_get_and_clear and ptep_clear_flush
1086 * both clear the TLB for the unmapped pte. The reason is that
1087 * ptep_get_and_clear is used in common code (e.g. change_pte_range)
1088 * to modify an active pte. The sequence is
1089 * 1) ptep_get_and_clear
1090 * 2) set_pte_at
1091 * 3) flush_tlb_range
1092 * On s390 the tlb needs to get flushed with the modification of the pte
1093 * if the pte is active. The only way how this can be implemented is to
1094 * have ptep_get_and_clear do the tlb flush. In exchange flush_tlb_range
1095 * is a nop.
0a61b222 1096 */
ebde765c
MS		 1097pte_t ptep_xchg_direct(struct mm_struct *, unsigned long, pte_t *, pte_t);
1098pte_t ptep_xchg_lazy(struct mm_struct *, unsigned long, pte_t *, pte_t);
0a61b222 1099
0944fe3f
MS		 1100#define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
1101static inline int ptep_test_and_clear_young(struct vm_area_struct *vma,
1102 unsigned long addr, pte_t *ptep)
1103{
ebde765c 1104 pte_t pte = *ptep;
0944fe3f 1105
ebde765c
MS		 1106 pte = ptep_xchg_direct(vma->vm_mm, addr, ptep, pte_mkold(pte));
1107 return pte_young(pte);
0944fe3f
MS		 1108}
1109
1110#define __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH
1111static inline int ptep_clear_flush_young(struct vm_area_struct *vma,
1112 unsigned long address, pte_t *ptep)
1113{
1114 return ptep_test_and_clear_young(vma, address, ptep);
1115}
1116
ba8a9229 1117#define __HAVE_ARCH_PTEP_GET_AND_CLEAR
b2fa47e6 1118static inline pte_t ptep_get_and_clear(struct mm_struct *mm,
ebde765c 1119 unsigned long addr, pte_t *ptep)
b2fa47e6 1120{
214d9bbc
CI		 1121 pte_t res;
1122
1123 res = ptep_xchg_lazy(mm, addr, ptep, __pte(_PAGE_INVALID));
380d97bd 1124 /* At this point the reference through the mapping is still present */
214d9bbc 1125 if (mm_is_protected(mm) && pte_present(res))
380d97bd 1126 uv_convert_owned_from_secure(pte_val(res) & PAGE_MASK);
214d9bbc 1127 return res;
b2fa47e6
MS		 1128}
1129
1130#define __HAVE_ARCH_PTEP_MODIFY_PROT_TRANSACTION
0cbe3e26 1131pte_t ptep_modify_prot_start(struct vm_area_struct *, unsigned long, pte_t *);
04a86453
AK		 1132void ptep_modify_prot_commit(struct vm_area_struct *, unsigned long,
1133 pte_t *, pte_t, pte_t);
ba8a9229
MS		 1134
1135#define __HAVE_ARCH_PTEP_CLEAR_FLUSH
f0e47c22 1136static inline pte_t ptep_clear_flush(struct vm_area_struct *vma,
ebde765c 1137 unsigned long addr, pte_t *ptep)
f0e47c22 1138{
214d9bbc
CI		 1139 pte_t res;
1140
1141 res = ptep_xchg_direct(vma->vm_mm, addr, ptep, __pte(_PAGE_INVALID));
380d97bd 1142 /* At this point the reference through the mapping is still present */
214d9bbc 1143 if (mm_is_protected(vma->vm_mm) && pte_present(res))
380d97bd 1144 uv_convert_owned_from_secure(pte_val(res) & PAGE_MASK);
214d9bbc 1145 return res;
1da177e4
LT		 1146}
1147
ba8a9229
MS		 1148/*
1149 * The batched pte unmap code uses ptep_get_and_clear_full to clear the
1150 * ptes. Here an optimization is possible. tlb_gather_mmu flushes all
1151 * tlbs of an mm if it can guarantee that the ptes of the mm_struct
1152 * cannot be accessed while the batched unmap is running. In this case
1153 * full==1 and a simple pte_clear is enough. See tlb.h.
1154 */
1155#define __HAVE_ARCH_PTEP_GET_AND_CLEAR_FULL
1156static inline pte_t ptep_get_and_clear_full(struct mm_struct *mm,
ebde765c 1157 unsigned long addr,
ba8a9229 1158 pte_t *ptep, int full)
1da177e4 1159{
214d9bbc
CI		 1160 pte_t res;
1161
ebde765c 1162 if (full) {
214d9bbc 1163 res = *ptep;
b8e3b379 1164 set_pte(ptep, __pte(_PAGE_INVALID));
214d9bbc
CI		 1165 } else {
1166 res = ptep_xchg_lazy(mm, addr, ptep, __pte(_PAGE_INVALID));
b2fa47e6 1167 }
9bf811da
CI		 1168 /* Nothing to do */
1169 if (!mm_is_protected(mm) || !pte_present(res))
1170 return res;
1171 /*
1172 * At this point the reference through the mapping is still present.
1173 * The notifier should have destroyed all protected vCPUs at this
1174 * point, so the destroy should be successful.
1175 */
1176 if (full && !uv_destroy_owned_page(pte_val(res) & PAGE_MASK))
1177 return res;
1178 /*
1179 * If something went wrong and the page could not be destroyed, or
1180 * if this is not a mm teardown, the slower export is used as
1181 * fallback instead.
1182 */
1183 uv_convert_owned_from_secure(pte_val(res) & PAGE_MASK);
214d9bbc 1184 return res;
1da177e4
LT		 1185}
1186
ba8a9229 1187#define __HAVE_ARCH_PTEP_SET_WRPROTECT
ebde765c
MS		 1188static inline void ptep_set_wrprotect(struct mm_struct *mm,
1189 unsigned long addr, pte_t *ptep)
b2fa47e6 1190{
b2fa47e6
MS		 1191 pte_t pte = *ptep;
1192
ebde765c
MS		 1193 if (pte_write(pte))
1194 ptep_xchg_lazy(mm, addr, ptep, pte_wrprotect(pte));
b2fa47e6 1195}
ba8a9229
MS		 1196
1197#define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS
b2fa47e6 1198static inline int ptep_set_access_flags(struct vm_area_struct *vma,
ebde765c 1199 unsigned long addr, pte_t *ptep,
b2fa47e6
MS		 1200 pte_t entry, int dirty)
1201{
ebde765c 1202 if (pte_same(*ptep, entry))
b2fa47e6 1203 return 0;
ebde765c
MS		 1204 ptep_xchg_direct(vma->vm_mm, addr, ptep, entry);
1205 return 1;
1206}
b2fa47e6 1207
1e133ab2
MS		 1208/*
1209 * Additional functions to handle KVM guest page tables
1210 */
1211void ptep_set_pte_at(struct mm_struct *mm, unsigned long addr,
1212 pte_t *ptep, pte_t entry);
1213void ptep_set_notify(struct mm_struct *mm, unsigned long addr, pte_t *ptep);
4be130a0
MS		 1214void ptep_notify(struct mm_struct *mm, unsigned long addr,
1215 pte_t *ptep, unsigned long bits);
b2d73b2a 1216int ptep_force_prot(struct mm_struct *mm, unsigned long gaddr,
4be130a0 1217 pte_t *ptep, int prot, unsigned long bit);
1e133ab2
MS		 1218void ptep_zap_unused(struct mm_struct *mm, unsigned long addr,
1219 pte_t *ptep , int reset);
1220void ptep_zap_key(struct mm_struct *mm, unsigned long addr, pte_t *ptep);
4be130a0 1221int ptep_shadow_pte(struct mm_struct *mm, unsigned long saddr,
a9d23e71 1222 pte_t *sptep, pte_t *tptep, pte_t pte);
4be130a0 1223void ptep_unshadow_pte(struct mm_struct *mm, unsigned long saddr, pte_t *ptep);
1e133ab2 1224
0959e168
JF		 1225bool ptep_test_and_clear_uc(struct mm_struct *mm, unsigned long address,
1226 pte_t *ptep);
1e133ab2
MS		 1227int set_guest_storage_key(struct mm_struct *mm, unsigned long addr,
1228 unsigned char key, bool nq);
1824c723
DH		 1229int cond_set_guest_storage_key(struct mm_struct *mm, unsigned long addr,
1230 unsigned char key, unsigned char *oldkey,
1231 bool nq, bool mr, bool mc);
a7e19ab5 1232int reset_guest_reference_bit(struct mm_struct *mm, unsigned long addr);
154c8c19
DH		 1233int get_guest_storage_key(struct mm_struct *mm, unsigned long addr,
1234 unsigned char *key);
b2fa47e6 1235
2d42f947
CI		 1236int set_pgste_bits(struct mm_struct *mm, unsigned long addr,
1237 unsigned long bits, unsigned long value);
1238int get_pgste(struct mm_struct *mm, unsigned long hva, unsigned long *pgstep);
1239int pgste_perform_essa(struct mm_struct *mm, unsigned long hva, int orc,
1240 unsigned long *oldpte, unsigned long *oldpgste);
6a376277
JF		 1241void gmap_pmdp_csp(struct mm_struct *mm, unsigned long vmaddr);
1242void gmap_pmdp_invalidate(struct mm_struct *mm, unsigned long vmaddr);
1243void gmap_pmdp_idte_local(struct mm_struct *mm, unsigned long vmaddr);
1244void gmap_pmdp_idte_global(struct mm_struct *mm, unsigned long vmaddr);
2d42f947 1245
b02002cc
NS		 1246#define pgprot_writecombine pgprot_writecombine
1247pgprot_t pgprot_writecombine(pgprot_t prot);
1248
1249#define pgprot_writethrough pgprot_writethrough
1250pgprot_t pgprot_writethrough(pgprot_t prot);
1251
ebde765c
MS		 1252/*
1253 * Certain architectures need to do special things when PTEs
1254 * within a page table are directly modified. Thus, the following
1255 * hook is made available.
1256 */
1257static inline void set_pte_at(struct mm_struct *mm, unsigned long addr,
1258 pte_t *ptep, pte_t entry)
1259{
a8f60d1f 1260 if (pte_present(entry))
4a366f51 1261 entry = clear_pte_bit(entry, __pgprot(_PAGE_UNUSED));
ebde765c 1262 if (mm_has_pgste(mm))
1e133ab2 1263 ptep_set_pte_at(mm, addr, ptep, entry);
ebde765c 1264 else
b8e3b379 1265 set_pte(ptep, entry);
b2fa47e6 1266}
1da177e4 1267
1da177e4
LT		 1268/*
1269 * Conversion functions: convert a page and protection to a page entry,
1270 * and a page entry and page directory to the page they refer to.
1271 */
1272static inline pte_t mk_pte_phys(unsigned long physpage, pgprot_t pgprot)
1273{
1274 pte_t __pte;
b02002cc 1275
4a366f51 1276 __pte = __pte(physpage | pgprot_val(pgprot));
ab874f22 1277 if (!MACHINE_HAS_NX)
4a366f51 1278 __pte = clear_pte_bit(__pte, __pgprot(_PAGE_NOEXEC));
0944fe3f 1279 return pte_mkyoung(__pte);
1da177e4
LT		 1280}
1281
2dcea57a
HC		 1282static inline pte_t mk_pte(struct page *page, pgprot_t pgprot)
1283{
0b2b6e1d 1284 unsigned long physpage = page_to_phys(page);
abf09bed 1285 pte_t __pte = mk_pte_phys(physpage, pgprot);
1da177e4 1286
e5098611
MS		 1287 if (pte_write(__pte) && PageDirty(page))
1288 __pte = pte_mkdirty(__pte);
abf09bed 1289 return __pte;
2dcea57a
HC		 1290}
1291
190a1d72 1292#define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD-1))
1aea9b3f 1293#define p4d_index(address) (((address) >> P4D_SHIFT) & (PTRS_PER_P4D-1))
190a1d72
MS		 1294#define pud_index(address) (((address) >> PUD_SHIFT) & (PTRS_PER_PUD-1))
1295#define pmd_index(address) (((address) >> PMD_SHIFT) & (PTRS_PER_PMD-1))
1da177e4 1296
86c827b3
AG		 1297#define p4d_deref(pud) ((unsigned long)__va(p4d_val(pud) & _REGION_ENTRY_ORIGIN))
1298#define pgd_deref(pgd) ((unsigned long)__va(pgd_val(pgd) & _REGION_ENTRY_ORIGIN))
1da177e4 1299
b0e98aa9
GS		 1300static inline unsigned long pmd_deref(pmd_t pmd)
1301{
1302 unsigned long origin_mask;
1303
1304 origin_mask = _SEGMENT_ENTRY_ORIGIN;
1305 if (pmd_large(pmd))
1306 origin_mask = _SEGMENT_ENTRY_ORIGIN_LARGE;
86c827b3 1307 return (unsigned long)__va(pmd_val(pmd) & origin_mask);
b0e98aa9
GS		 1308}
1309
1310static inline unsigned long pmd_pfn(pmd_t pmd)
1311{
86c827b3 1312 return __pa(pmd_deref(pmd)) >> PAGE_SHIFT;
b0e98aa9
GS		 1313}
1314
1315static inline unsigned long pud_deref(pud_t pud)
1316{
1317 unsigned long origin_mask;
1318
1319 origin_mask = _REGION_ENTRY_ORIGIN;
1320 if (pud_large(pud))
1321 origin_mask = _REGION3_ENTRY_ORIGIN_LARGE;
86c827b3 1322 return (unsigned long)__va(pud_val(pud) & origin_mask);
b0e98aa9
GS		 1323}
1324
1325static inline unsigned long pud_pfn(pud_t pud)
1326{
86c827b3 1327 return __pa(pud_deref(pud)) >> PAGE_SHIFT;
b0e98aa9
GS		 1328}
1329
d1874a0c
MS		 1330/*
1331 * The pgd_offset function *always* adds the index for the top-level
1332 * region/segment table. This is done to get a sequence like the
1333 * following to work:
1334 * pgdp = pgd_offset(current->mm, addr);
1335 * pgd = READ_ONCE(*pgdp);
1336 * p4dp = p4d_offset(&pgd, addr);
1337 * ...
1338 * The subsequent p4d_offset, pud_offset and pmd_offset functions
1339 * only add an index if they dereferenced the pointer.
1340 */
1341static inline pgd_t *pgd_offset_raw(pgd_t *pgd, unsigned long address)
5a216a20 1342{
d1874a0c
MS		 1343 unsigned long rste;
1344 unsigned int shift;
1aea9b3f 1345
d1874a0c
MS		 1346 /* Get the first entry of the top level table */
1347 rste = pgd_val(*pgd);
1348 /* Pick up the shift from the table type of the first entry */
1349 shift = ((rste & _REGION_ENTRY_TYPE_MASK) >> 2) * 11 + 20;
1350 return pgd + ((address >> shift) & (PTRS_PER_PGD - 1));
1aea9b3f
MS		 1351}
1352
d1874a0c 1353#define pgd_offset(mm, address) pgd_offset_raw(READ_ONCE((mm)->pgd), address)
d1874a0c 1354
d3f7b1bb 1355static inline p4d_t *p4d_offset_lockless(pgd_t *pgdp, pgd_t pgd, unsigned long address)
1aea9b3f 1356{
d3f7b1bb
VG		 1357 if ((pgd_val(pgd) & _REGION_ENTRY_TYPE_MASK) >= _REGION_ENTRY_TYPE_R1)
1358 return (p4d_t *) pgd_deref(pgd) + p4d_index(address);
1359 return (p4d_t *) pgdp;
d1874a0c 1360}
d3f7b1bb 1361#define p4d_offset_lockless p4d_offset_lockless
1aea9b3f 1362
d3f7b1bb 1363static inline p4d_t *p4d_offset(pgd_t *pgdp, unsigned long address)
d1874a0c 1364{
d3f7b1bb
VG		 1365 return p4d_offset_lockless(pgdp, *pgdp, address);
1366}
1367
1368static inline pud_t *pud_offset_lockless(p4d_t *p4dp, p4d_t p4d, unsigned long address)
1369{
1370 if ((p4d_val(p4d) & _REGION_ENTRY_TYPE_MASK) >= _REGION_ENTRY_TYPE_R2)
1371 return (pud_t *) p4d_deref(p4d) + pud_index(address);
1372 return (pud_t *) p4dp;
1373}
1374#define pud_offset_lockless pud_offset_lockless
1375
1376static inline pud_t *pud_offset(p4d_t *p4dp, unsigned long address)
1377{
1378 return pud_offset_lockless(p4dp, *p4dp, address);
5a216a20 1379}
974b9b2c 1380#define pud_offset pud_offset
1da177e4 1381
d3f7b1bb
VG		 1382static inline pmd_t *pmd_offset_lockless(pud_t *pudp, pud_t pud, unsigned long address)
1383{
1384 if ((pud_val(pud) & _REGION_ENTRY_TYPE_MASK) >= _REGION_ENTRY_TYPE_R3)
1385 return (pmd_t *) pud_deref(pud) + pmd_index(address);
1386 return (pmd_t *) pudp;
1387}
1388#define pmd_offset_lockless pmd_offset_lockless
1389
1390static inline pmd_t *pmd_offset(pud_t *pudp, unsigned long address)
1da177e4 1391{
d3f7b1bb 1392 return pmd_offset_lockless(pudp, *pudp, address);
d1874a0c 1393}
974b9b2c 1394#define pmd_offset pmd_offset
1aea9b3f 1395
974b9b2c 1396static inline unsigned long pmd_page_vaddr(pmd_t pmd)
d1874a0c 1397{
974b9b2c 1398 return (unsigned long) pmd_deref(pmd);
1da177e4
LT		 1399}
1400
26f4c328 1401static inline bool gup_fast_permitted(unsigned long start, unsigned long end)
1a42010c 1402{
1a42010c
MS		 1403 return end <= current->mm->context.asce_limit;
1404}
1405#define gup_fast_permitted gup_fast_permitted
1406
0f3bf303 1407#define pfn_pte(pfn, pgprot) mk_pte_phys(((pfn) << PAGE_SHIFT), (pgprot))
190a1d72
MS		 1408#define pte_pfn(x) (pte_val(x) >> PAGE_SHIFT)
1409#define pte_page(x) pfn_to_page(pte_pfn(x))
1da177e4 1410
152125b7 1411#define pmd_page(pmd) pfn_to_page(pmd_pfn(pmd))
d08de8e2 1412#define pud_page(pud) pfn_to_page(pud_pfn(pud))
d0e2eb0a
VG		 1413#define p4d_page(p4d) pfn_to_page(p4d_pfn(p4d))
1414#define pgd_page(pgd) pfn_to_page(pgd_pfn(pgd))
1da177e4 1415
152125b7 1416static inline pmd_t pmd_wrprotect(pmd_t pmd)
0944fe3f 1417{
4a366f51
HC		 1418 pmd = clear_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_WRITE));
1419 return set_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_PROTECT));
152125b7
MS		 1420}
1421
1422static inline pmd_t pmd_mkwrite(pmd_t pmd)
1423{
4a366f51 1424 pmd = set_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_WRITE));
2d1fc1eb 1425 if (pmd_val(pmd) & _SEGMENT_ENTRY_DIRTY)
4a366f51 1426 pmd = clear_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_PROTECT));
152125b7
MS		 1427 return pmd;
1428}
1429
1430static inline pmd_t pmd_mkclean(pmd_t pmd)
1431{
4a366f51
HC		 1432 pmd = clear_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_DIRTY));
1433 return set_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_PROTECT));
152125b7
MS		 1434}
1435
1436static inline pmd_t pmd_mkdirty(pmd_t pmd)
1437{
4a366f51 1438 pmd = set_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_DIRTY | _SEGMENT_ENTRY_SOFT_DIRTY));
2d1fc1eb 1439 if (pmd_val(pmd) & _SEGMENT_ENTRY_WRITE)
4a366f51 1440 pmd = clear_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_PROTECT));
152125b7
MS		 1441 return pmd;
1442}
1443
9e20b4da
HC		 1444static inline pud_t pud_wrprotect(pud_t pud)
1445{
4a366f51
HC		 1446 pud = clear_pud_bit(pud, __pgprot(_REGION3_ENTRY_WRITE));
1447 return set_pud_bit(pud, __pgprot(_REGION_ENTRY_PROTECT));
9e20b4da
HC		 1448}
1449
1450static inline pud_t pud_mkwrite(pud_t pud)
1451{
4a366f51 1452 pud = set_pud_bit(pud, __pgprot(_REGION3_ENTRY_WRITE));
2d1fc1eb 1453 if (pud_val(pud) & _REGION3_ENTRY_DIRTY)
4a366f51 1454 pud = clear_pud_bit(pud, __pgprot(_REGION_ENTRY_PROTECT));
9e20b4da
HC		 1455 return pud;
1456}
1457
1458static inline pud_t pud_mkclean(pud_t pud)
1459{
4a366f51
HC		 1460 pud = clear_pud_bit(pud, __pgprot(_REGION3_ENTRY_DIRTY));
1461 return set_pud_bit(pud, __pgprot(_REGION_ENTRY_PROTECT));
9e20b4da
HC		 1462}
1463
1464static inline pud_t pud_mkdirty(pud_t pud)
1465{
4a366f51 1466 pud = set_pud_bit(pud, __pgprot(_REGION3_ENTRY_DIRTY | _REGION3_ENTRY_SOFT_DIRTY));
2d1fc1eb 1467 if (pud_val(pud) & _REGION3_ENTRY_WRITE)
4a366f51 1468 pud = clear_pud_bit(pud, __pgprot(_REGION_ENTRY_PROTECT));
9e20b4da
HC		 1469 return pud;
1470}
1471
1472#if defined(CONFIG_TRANSPARENT_HUGEPAGE) || defined(CONFIG_HUGETLB_PAGE)
1473static inline unsigned long massage_pgprot_pmd(pgprot_t pgprot)
1474{
1475 /*
57d7f939
MS		 1476 * pgprot is PAGE_NONE, PAGE_RO, PAGE_RX, PAGE_RW or PAGE_RWX
1477 * (see __Pxxx / __Sxxx). Convert to segment table entry format.
9e20b4da
HC		 1478 */
1479 if (pgprot_val(pgprot) == pgprot_val(PAGE_NONE))
1480 return pgprot_val(SEGMENT_NONE);
57d7f939
MS		 1481 if (pgprot_val(pgprot) == pgprot_val(PAGE_RO))
1482 return pgprot_val(SEGMENT_RO);
1483 if (pgprot_val(pgprot) == pgprot_val(PAGE_RX))
1484 return pgprot_val(SEGMENT_RX);
1485 if (pgprot_val(pgprot) == pgprot_val(PAGE_RW))
1486 return pgprot_val(SEGMENT_RW);
1487 return pgprot_val(SEGMENT_RWX);
9e20b4da
HC		 1488}
1489
152125b7
MS		 1490static inline pmd_t pmd_mkyoung(pmd_t pmd)
1491{
4a366f51 1492 pmd = set_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_YOUNG));
2d1fc1eb 1493 if (pmd_val(pmd) & _SEGMENT_ENTRY_READ)
4a366f51 1494 pmd = clear_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_INVALID));
0944fe3f
MS		 1495 return pmd;
1496}
1497
1498static inline pmd_t pmd_mkold(pmd_t pmd)
1499{
4a366f51
HC		 1500 pmd = clear_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_YOUNG));
1501 return set_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_INVALID));
0944fe3f
MS		 1502}
1503
1ae1c1d0
GS		 1504static inline pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot)
1505{
4a366f51
HC		 1506 unsigned long mask;
1507
1508 mask = _SEGMENT_ENTRY_ORIGIN_LARGE;
1509 mask |= _SEGMENT_ENTRY_DIRTY;
1510 mask |= _SEGMENT_ENTRY_YOUNG;
1511 mask |= _SEGMENT_ENTRY_LARGE;
1512 mask |= _SEGMENT_ENTRY_SOFT_DIRTY;
1513 pmd = __pmd(pmd_val(pmd) & mask);
1514 pmd = set_pmd_bit(pmd, __pgprot(massage_pgprot_pmd(newprot)));
2d1fc1eb 1515 if (!(pmd_val(pmd) & _SEGMENT_ENTRY_DIRTY))
4a366f51 1516 pmd = set_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_PROTECT));
2d1fc1eb 1517 if (!(pmd_val(pmd) & _SEGMENT_ENTRY_YOUNG))
4a366f51 1518 pmd = set_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_INVALID));
1ae1c1d0
GS		 1519 return pmd;
1520}
1521
106c992a 1522static inline pmd_t mk_pmd_phys(unsigned long physpage, pgprot_t pgprot)
1ae1c1d0 1523{
4a366f51 1524 return __pmd(physpage + massage_pgprot_pmd(pgprot));
1ae1c1d0
GS		 1525}
1526
106c992a
GS		 1527#endif /* CONFIG_TRANSPARENT_HUGEPAGE || CONFIG_HUGETLB_PAGE */
1528
1b948d6c
MS		 1529static inline void __pmdp_csp(pmd_t *pmdp)
1530{
4ccccc52
HC		 1531 csp((unsigned int *)pmdp + 1, pmd_val(*pmdp),
1532 pmd_val(*pmdp) | _SEGMENT_ENTRY_INVALID);
1b948d6c
MS		 1533}
1534
47e4d851
MS		 1535#define IDTE_GLOBAL 0
1536#define IDTE_LOCAL 1
d08de8e2 1537
118bd31b
MS		 1538#define IDTE_PTOA 0x0800
1539#define IDTE_NODAT 0x1000
28c807e5 1540#define IDTE_GUEST_ASCE 0x2000
118bd31b 1541
6818b542
HC		 1542static __always_inline void __pmdp_idte(unsigned long addr, pmd_t *pmdp,
1543 unsigned long opt, unsigned long asce,
1544 int local)
1b948d6c
MS		 1545{
1546 unsigned long sto;
1547
273cd173 1548 sto = __pa(pmdp) - pmd_index(addr) * sizeof(pmd_t);
28c807e5
MS		 1549 if (__builtin_constant_p(opt) && opt == 0) {
1550 /* flush without guest asce */
1551 asm volatile(
731efc96 1552 " idte %[r1],0,%[r2],%[m4]"
28c807e5
MS		 1553 : "+m" (*pmdp)
1554 : [r1] "a" (sto), [r2] "a" ((addr & HPAGE_MASK)),
1555 [m4] "i" (local)
1556 : "cc" );
1557 } else {
1558 /* flush with guest asce */
1559 asm volatile(
731efc96 1560 " idte %[r1],%[r3],%[r2],%[m4]"
28c807e5
MS		 1561 : "+m" (*pmdp)
1562 : [r1] "a" (sto), [r2] "a" ((addr & HPAGE_MASK) | opt),
1563 [r3] "a" (asce), [m4] "i" (local)
1564 : "cc" );
1565 }
1b948d6c
MS		 1566}
1567
6818b542
HC		 1568static __always_inline void __pudp_idte(unsigned long addr, pud_t *pudp,
1569 unsigned long opt, unsigned long asce,
1570 int local)
d08de8e2
GS		 1571{
1572 unsigned long r3o;
1573
273cd173 1574 r3o = __pa(pudp) - pud_index(addr) * sizeof(pud_t);
d08de8e2 1575 r3o |= _ASCE_TYPE_REGION3;
28c807e5
MS		 1576 if (__builtin_constant_p(opt) && opt == 0) {
1577 /* flush without guest asce */
1578 asm volatile(
731efc96 1579 " idte %[r1],0,%[r2],%[m4]"
28c807e5
MS		 1580 : "+m" (*pudp)
1581 : [r1] "a" (r3o), [r2] "a" ((addr & PUD_MASK)),
1582 [m4] "i" (local)
1583 : "cc");
1584 } else {
1585 /* flush with guest asce */
1586 asm volatile(
731efc96 1587 " idte %[r1],%[r3],%[r2],%[m4]"
28c807e5
MS		 1588 : "+m" (*pudp)
1589 : [r1] "a" (r3o), [r2] "a" ((addr & PUD_MASK) | opt),
1590 [r3] "a" (asce), [m4] "i" (local)
1591 : "cc" );
1592 }
d08de8e2
GS		 1593}
1594
227be799
MS		 1595pmd_t pmdp_xchg_direct(struct mm_struct *, unsigned long, pmd_t *, pmd_t);
1596pmd_t pmdp_xchg_lazy(struct mm_struct *, unsigned long, pmd_t *, pmd_t);
d08de8e2 1597pud_t pudp_xchg_direct(struct mm_struct *, unsigned long, pud_t *, pud_t);
1b948d6c 1598
227be799
MS		 1599#ifdef CONFIG_TRANSPARENT_HUGEPAGE
1600
1601#define __HAVE_ARCH_PGTABLE_DEPOSIT
1602void pgtable_trans_huge_deposit(struct mm_struct *mm, pmd_t *pmdp,
1603 pgtable_t pgtable);
1604
1605#define __HAVE_ARCH_PGTABLE_WITHDRAW
1606pgtable_t pgtable_trans_huge_withdraw(struct mm_struct *mm, pmd_t *pmdp);
1b948d6c 1607
227be799
MS		 1608#define __HAVE_ARCH_PMDP_SET_ACCESS_FLAGS
1609static inline int pmdp_set_access_flags(struct vm_area_struct *vma,
1610 unsigned long addr, pmd_t *pmdp,
1611 pmd_t entry, int dirty)
3eabaee9 1612{
227be799 1613 VM_BUG_ON(addr & ~HPAGE_MASK);
3eabaee9 1614
227be799
MS		 1615 entry = pmd_mkyoung(entry);
1616 if (dirty)
1617 entry = pmd_mkdirty(entry);
1618 if (pmd_val(*pmdp) == pmd_val(entry))
1619 return 0;
1620 pmdp_xchg_direct(vma->vm_mm, addr, pmdp, entry);
1621 return 1;
3eabaee9
MS		 1622}
1623
227be799
MS		 1624#define __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG
1625static inline int pmdp_test_and_clear_young(struct vm_area_struct *vma,
1626 unsigned long addr, pmd_t *pmdp)
1627{
1628 pmd_t pmd = *pmdp;
106c992a 1629
227be799
MS		 1630 pmd = pmdp_xchg_direct(vma->vm_mm, addr, pmdp, pmd_mkold(pmd));
1631 return pmd_young(pmd);
1632}
106c992a 1633
227be799
MS		 1634#define __HAVE_ARCH_PMDP_CLEAR_YOUNG_FLUSH
1635static inline int pmdp_clear_flush_young(struct vm_area_struct *vma,
1636 unsigned long addr, pmd_t *pmdp)
1637{
1638 VM_BUG_ON(addr & ~HPAGE_MASK);
1639 return pmdp_test_and_clear_young(vma, addr, pmdp);
1640}
106c992a 1641
106c992a
GS		 1642static inline void set_pmd_at(struct mm_struct *mm, unsigned long addr,
1643 pmd_t *pmdp, pmd_t entry)
1644{
57d7f939 1645 if (!MACHINE_HAS_NX)
4a366f51 1646 entry = clear_pmd_bit(entry, __pgprot(_SEGMENT_ENTRY_NOEXEC));
b8e3b379 1647 set_pmd(pmdp, entry);
106c992a
GS		 1648}
1649
1650static inline pmd_t pmd_mkhuge(pmd_t pmd)
1651{
4a366f51
HC		 1652 pmd = set_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_LARGE));
1653 pmd = set_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_YOUNG));
1654 return set_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_PROTECT));
1ae1c1d0
GS		 1655}
1656
8809aa2d
AK		 1657#define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR
1658static inline pmd_t pmdp_huge_get_and_clear(struct mm_struct *mm,
227be799 1659 unsigned long addr, pmd_t *pmdp)
1ae1c1d0 1660{
54397bb0 1661 return pmdp_xchg_direct(mm, addr, pmdp, __pmd(_SEGMENT_ENTRY_EMPTY));
1ae1c1d0
GS		 1662}
1663
8809aa2d 1664#define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR_FULL
93a98695 1665static inline pmd_t pmdp_huge_get_and_clear_full(struct vm_area_struct *vma,
227be799 1666 unsigned long addr,
8809aa2d 1667 pmd_t *pmdp, int full)
fcbe08d6 1668{
227be799
MS		 1669 if (full) {
1670 pmd_t pmd = *pmdp;
b8e3b379 1671 set_pmd(pmdp, __pmd(_SEGMENT_ENTRY_EMPTY));
227be799
MS		 1672 return pmd;
1673 }
93a98695 1674 return pmdp_xchg_lazy(vma->vm_mm, addr, pmdp, __pmd(_SEGMENT_ENTRY_EMPTY));
fcbe08d6
MS		 1675}
1676
8809aa2d
AK		 1677#define __HAVE_ARCH_PMDP_HUGE_CLEAR_FLUSH
1678static inline pmd_t pmdp_huge_clear_flush(struct vm_area_struct *vma,
227be799 1679 unsigned long addr, pmd_t *pmdp)
1ae1c1d0 1680{
227be799 1681 return pmdp_huge_get_and_clear(vma->vm_mm, addr, pmdp);
1ae1c1d0
GS		 1682}
1683
1684#define __HAVE_ARCH_PMDP_INVALIDATE
9c4563f1 1685static inline pmd_t pmdp_invalidate(struct vm_area_struct *vma,
227be799 1686 unsigned long addr, pmd_t *pmdp)
1ae1c1d0 1687{
91c575b3
GS		 1688 pmd_t pmd = __pmd(pmd_val(*pmdp) | _SEGMENT_ENTRY_INVALID);
1689
9c4563f1 1690 return pmdp_xchg_direct(vma->vm_mm, addr, pmdp, pmd);
1ae1c1d0
GS		 1691}
1692
be328650
GS		 1693#define __HAVE_ARCH_PMDP_SET_WRPROTECT
1694static inline void pmdp_set_wrprotect(struct mm_struct *mm,
227be799 1695 unsigned long addr, pmd_t *pmdp)
be328650
GS		 1696{
1697 pmd_t pmd = *pmdp;
1698
227be799
MS		 1699 if (pmd_write(pmd))
1700 pmd = pmdp_xchg_lazy(mm, addr, pmdp, pmd_wrprotect(pmd));
be328650
GS		 1701}
1702
f28b6ff8
AK		 1703static inline pmd_t pmdp_collapse_flush(struct vm_area_struct *vma,
1704 unsigned long address,
1705 pmd_t *pmdp)
1706{
8809aa2d 1707 return pmdp_huge_get_and_clear(vma->vm_mm, address, pmdp);
f28b6ff8
AK		 1708}
1709#define pmdp_collapse_flush pmdp_collapse_flush
1710
0f3bf303 1711#define pfn_pmd(pfn, pgprot) mk_pmd_phys(((pfn) << PAGE_SHIFT), (pgprot))
1ae1c1d0
GS		 1712#define mk_pmd(page, pgprot) pfn_pmd(page_to_pfn(page), (pgprot))
1713
1714static inline int pmd_trans_huge(pmd_t pmd)
1715{
1716 return pmd_val(pmd) & _SEGMENT_ENTRY_LARGE;
1717}
1718
fd8cfd30 1719#define has_transparent_hugepage has_transparent_hugepage
1ae1c1d0
GS		 1720static inline int has_transparent_hugepage(void)
1721{
466178fc 1722 return MACHINE_HAS_EDAT1 ? 1 : 0;
1ae1c1d0 1723}
75077afb
GS		 1724#endif /* CONFIG_TRANSPARENT_HUGEPAGE */
1725
1da177e4 1726/*
1da177e4
LT		 1727 * 64 bit swap entry format:
1728 * A page-table entry has some bits we have to treat in a special way.
8043d26c
DH		 1729 * Bits 54 and 63 are used to indicate the page type. Bit 53 marks the pte
1730 * as invalid.
a1c843b8 1731 * A swap pte is indicated by bit pattern (pte & 0x201) == 0x200
92cd58bd 1732 * | offset |E11XX|type |S0|
a1c843b8
MS		 1733 * |0000000000111111111122222222223333333333444444444455|55555|55566|66|
1734 * |0123456789012345678901234567890123456789012345678901|23456|78901|23|
8043d26c
DH		 1735 *
1736 * Bits 0-51 store the offset.
92cd58bd 1737 * Bit 52 (E) is used to remember PG_anon_exclusive.
8043d26c
DH		 1738 * Bits 57-61 store the type.
1739 * Bit 62 (S) is used for softdirty tracking.
92cd58bd 1740 * Bits 55 and 56 (X) are unused.
1da177e4 1741 */
5a79859a 1742
a1c843b8
MS		 1743#define __SWP_OFFSET_MASK ((1UL << 52) - 1)
1744#define __SWP_OFFSET_SHIFT 12
1745#define __SWP_TYPE_MASK ((1UL << 5) - 1)
1746#define __SWP_TYPE_SHIFT 2
5a79859a 1747
4448aaf0 1748static inline pte_t mk_swap_pte(unsigned long type, unsigned long offset)
1da177e4 1749{
4a366f51 1750 unsigned long pteval;
a1c843b8 1751
4a366f51
HC		 1752 pteval = _PAGE_INVALID | _PAGE_PROTECT;
1753 pteval |= (offset & __SWP_OFFSET_MASK) << __SWP_OFFSET_SHIFT;
1754 pteval |= (type & __SWP_TYPE_MASK) << __SWP_TYPE_SHIFT;
1755 return __pte(pteval);
1da177e4
LT		 1756}
1757
a1c843b8
MS		 1758static inline unsigned long __swp_type(swp_entry_t entry)
1759{
1760 return (entry.val >> __SWP_TYPE_SHIFT) & __SWP_TYPE_MASK;
1761}
1762
1763static inline unsigned long __swp_offset(swp_entry_t entry)
1764{
1765 return (entry.val >> __SWP_OFFSET_SHIFT) & __SWP_OFFSET_MASK;
1766}
1767
1768static inline swp_entry_t __swp_entry(unsigned long type, unsigned long offset)
1769{
1770 return (swp_entry_t) { pte_val(mk_swap_pte(type, offset)) };
1771}
1da177e4
LT		 1772
1773#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
1774#define __swp_entry_to_pte(x) ((pte_t) { (x).val })
1775
17f34580 1776extern int vmem_add_mapping(unsigned long start, unsigned long size);
f05f62d0 1777extern void vmem_remove_mapping(unsigned long start, unsigned long size);
4df29d2b
AG		 1778extern int __vmem_map_4k_page(unsigned long addr, unsigned long phys, pgprot_t prot, bool alloc);
1779extern int vmem_map_4k_page(unsigned long addr, unsigned long phys, pgprot_t prot);
1780extern void vmem_unmap_4k_page(unsigned long addr);
2f0e8aae 1781extern pte_t *vmem_get_alloc_pte(unsigned long addr, bool alloc);
402b0862 1782extern int s390_enable_sie(void);
3ac8e380 1783extern int s390_enable_skey(void);
a13cff31 1784extern void s390_reset_cmma(struct mm_struct *mm);
f4eb07c1 1785
1f6b83e5
MS		 1786/* s390 has a private copy of get unmapped area to deal with cache synonyms */
1787#define HAVE_ARCH_UNMAPPED_AREA
1788#define HAVE_ARCH_UNMAPPED_AREA_TOPDOWN
1789
1c2f7d14
AK		 1790#define pmd_pgtable(pmd) \
1791 ((pgtable_t)__va(pmd_val(pmd) & -sizeof(pte_t)*PTRS_PER_PTE))
1792
1da177e4 1793#endif /* _S390_PAGE_H */
Linux 6.x block layer and io_uring tree(s)