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Merge tag 'mm-stable-2024-05-17-19-19' of git://git.kernel.org/pub/scm/linux/kernel...
[linux-2.6-block.git] / arch / s390 / include / asm / pgtable.h
CommitLineData
b2441318 1/* SPDX-License-Identifier: GPL-2.0 */
1da177e4 2/*
1da177e4 3 * S390 version
a53c8fab 4 * Copyright IBM Corp. 1999, 2000
1da177e4
LT		 5 * Author(s): Hartmut Penner (hp@de.ibm.com)
6 * Ulrich Weigand (weigand@de.ibm.com)
7 * Martin Schwidefsky (schwidefsky@de.ibm.com)
8 *
9 * Derived from "include/asm-i386/pgtable.h"
10 */
11
12#ifndef _ASM_S390_PGTABLE_H
13#define _ASM_S390_PGTABLE_H
14
9789db08 15#include <linux/sched.h>
2dcea57a 16#include <linux/mm_types.h>
abf09bed 17#include <linux/page-flags.h>
527e30b4 18#include <linux/radix-tree.h>
37cd944c 19#include <linux/atomic.h>
0c4f2623 20#include <asm/sections.h>
527618ab 21#include <asm/ctlreg.h>
1da177e4 22#include <asm/bug.h>
b2fa47e6 23#include <asm/page.h>
214d9bbc 24#include <asm/uv.h>
1da177e4 25
0ccb32c9 26extern pgd_t swapper_pg_dir[];
bb1520d5 27extern pgd_t invalid_pg_dir[];
1da177e4 28extern void paging_init(void);
527618ab 29extern struct ctlreg s390_invalid_asce;
1da177e4 30
37cd944c
HC		 31enum {
32 PG_DIRECT_MAP_4K = 0,
33 PG_DIRECT_MAP_1M,
34 PG_DIRECT_MAP_2G,
35 PG_DIRECT_MAP_MAX
36};
37
81e84796 38extern atomic_long_t __bootdata_preserved(direct_pages_count[PG_DIRECT_MAP_MAX]);
37cd944c
HC		 39
40static inline void update_page_count(int level, long count)
41{
42 if (IS_ENABLED(CONFIG_PROC_FS))
43 atomic_long_add(count, &direct_pages_count[level]);
44}
45
1da177e4
LT		 46/*
47 * The S390 doesn't have any external MMU info: the kernel page
48 * tables contain all the necessary information.
49 */
4b3073e1 50#define update_mmu_cache(vma, address, ptep) do { } while (0)
843f9310 51#define update_mmu_cache_range(vmf, vma, addr, ptep, nr) do { } while (0)
b113da65 52#define update_mmu_cache_pmd(vma, address, ptep) do { } while (0)
1da177e4
LT		 53
54/*
238ec4ef 55 * ZERO_PAGE is a global shared page that is always zero; used
1da177e4
LT		 56 * for zero-mapped memory areas etc..
57 */
238ec4ef
MS		 58
59extern unsigned long empty_zero_page;
60extern unsigned long zero_page_mask;
61
62#define ZERO_PAGE(vaddr) \
63 (virt_to_page((void *)(empty_zero_page + \
64 (((unsigned long)(vaddr)) &zero_page_mask))))
816422ad 65#define __HAVE_COLOR_ZERO_PAGE
238ec4ef 66
4f2e2903 67/* TODO: s390 cannot support io_remap_pfn_range... */
1da177e4 68
1da177e4 69#define pte_ERROR(e) \
bb50655b 70 pr_err("%s:%d: bad pte %016lx.\n", __FILE__, __LINE__, pte_val(e))
1da177e4 71#define pmd_ERROR(e) \
bb50655b 72 pr_err("%s:%d: bad pmd %016lx.\n", __FILE__, __LINE__, pmd_val(e))
190a1d72 73#define pud_ERROR(e) \
bb50655b 74 pr_err("%s:%d: bad pud %016lx.\n", __FILE__, __LINE__, pud_val(e))
1aea9b3f 75#define p4d_ERROR(e) \
bb50655b 76 pr_err("%s:%d: bad p4d %016lx.\n", __FILE__, __LINE__, p4d_val(e))
1da177e4 77#define pgd_ERROR(e) \
bb50655b 78 pr_err("%s:%d: bad pgd %016lx.\n", __FILE__, __LINE__, pgd_val(e))
1da177e4 79
1da177e4 80/*
a1c843b8 81 * The vmalloc and module area will always be on the topmost area of the
fc67c880
HC		 82 * kernel mapping. 512GB are reserved for vmalloc by default.
83 * At the top of the vmalloc area a 2GB area is reserved where modules
84 * will reside. That makes sure that inter module branches always
85 * happen without trampolines and in addition the placement within a
86 * 2GB frame is branch prediction unit friendly.
8b62bc96 87 */
0c4f2623
VG		 88extern unsigned long __bootdata_preserved(VMALLOC_START);
89extern unsigned long __bootdata_preserved(VMALLOC_END);
fc67c880 90#define VMALLOC_DEFAULT_SIZE ((512UL << 30) - MODULES_LEN)
0c4f2623
VG		 91extern struct page *__bootdata_preserved(vmemmap);
92extern unsigned long __bootdata_preserved(vmemmap_size);
239a6425 93
0c4f2623
VG		 94extern unsigned long __bootdata_preserved(MODULES_VADDR);
95extern unsigned long __bootdata_preserved(MODULES_END);
c972cc60
HC		 96#define MODULES_VADDR MODULES_VADDR
97#define MODULES_END MODULES_END
98#define MODULES_LEN (1UL << 31)
c972cc60 99
c933146a
HC		 100static inline int is_module_addr(void *addr)
101{
c933146a
HC		 102 BUILD_BUG_ON(MODULES_LEN > (1UL << 31));
103 if (addr < (void *)MODULES_VADDR)
104 return 0;
105 if (addr > (void *)MODULES_END)
106 return 0;
c933146a
HC		 107 return 1;
108}
109
c98d2eca
AG		 110#ifdef CONFIG_RANDOMIZE_BASE
111#define KASLR_LEN (1UL << 31)
112#else
113#define KASLR_LEN 0UL
114#endif
115
1da177e4 116/*
1da177e4 117 * A 64 bit pagetable entry of S390 has following format:
6a985c61 118 * | PFRA |0IPC| OS |
1da177e4
LT		 119 * 0000000000111111111122222222223333333333444444444455555555556666
120 * 0123456789012345678901234567890123456789012345678901234567890123
121 *
122 * I Page-Invalid Bit: Page is not available for address-translation
123 * P Page-Protection Bit: Store access not possible for page
6a985c61 124 * C Change-bit override: HW is not required to set change bit
1da177e4
LT		 125 *
126 * A 64 bit segmenttable entry of S390 has following format:
127 * | P-table origin | TT
128 * 0000000000111111111122222222223333333333444444444455555555556666
129 * 0123456789012345678901234567890123456789012345678901234567890123
130 *
131 * I Segment-Invalid Bit: Segment is not available for address-translation
132 * C Common-Segment Bit: Segment is not private (PoP 3-30)
133 * P Page-Protection Bit: Store access not possible for page
134 * TT Type 00
135 *
136 * A 64 bit region table entry of S390 has following format:
137 * | S-table origin | TF TTTL
138 * 0000000000111111111122222222223333333333444444444455555555556666
139 * 0123456789012345678901234567890123456789012345678901234567890123
140 *
141 * I Segment-Invalid Bit: Segment is not available for address-translation
142 * TT Type 01
143 * TF
190a1d72 144 * TL Table length
1da177e4
LT		 145 *
146 * The 64 bit regiontable origin of S390 has following format:
147 * | region table origon | DTTL
148 * 0000000000111111111122222222223333333333444444444455555555556666
149 * 0123456789012345678901234567890123456789012345678901234567890123
150 *
151 * X Space-Switch event:
152 * G Segment-Invalid Bit:
153 * P Private-Space Bit:
154 * S Storage-Alteration:
155 * R Real space
156 * TL Table-Length:
157 *
158 * A storage key has the following format:
159 * | ACC |F|R|C|0|
160 * 0 3 4 5 6 7
161 * ACC: access key
162 * F : fetch protection bit
163 * R : referenced bit
164 * C : changed bit
165 */
166
167/* Hardware bits in the page table entry */
57d7f939 168#define _PAGE_NOEXEC 0x100 /* HW no-execute bit */
e5098611 169#define _PAGE_PROTECT 0x200 /* HW read-only bit */
83377484 170#define _PAGE_INVALID 0x400 /* HW invalid bit */
e5098611 171#define _PAGE_LARGE 0x800 /* Bit to mark a large pte */
3610cce8
MS		 172
173/* Software bits in the page table entry */
e5098611 174#define _PAGE_PRESENT 0x001 /* SW pte present bit */
e5098611
MS		 175#define _PAGE_YOUNG 0x004 /* SW pte young bit */
176#define _PAGE_DIRTY 0x008 /* SW pte dirty bit */
0944fe3f
MS		 177#define _PAGE_READ 0x010 /* SW pte read bit */
178#define _PAGE_WRITE 0x020 /* SW pte write bit */
179#define _PAGE_SPECIAL 0x040 /* SW associated with special page */
b31288fa 180#define _PAGE_UNUSED 0x080 /* SW bit for pgste usage state */
1da177e4 181
5614dd92
MS		 182#ifdef CONFIG_MEM_SOFT_DIRTY
183#define _PAGE_SOFT_DIRTY 0x002 /* SW pte soft dirty bit */
184#else
185#define _PAGE_SOFT_DIRTY 0x000
186#endif
187
0807b856
GS		 188#define _PAGE_SW_BITS 0xffUL /* All SW bits */
189
92cd58bd
DH		 190#define _PAGE_SWP_EXCLUSIVE _PAGE_LARGE /* SW pte exclusive swap bit */
191
138c9021 192/* Set of bits not changed in pte_modify */
6a5c1482 193#define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_SPECIAL | _PAGE_DIRTY | \
5614dd92 194 _PAGE_YOUNG | _PAGE_SOFT_DIRTY)
53492b1d 195
0807b856
GS		 196/*
197 * Mask of bits that must not be changed with RDP. Allow only _PAGE_PROTECT
198 * HW bit and all SW bits.
199 */
200#define _PAGE_RDP_MASK ~(_PAGE_PROTECT | _PAGE_SW_BITS)
201
83377484 202/*
6e76d4b2
KS		 203 * handle_pte_fault uses pte_present and pte_none to find out the pte type
204 * WITHOUT holding the page table lock. The _PAGE_PRESENT bit is used to
205 * distinguish present from not-present ptes. It is changed only with the page
206 * table lock held.
83377484 207 *
e5098611 208 * The following table gives the different possible bit combinations for
a1c843b8
MS		 209 * the pte hardware and software bits in the last 12 bits of a pte
210 * (. unassigned bit, x don't care, t swap type):
83377484 211 *
0944fe3f
MS		 212 * 842100000000
213 * 000084210000
214 * 000000008421
a1c843b8
MS		 215 * .IR.uswrdy.p
216 * empty .10.00000000
217 * swap .11..ttttt.0
218 * prot-none, clean, old .11.xx0000.1
219 * prot-none, clean, young .11.xx0001.1
bc29b7ac
GS		 220 * prot-none, dirty, old .11.xx0010.1
221 * prot-none, dirty, young .11.xx0011.1
a1c843b8
MS		 222 * read-only, clean, old .11.xx0100.1
223 * read-only, clean, young .01.xx0101.1
224 * read-only, dirty, old .11.xx0110.1
225 * read-only, dirty, young .01.xx0111.1
226 * read-write, clean, old .11.xx1100.1
227 * read-write, clean, young .01.xx1101.1
228 * read-write, dirty, old .10.xx1110.1
229 * read-write, dirty, young .00.xx1111.1
230 * HW-bits: R read-only, I invalid
231 * SW-bits: p present, y young, d dirty, r read, w write, s special,
232 * u unused, l large
e5098611 233 *
a1c843b8
MS		 234 * pte_none is true for the bit pattern .10.00000000, pte == 0x400
235 * pte_swap is true for the bit pattern .11..ooooo.0, (pte & 0x201) == 0x200
236 * pte_present is true for the bit pattern .xx.xxxxxx.1, (pte & 0x001) == 0x001
83377484
MS		 237 */
238
3610cce8 239/* Bits in the segment/region table address-space-control-element */
8457d775 240#define _ASCE_ORIGIN ~0xfffUL/* region/segment table origin */
3610cce8
MS		 241#define _ASCE_PRIVATE_SPACE 0x100 /* private space control */
242#define _ASCE_ALT_EVENT 0x80 /* storage alteration event control */
243#define _ASCE_SPACE_SWITCH 0x40 /* space switch event */
244#define _ASCE_REAL_SPACE 0x20 /* real space control */
245#define _ASCE_TYPE_MASK 0x0c /* asce table type mask */
246#define _ASCE_TYPE_REGION1 0x0c /* region first table type */
247#define _ASCE_TYPE_REGION2 0x08 /* region second table type */
248#define _ASCE_TYPE_REGION3 0x04 /* region third table type */
249#define _ASCE_TYPE_SEGMENT 0x00 /* segment table type */
250#define _ASCE_TABLE_LENGTH 0x03 /* region table length */
251
252/* Bits in the region table entry */
253#define _REGION_ENTRY_ORIGIN ~0xfffUL/* region/segment table origin */
e5098611 254#define _REGION_ENTRY_PROTECT 0x200 /* region protection bit */
57d7f939 255#define _REGION_ENTRY_NOEXEC 0x100 /* region no-execute bit */
4be130a0 256#define _REGION_ENTRY_OFFSET 0xc0 /* region table offset */
e5098611 257#define _REGION_ENTRY_INVALID 0x20 /* invalid region table entry */
c9f62152 258#define _REGION_ENTRY_TYPE_MASK 0x0c /* region table type mask */
3610cce8
MS		 259#define _REGION_ENTRY_TYPE_R1 0x0c /* region first table type */
260#define _REGION_ENTRY_TYPE_R2 0x08 /* region second table type */
261#define _REGION_ENTRY_TYPE_R3 0x04 /* region third table type */
262#define _REGION_ENTRY_LENGTH 0x03 /* region third length */
263
264#define _REGION1_ENTRY (_REGION_ENTRY_TYPE_R1 | _REGION_ENTRY_LENGTH)
e5098611 265#define _REGION1_ENTRY_EMPTY (_REGION_ENTRY_TYPE_R1 | _REGION_ENTRY_INVALID)
3610cce8 266#define _REGION2_ENTRY (_REGION_ENTRY_TYPE_R2 | _REGION_ENTRY_LENGTH)
e5098611 267#define _REGION2_ENTRY_EMPTY (_REGION_ENTRY_TYPE_R2 | _REGION_ENTRY_INVALID)
3610cce8 268#define _REGION3_ENTRY (_REGION_ENTRY_TYPE_R3 | _REGION_ENTRY_LENGTH)
e5098611 269#define _REGION3_ENTRY_EMPTY (_REGION_ENTRY_TYPE_R3 | _REGION_ENTRY_INVALID)
3610cce8 270
9e20b4da 271#define _REGION3_ENTRY_ORIGIN_LARGE ~0x7fffffffUL /* large page address */
2dffdcba
HC		 272#define _REGION3_ENTRY_DIRTY 0x2000 /* SW region dirty bit */
273#define _REGION3_ENTRY_YOUNG 0x1000 /* SW region young bit */
274#define _REGION3_ENTRY_LARGE 0x0400 /* RTTE-format control, large page */
275#define _REGION3_ENTRY_READ 0x0002 /* SW region read bit */
276#define _REGION3_ENTRY_WRITE 0x0001 /* SW region write bit */
277
278#ifdef CONFIG_MEM_SOFT_DIRTY
279#define _REGION3_ENTRY_SOFT_DIRTY 0x4000 /* SW region soft dirty bit */
280#else
281#define _REGION3_ENTRY_SOFT_DIRTY 0x0000 /* SW region soft dirty bit */
282#endif
283
1aea9b3f 284#define _REGION_ENTRY_BITS 0xfffffffffffff22fUL
d08de8e2 285
1da177e4 286/* Bits in the segment table entry */
58b7e200 287#define _SEGMENT_ENTRY_BITS 0xfffffffffffffe33UL
58b7e200
JF		 288#define _SEGMENT_ENTRY_HARDWARE_BITS 0xfffffffffffffe30UL
289#define _SEGMENT_ENTRY_HARDWARE_BITS_LARGE 0xfffffffffff00730UL
ea81531d 290#define _SEGMENT_ENTRY_ORIGIN_LARGE ~0xfffffUL /* large page address */
8457d775
HC		 291#define _SEGMENT_ENTRY_ORIGIN ~0x7ffUL/* page table origin */
292#define _SEGMENT_ENTRY_PROTECT 0x200 /* segment protection bit */
293#define _SEGMENT_ENTRY_NOEXEC 0x100 /* segment no-execute bit */
e5098611 294#define _SEGMENT_ENTRY_INVALID 0x20 /* invalid segment table entry */
c9f62152 295#define _SEGMENT_ENTRY_TYPE_MASK 0x0c /* segment table type mask */
1da177e4 296
3610cce8 297#define _SEGMENT_ENTRY (0)
e5098611 298#define _SEGMENT_ENTRY_EMPTY (_SEGMENT_ENTRY_INVALID)
3610cce8 299
152125b7
MS		 300#define _SEGMENT_ENTRY_DIRTY 0x2000 /* SW segment dirty bit */
301#define _SEGMENT_ENTRY_YOUNG 0x1000 /* SW segment young bit */
152125b7 302#define _SEGMENT_ENTRY_LARGE 0x0400 /* STE-format control, large page */
bc29b7ac
GS		 303#define _SEGMENT_ENTRY_WRITE 0x0002 /* SW segment write bit */
304#define _SEGMENT_ENTRY_READ 0x0001 /* SW segment read bit */
0944fe3f 305
5614dd92
MS		 306#ifdef CONFIG_MEM_SOFT_DIRTY
307#define _SEGMENT_ENTRY_SOFT_DIRTY 0x4000 /* SW segment soft dirty bit */
308#else
309#define _SEGMENT_ENTRY_SOFT_DIRTY 0x0000 /* SW segment soft dirty bit */
310#endif
311
c67da7c7
HC		 312#define _CRST_ENTRIES 2048 /* number of region/segment table entries */
313#define _PAGE_ENTRIES 256 /* number of page table entries */
314
315#define _CRST_TABLE_SIZE (_CRST_ENTRIES * 8)
316#define _PAGE_TABLE_SIZE (_PAGE_ENTRIES * 8)
317
318#define _REGION1_SHIFT 53
319#define _REGION2_SHIFT 42
320#define _REGION3_SHIFT 31
321#define _SEGMENT_SHIFT 20
322
323#define _REGION1_INDEX (0x7ffUL << _REGION1_SHIFT)
324#define _REGION2_INDEX (0x7ffUL << _REGION2_SHIFT)
325#define _REGION3_INDEX (0x7ffUL << _REGION3_SHIFT)
326#define _SEGMENT_INDEX (0x7ffUL << _SEGMENT_SHIFT)
327#define _PAGE_INDEX (0xffUL << _PAGE_SHIFT)
328
329#define _REGION1_SIZE (1UL << _REGION1_SHIFT)
330#define _REGION2_SIZE (1UL << _REGION2_SHIFT)
331#define _REGION3_SIZE (1UL << _REGION3_SHIFT)
332#define _SEGMENT_SIZE (1UL << _SEGMENT_SHIFT)
333
334#define _REGION1_MASK (~(_REGION1_SIZE - 1))
335#define _REGION2_MASK (~(_REGION2_SIZE - 1))
336#define _REGION3_MASK (~(_REGION3_SIZE - 1))
337#define _SEGMENT_MASK (~(_SEGMENT_SIZE - 1))
338
339#define PMD_SHIFT _SEGMENT_SHIFT
340#define PUD_SHIFT _REGION3_SHIFT
341#define P4D_SHIFT _REGION2_SHIFT
342#define PGDIR_SHIFT _REGION1_SHIFT
343
344#define PMD_SIZE _SEGMENT_SIZE
345#define PUD_SIZE _REGION3_SIZE
346#define P4D_SIZE _REGION2_SIZE
347#define PGDIR_SIZE _REGION1_SIZE
348
349#define PMD_MASK _SEGMENT_MASK
350#define PUD_MASK _REGION3_MASK
351#define P4D_MASK _REGION2_MASK
352#define PGDIR_MASK _REGION1_MASK
353
354#define PTRS_PER_PTE _PAGE_ENTRIES
355#define PTRS_PER_PMD _CRST_ENTRIES
356#define PTRS_PER_PUD _CRST_ENTRIES
357#define PTRS_PER_P4D _CRST_ENTRIES
358#define PTRS_PER_PGD _CRST_ENTRIES
359
0944fe3f 360/*
2dffdcba
HC		 361 * Segment table and region3 table entry encoding
362 * (R = read-only, I = invalid, y = young bit):
bc29b7ac 363 * dy..R...I...wr
152125b7
MS		 364 * prot-none, clean, old 00..1...1...00
365 * prot-none, clean, young 01..1...1...00
366 * prot-none, dirty, old 10..1...1...00
367 * prot-none, dirty, young 11..1...1...00
bc29b7ac
GS		 368 * read-only, clean, old 00..1...1...01
369 * read-only, clean, young 01..1...0...01
370 * read-only, dirty, old 10..1...1...01
371 * read-only, dirty, young 11..1...0...01
152125b7
MS		 372 * read-write, clean, old 00..1...1...11
373 * read-write, clean, young 01..1...0...11
374 * read-write, dirty, old 10..0...1...11
375 * read-write, dirty, young 11..0...0...11
0944fe3f
MS		 376 * The segment table origin is used to distinguish empty (origin==0) from
377 * read-write, old segment table entries (origin!=0)
a1c843b8
MS		 378 * HW-bits: R read-only, I invalid
379 * SW-bits: y young, d dirty, r read, w write
0944fe3f 380 */
e5098611 381
6c61cfe9 382/* Page status table bits for virtualization */
0d0dafc1
MS		 383#define PGSTE_ACC_BITS 0xf000000000000000UL
384#define PGSTE_FP_BIT 0x0800000000000000UL
385#define PGSTE_PCL_BIT 0x0080000000000000UL
386#define PGSTE_HR_BIT 0x0040000000000000UL
387#define PGSTE_HC_BIT 0x0020000000000000UL
388#define PGSTE_GR_BIT 0x0004000000000000UL
389#define PGSTE_GC_BIT 0x0002000000000000UL
0a61b222
MS		 390#define PGSTE_UC_BIT 0x0000800000000000UL /* user dirty (migration) */
391#define PGSTE_IN_BIT 0x0000400000000000UL /* IPTE notify bit */
4be130a0 392#define PGSTE_VSIE_BIT 0x0000200000000000UL /* ref'd in a shadow table */
6c61cfe9 393
b31288fa 394/* Guest Page State used for virtualization */
2d42f947 395#define _PGSTE_GPS_ZERO 0x0000000080000000UL
cd774b90 396#define _PGSTE_GPS_NODAT 0x0000000040000000UL
2d42f947
CI		 397#define _PGSTE_GPS_USAGE_MASK 0x0000000003000000UL
398#define _PGSTE_GPS_USAGE_STABLE 0x0000000000000000UL
399#define _PGSTE_GPS_USAGE_UNUSED 0x0000000001000000UL
400#define _PGSTE_GPS_USAGE_POT_VOLATILE 0x0000000002000000UL
401#define _PGSTE_GPS_USAGE_VOLATILE _PGSTE_GPS_USAGE_MASK
b31288fa 402
1da177e4 403/*
3610cce8
MS		 404 * A user page table pointer has the space-switch-event bit, the
405 * private-space-control bit and the storage-alteration-event-control
406 * bit set. A kernel page table pointer doesn't need them.
1da177e4 407 */
3610cce8
MS		 408#define _ASCE_USER_BITS (_ASCE_SPACE_SWITCH | _ASCE_PRIVATE_SPACE | \
409 _ASCE_ALT_EVENT)
1da177e4 410
1da177e4 411/*
9282ed92 412 * Page protection definitions.
1da177e4 413 */
bc29b7ac 414#define PAGE_NONE __pgprot(_PAGE_PRESENT | _PAGE_INVALID | _PAGE_PROTECT)
57d7f939
MS		 415#define PAGE_RO __pgprot(_PAGE_PRESENT | _PAGE_READ | \
416 _PAGE_NOEXEC | _PAGE_INVALID | _PAGE_PROTECT)
417#define PAGE_RX __pgprot(_PAGE_PRESENT | _PAGE_READ | \
0944fe3f 418 _PAGE_INVALID | _PAGE_PROTECT)
57d7f939
MS		 419#define PAGE_RW __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \
420 _PAGE_NOEXEC | _PAGE_INVALID | _PAGE_PROTECT)
421#define PAGE_RWX __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \
0944fe3f
MS		 422 _PAGE_INVALID | _PAGE_PROTECT)
423
424#define PAGE_SHARED __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \
57d7f939 425 _PAGE_YOUNG | _PAGE_DIRTY | _PAGE_NOEXEC)
0944fe3f 426#define PAGE_KERNEL __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \
57d7f939 427 _PAGE_YOUNG | _PAGE_DIRTY | _PAGE_NOEXEC)
0944fe3f 428#define PAGE_KERNEL_RO __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_YOUNG | \
57d7f939
MS		 429 _PAGE_PROTECT | _PAGE_NOEXEC)
430#define PAGE_KERNEL_EXEC __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \
431 _PAGE_YOUNG | _PAGE_DIRTY)
1da177e4
LT		 432
433/*
043d0708
MS		 434 * On s390 the page table entry has an invalid bit and a read-only bit.
435 * Read permission implies execute permission and write permission
436 * implies read permission.
1da177e4
LT		 437 */
438 /*xwr*/
1da177e4 439
106c992a
GS		 440/*
441 * Segment entry (large page) protection definitions.
442 */
e5098611
MS		 443#define SEGMENT_NONE __pgprot(_SEGMENT_ENTRY_INVALID | \
444 _SEGMENT_ENTRY_PROTECT)
57d7f939
MS		 445#define SEGMENT_RO __pgprot(_SEGMENT_ENTRY_PROTECT | \
446 _SEGMENT_ENTRY_READ | \
447 _SEGMENT_ENTRY_NOEXEC)
448#define SEGMENT_RX __pgprot(_SEGMENT_ENTRY_PROTECT | \
152125b7 449 _SEGMENT_ENTRY_READ)
57d7f939
MS		 450#define SEGMENT_RW __pgprot(_SEGMENT_ENTRY_READ | \
451 _SEGMENT_ENTRY_WRITE | \
452 _SEGMENT_ENTRY_NOEXEC)
453#define SEGMENT_RWX __pgprot(_SEGMENT_ENTRY_READ | \
152125b7 454 _SEGMENT_ENTRY_WRITE)
2dffdcba
HC		 455#define SEGMENT_KERNEL __pgprot(_SEGMENT_ENTRY | \
456 _SEGMENT_ENTRY_LARGE | \
457 _SEGMENT_ENTRY_READ | \
458 _SEGMENT_ENTRY_WRITE | \
459 _SEGMENT_ENTRY_YOUNG | \
57d7f939
MS		 460 _SEGMENT_ENTRY_DIRTY | \
461 _SEGMENT_ENTRY_NOEXEC)
2dffdcba
HC		 462#define SEGMENT_KERNEL_RO __pgprot(_SEGMENT_ENTRY | \
463 _SEGMENT_ENTRY_LARGE | \
464 _SEGMENT_ENTRY_READ | \
465 _SEGMENT_ENTRY_YOUNG | \
57d7f939
MS		 466 _SEGMENT_ENTRY_PROTECT | \
467 _SEGMENT_ENTRY_NOEXEC)
d58106c3
VG		 468#define SEGMENT_KERNEL_EXEC __pgprot(_SEGMENT_ENTRY | \
469 _SEGMENT_ENTRY_LARGE | \
470 _SEGMENT_ENTRY_READ | \
471 _SEGMENT_ENTRY_WRITE | \
472 _SEGMENT_ENTRY_YOUNG | \
473 _SEGMENT_ENTRY_DIRTY)
2dffdcba
HC		 474
475/*
476 * Region3 entry (large page) protection definitions.
477 */
478
479#define REGION3_KERNEL __pgprot(_REGION_ENTRY_TYPE_R3 | \
480 _REGION3_ENTRY_LARGE | \
481 _REGION3_ENTRY_READ | \
482 _REGION3_ENTRY_WRITE | \
483 _REGION3_ENTRY_YOUNG | \
57d7f939
MS		 484 _REGION3_ENTRY_DIRTY | \
485 _REGION_ENTRY_NOEXEC)
2dffdcba
HC		 486#define REGION3_KERNEL_RO __pgprot(_REGION_ENTRY_TYPE_R3 | \
487 _REGION3_ENTRY_LARGE | \
488 _REGION3_ENTRY_READ | \
489 _REGION3_ENTRY_YOUNG | \
57d7f939
MS		 490 _REGION_ENTRY_PROTECT | \
491 _REGION_ENTRY_NOEXEC)
b2658540
AG		 492#define REGION3_KERNEL_EXEC __pgprot(_REGION_ENTRY_TYPE_R3 | \
493 _REGION3_ENTRY_LARGE | \
494 _REGION3_ENTRY_READ | \
495 _REGION3_ENTRY_WRITE | \
496 _REGION3_ENTRY_YOUNG | \
497 _REGION3_ENTRY_DIRTY)
106c992a 498
e12e4044
MS		 499static inline bool mm_p4d_folded(struct mm_struct *mm)
500{
501 return mm->context.asce_limit <= _REGION1_SIZE;
502}
503#define mm_p4d_folded(mm) mm_p4d_folded(mm)
504
505static inline bool mm_pud_folded(struct mm_struct *mm)
506{
507 return mm->context.asce_limit <= _REGION2_SIZE;
508}
509#define mm_pud_folded(mm) mm_pud_folded(mm)
510
511static inline bool mm_pmd_folded(struct mm_struct *mm)
512{
513 return mm->context.asce_limit <= _REGION3_SIZE;
514}
515#define mm_pmd_folded(mm) mm_pmd_folded(mm)
516
b2fa47e6
MS		 517static inline int mm_has_pgste(struct mm_struct *mm)
518{
519#ifdef CONFIG_PGSTE
520 if (unlikely(mm->context.has_pgste))
521 return 1;
522#endif
523 return 0;
524}
65eef335 525
214d9bbc
CI		 526static inline int mm_is_protected(struct mm_struct *mm)
527{
528#ifdef CONFIG_PGSTE
07fbdf7f 529 if (unlikely(atomic_read(&mm->context.protected_count)))
214d9bbc
CI		 530 return 1;
531#endif
532 return 0;
533}
534
0b46e0a3
MS		 535static inline int mm_alloc_pgste(struct mm_struct *mm)
536{
537#ifdef CONFIG_PGSTE
538 if (unlikely(mm->context.alloc_pgste))
539 return 1;
540#endif
541 return 0;
542}
543
f29111f1
HC		 544static inline pte_t clear_pte_bit(pte_t pte, pgprot_t prot)
545{
546 return __pte(pte_val(pte) & ~pgprot_val(prot));
547}
548
549static inline pte_t set_pte_bit(pte_t pte, pgprot_t prot)
550{
551 return __pte(pte_val(pte) | pgprot_val(prot));
552}
553
554static inline pmd_t clear_pmd_bit(pmd_t pmd, pgprot_t prot)
555{
556 return __pmd(pmd_val(pmd) & ~pgprot_val(prot));
557}
558
559static inline pmd_t set_pmd_bit(pmd_t pmd, pgprot_t prot)
560{
561 return __pmd(pmd_val(pmd) | pgprot_val(prot));
562}
563
564static inline pud_t clear_pud_bit(pud_t pud, pgprot_t prot)
565{
566 return __pud(pud_val(pud) & ~pgprot_val(prot));
567}
568
569static inline pud_t set_pud_bit(pud_t pud, pgprot_t prot)
570{
571 return __pud(pud_val(pud) | pgprot_val(prot));
572}
573
2faee8ff 574/*
06201e00
DH		 575 * As soon as the guest uses storage keys or enables PV, we deduplicate all
576 * mapped shared zeropages and prevent new shared zeropages from getting
577 * mapped.
2faee8ff 578 */
06201e00
DH		 579#define mm_forbids_zeropage mm_forbids_zeropage
580static inline int mm_forbids_zeropage(struct mm_struct *mm)
581{
582#ifdef CONFIG_PGSTE
583 if (!mm->context.allow_cow_sharing)
584 return 1;
585#endif
586 return 0;
587}
588
55531b74 589static inline int mm_uses_skeys(struct mm_struct *mm)
65eef335
DD		 590{
591#ifdef CONFIG_PGSTE
55531b74 592 if (mm->context.uses_skeys)
65eef335
DD		 593 return 1;
594#endif
595 return 0;
596}
597
4ccccc52
HC		 598static inline void csp(unsigned int *ptr, unsigned int old, unsigned int new)
599{
53c1c250 600 union register_pair r1 = { .even = old, .odd = new, };
4ccccc52
HC		 601 unsigned long address = (unsigned long)ptr | 1;
602
603 asm volatile(
53c1c250
HC		 604 " csp %[r1],%[address]"
605 : [r1] "+&d" (r1.pair), "+m" (*ptr)
606 : [address] "d" (address)
4ccccc52
HC		 607 : "cc");
608}
609
e8a97e42
HC		 610static inline void cspg(unsigned long *ptr, unsigned long old, unsigned long new)
611{
53c1c250 612 union register_pair r1 = { .even = old, .odd = new, };
e8a97e42
HC		 613 unsigned long address = (unsigned long)ptr | 1;
614
615 asm volatile(
731efc96 616 " cspg %[r1],%[address]"
53c1c250
HC		 617 : [r1] "+&d" (r1.pair), "+m" (*ptr)
618 : [address] "d" (address)
e8a97e42
HC		 619 : "cc");
620}
621
622#define CRDTE_DTT_PAGE 0x00UL
623#define CRDTE_DTT_SEGMENT 0x10UL
624#define CRDTE_DTT_REGION3 0x14UL
625#define CRDTE_DTT_REGION2 0x18UL
626#define CRDTE_DTT_REGION1 0x1cUL
627
628static inline void crdte(unsigned long old, unsigned long new,
273cd173 629 unsigned long *table, unsigned long dtt,
e8a97e42
HC		 630 unsigned long address, unsigned long asce)
631{
53c1c250 632 union register_pair r1 = { .even = old, .odd = new, };
273cd173 633 union register_pair r2 = { .even = __pa(table) | dtt, .odd = address, };
e8a97e42 634
53c1c250
HC		 635 asm volatile(".insn rrf,0xb98f0000,%[r1],%[r2],%[asce],0"
636 : [r1] "+&d" (r1.pair)
637 : [r2] "d" (r2.pair), [asce] "a" (asce)
e8a97e42
HC		 638 : "memory", "cc");
639}
640
1da177e4 641/*
cc18b460 642 * pgd/p4d/pud/pmd/pte query functions
1da177e4 643 */
cc18b460
HC		 644static inline int pgd_folded(pgd_t pgd)
645{
646 return (pgd_val(pgd) & _REGION_ENTRY_TYPE_MASK) < _REGION_ENTRY_TYPE_R1;
647}
648
5a216a20
MS		 649static inline int pgd_present(pgd_t pgd)
650{
cc18b460 651 if (pgd_folded(pgd))
6252d702 652 return 1;
5a216a20
MS		 653 return (pgd_val(pgd) & _REGION_ENTRY_ORIGIN) != 0UL;
654}
655
656static inline int pgd_none(pgd_t pgd)
657{
cc18b460 658 if (pgd_folded(pgd))
6252d702 659 return 0;
e5098611 660 return (pgd_val(pgd) & _REGION_ENTRY_INVALID) != 0UL;
5a216a20
MS		 661}
662
663static inline int pgd_bad(pgd_t pgd)
664{
c9f62152
MS		 665 if ((pgd_val(pgd) & _REGION_ENTRY_TYPE_MASK) < _REGION_ENTRY_TYPE_R1)
666 return 0;
667 return (pgd_val(pgd) & ~_REGION_ENTRY_BITS) != 0;
5a216a20 668}
190a1d72 669
d0e2eb0a
VG		 670static inline unsigned long pgd_pfn(pgd_t pgd)
671{
672 unsigned long origin_mask;
673
674 origin_mask = _REGION_ENTRY_ORIGIN;
675 return (pgd_val(pgd) & origin_mask) >> PAGE_SHIFT;
676}
677
cc18b460
HC		 678static inline int p4d_folded(p4d_t p4d)
679{
680 return (p4d_val(p4d) & _REGION_ENTRY_TYPE_MASK) < _REGION_ENTRY_TYPE_R2;
681}
682
1aea9b3f
MS		 683static inline int p4d_present(p4d_t p4d)
684{
cc18b460 685 if (p4d_folded(p4d))
1aea9b3f
MS		 686 return 1;
687 return (p4d_val(p4d) & _REGION_ENTRY_ORIGIN) != 0UL;
688}
689
690static inline int p4d_none(p4d_t p4d)
691{
cc18b460 692 if (p4d_folded(p4d))
1aea9b3f
MS		 693 return 0;
694 return p4d_val(p4d) == _REGION2_ENTRY_EMPTY;
695}
696
697static inline unsigned long p4d_pfn(p4d_t p4d)
698{
699 unsigned long origin_mask;
700
701 origin_mask = _REGION_ENTRY_ORIGIN;
702 return (p4d_val(p4d) & origin_mask) >> PAGE_SHIFT;
703}
704
cc18b460
HC		 705static inline int pud_folded(pud_t pud)
706{
707 return (pud_val(pud) & _REGION_ENTRY_TYPE_MASK) < _REGION_ENTRY_TYPE_R3;
708}
709
190a1d72 710static inline int pud_present(pud_t pud)
1da177e4 711{
cc18b460 712 if (pud_folded(pud))
6252d702 713 return 1;
0d017923 714 return (pud_val(pud) & _REGION_ENTRY_ORIGIN) != 0UL;
1da177e4
LT		 715}
716
190a1d72 717static inline int pud_none(pud_t pud)
1da177e4 718{
cc18b460 719 if (pud_folded(pud))
6252d702 720 return 0;
d08de8e2 721 return pud_val(pud) == _REGION3_ENTRY_EMPTY;
1da177e4
LT		 722}
723
e72c7c2b 724#define pud_leaf pud_leaf
c05995b7 725static inline bool pud_leaf(pud_t pud)
18da2369
HC		 726{
727 if ((pud_val(pud) & _REGION_ENTRY_TYPE_MASK) != _REGION_ENTRY_TYPE_R3)
728 return 0;
729 return !!(pud_val(pud) & _REGION3_ENTRY_LARGE);
730}
731
e72c7c2b 732#define pmd_leaf pmd_leaf
c05995b7 733static inline bool pmd_leaf(pmd_t pmd)
d08de8e2
GS		 734{
735 return (pmd_val(pmd) & _SEGMENT_ENTRY_LARGE) != 0;
736}
737
738static inline int pmd_bad(pmd_t pmd)
739{
2f709f7b 740 if ((pmd_val(pmd) & _SEGMENT_ENTRY_TYPE_MASK) > 0 || pmd_leaf(pmd))
c9f62152 741 return 1;
d08de8e2
GS		 742 return (pmd_val(pmd) & ~_SEGMENT_ENTRY_BITS) != 0;
743}
744
190a1d72 745static inline int pud_bad(pud_t pud)
1da177e4 746{
c9f62152
MS		 747 unsigned long type = pud_val(pud) & _REGION_ENTRY_TYPE_MASK;
748
0a845e0f 749 if (type > _REGION_ENTRY_TYPE_R3 || pud_leaf(pud))
c9f62152
MS		 750 return 1;
751 if (type < _REGION_ENTRY_TYPE_R3)
752 return 0;
d08de8e2 753 return (pud_val(pud) & ~_REGION_ENTRY_BITS) != 0;
1da177e4
LT		 754}
755
1aea9b3f
MS		 756static inline int p4d_bad(p4d_t p4d)
757{
c9f62152
MS		 758 unsigned long type = p4d_val(p4d) & _REGION_ENTRY_TYPE_MASK;
759
760 if (type > _REGION_ENTRY_TYPE_R2)
761 return 1;
762 if (type < _REGION_ENTRY_TYPE_R2)
763 return 0;
1aea9b3f
MS		 764 return (p4d_val(p4d) & ~_REGION_ENTRY_BITS) != 0;
765}
766
4448aaf0 767static inline int pmd_present(pmd_t pmd)
1da177e4 768{
54397bb0 769 return pmd_val(pmd) != _SEGMENT_ENTRY_EMPTY;
1da177e4
LT		 770}
771
4448aaf0 772static inline int pmd_none(pmd_t pmd)
1da177e4 773{
54397bb0 774 return pmd_val(pmd) == _SEGMENT_ENTRY_EMPTY;
1da177e4
LT		 775}
776
e4e40e02 777#define pmd_write pmd_write
1ae1c1d0
GS		 778static inline int pmd_write(pmd_t pmd)
779{
152125b7
MS		 780 return (pmd_val(pmd) & _SEGMENT_ENTRY_WRITE) != 0;
781}
782
582b4e55
GS		 783#define pud_write pud_write
784static inline int pud_write(pud_t pud)
785{
786 return (pud_val(pud) & _REGION3_ENTRY_WRITE) != 0;
787}
788
533c67e6 789#define pmd_dirty pmd_dirty
152125b7
MS		 790static inline int pmd_dirty(pmd_t pmd)
791{
2d1fc1eb 792 return (pmd_val(pmd) & _SEGMENT_ENTRY_DIRTY) != 0;
1ae1c1d0
GS		 793}
794
6617da8f 795#define pmd_young pmd_young
1ae1c1d0
GS		 796static inline int pmd_young(pmd_t pmd)
797{
2d1fc1eb 798 return (pmd_val(pmd) & _SEGMENT_ENTRY_YOUNG) != 0;
1ae1c1d0
GS		 799}
800
e5098611 801static inline int pte_present(pte_t pte)
1da177e4 802{
e5098611
MS		 803 /* Bit pattern: (pte & 0x001) == 0x001 */
804 return (pte_val(pte) & _PAGE_PRESENT) != 0;
1da177e4
LT		 805}
806
e5098611 807static inline int pte_none(pte_t pte)
1da177e4 808{
e5098611
MS		 809 /* Bit pattern: pte == 0x400 */
810 return pte_val(pte) == _PAGE_INVALID;
1da177e4
LT		 811}
812
b31288fa
KW		 813static inline int pte_swap(pte_t pte)
814{
a1c843b8
MS		 815 /* Bit pattern: (pte & 0x201) == 0x200 */
816 return (pte_val(pte) & (_PAGE_PROTECT | _PAGE_PRESENT))
817 == _PAGE_PROTECT;
b31288fa
KW		 818}
819
7e675137
NP		 820static inline int pte_special(pte_t pte)
821{
a08cb629 822 return (pte_val(pte) & _PAGE_SPECIAL);
7e675137
NP		 823}
824
ba8a9229 825#define __HAVE_ARCH_PTE_SAME
b2fa47e6
MS		 826static inline int pte_same(pte_t a, pte_t b)
827{
828 return pte_val(a) == pte_val(b);
829}
1da177e4 830
b54565b8
MS		 831#ifdef CONFIG_NUMA_BALANCING
832static inline int pte_protnone(pte_t pte)
833{
834 return pte_present(pte) && !(pte_val(pte) & _PAGE_READ);
835}
836
837static inline int pmd_protnone(pmd_t pmd)
838{
2f709f7b
PX		 839 /* pmd_leaf(pmd) implies pmd_present(pmd) */
840 return pmd_leaf(pmd) && !(pmd_val(pmd) & _SEGMENT_ENTRY_READ);
b54565b8
MS		 841}
842#endif
843
92cd58bd
DH		 844static inline int pte_swp_exclusive(pte_t pte)
845{
846 return pte_val(pte) & _PAGE_SWP_EXCLUSIVE;
847}
848
849static inline pte_t pte_swp_mkexclusive(pte_t pte)
850{
851 return set_pte_bit(pte, __pgprot(_PAGE_SWP_EXCLUSIVE));
852}
853
854static inline pte_t pte_swp_clear_exclusive(pte_t pte)
855{
856 return clear_pte_bit(pte, __pgprot(_PAGE_SWP_EXCLUSIVE));
857}
858
5614dd92
MS		 859static inline int pte_soft_dirty(pte_t pte)
860{
861 return pte_val(pte) & _PAGE_SOFT_DIRTY;
862}
863#define pte_swp_soft_dirty pte_soft_dirty
864
865static inline pte_t pte_mksoft_dirty(pte_t pte)
866{
4a366f51 867 return set_pte_bit(pte, __pgprot(_PAGE_SOFT_DIRTY));
5614dd92
MS		 868}
869#define pte_swp_mksoft_dirty pte_mksoft_dirty
870
871static inline pte_t pte_clear_soft_dirty(pte_t pte)
872{
4a366f51 873 return clear_pte_bit(pte, __pgprot(_PAGE_SOFT_DIRTY));
5614dd92
MS		 874}
875#define pte_swp_clear_soft_dirty pte_clear_soft_dirty
876
877static inline int pmd_soft_dirty(pmd_t pmd)
878{
879 return pmd_val(pmd) & _SEGMENT_ENTRY_SOFT_DIRTY;
880}
881
882static inline pmd_t pmd_mksoft_dirty(pmd_t pmd)
883{
4a366f51 884 return set_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_SOFT_DIRTY));
5614dd92
MS		 885}
886
887static inline pmd_t pmd_clear_soft_dirty(pmd_t pmd)
888{
4a366f51 889 return clear_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_SOFT_DIRTY));
5614dd92
MS		 890}
891
1da177e4
LT		 892/*
893 * query functions pte_write/pte_dirty/pte_young only work if
894 * pte_present() is true. Undefined behaviour if not..
895 */
4448aaf0 896static inline int pte_write(pte_t pte)
1da177e4 897{
e5098611 898 return (pte_val(pte) & _PAGE_WRITE) != 0;
1da177e4
LT		 899}
900
4448aaf0 901static inline int pte_dirty(pte_t pte)
1da177e4 902{
e5098611 903 return (pte_val(pte) & _PAGE_DIRTY) != 0;
1da177e4
LT		 904}
905
4448aaf0 906static inline int pte_young(pte_t pte)
1da177e4 907{
0944fe3f 908 return (pte_val(pte) & _PAGE_YOUNG) != 0;
1da177e4
LT		 909}
910
b31288fa
KW		 911#define __HAVE_ARCH_PTE_UNUSED
912static inline int pte_unused(pte_t pte)
913{
914 return pte_val(pte) & _PAGE_UNUSED;
915}
916
d460bb6c
NS		 917/*
918 * Extract the pgprot value from the given pte while at the same time making it
919 * usable for kernel address space mappings where fault driven dirty and
920 * young/old accounting is not supported, i.e _PAGE_PROTECT and _PAGE_INVALID
921 * must not be set.
922 */
923static inline pgprot_t pte_pgprot(pte_t pte)
924{
925 unsigned long pte_flags = pte_val(pte) & _PAGE_CHG_MASK;
926
927 if (pte_write(pte))
928 pte_flags |= pgprot_val(PAGE_KERNEL);
929 else
930 pte_flags |= pgprot_val(PAGE_KERNEL_RO);
931 pte_flags |= pte_val(pte) & mio_wb_bit_mask;
932
933 return __pgprot(pte_flags);
934}
935
1da177e4
LT		 936/*
937 * pgd/pmd/pte modification functions
938 */
939
e2aaae2d
HC		 940static inline void set_pgd(pgd_t *pgdp, pgd_t pgd)
941{
942 WRITE_ONCE(*pgdp, pgd);
943}
944
945static inline void set_p4d(p4d_t *p4dp, p4d_t p4d)
946{
947 WRITE_ONCE(*p4dp, p4d);
948}
949
950static inline void set_pud(pud_t *pudp, pud_t pud)
951{
952 WRITE_ONCE(*pudp, pud);
953}
954
955static inline void set_pmd(pmd_t *pmdp, pmd_t pmd)
956{
957 WRITE_ONCE(*pmdp, pmd);
958}
959
960static inline void set_pte(pte_t *ptep, pte_t pte)
961{
962 WRITE_ONCE(*ptep, pte);
963}
964
b2fa47e6 965static inline void pgd_clear(pgd_t *pgd)
5a216a20 966{
1aea9b3f 967 if ((pgd_val(*pgd) & _REGION_ENTRY_TYPE_MASK) == _REGION_ENTRY_TYPE_R1)
b8e3b379 968 set_pgd(pgd, __pgd(_REGION1_ENTRY_EMPTY));
1aea9b3f
MS		 969}
970
971static inline void p4d_clear(p4d_t *p4d)
972{
973 if ((p4d_val(*p4d) & _REGION_ENTRY_TYPE_MASK) == _REGION_ENTRY_TYPE_R2)
b8e3b379 974 set_p4d(p4d, __p4d(_REGION2_ENTRY_EMPTY));
5a216a20
MS		 975}
976
b2fa47e6 977static inline void pud_clear(pud_t *pud)
1da177e4 978{
6252d702 979 if ((pud_val(*pud) & _REGION_ENTRY_TYPE_MASK) == _REGION_ENTRY_TYPE_R3)
b8e3b379 980 set_pud(pud, __pud(_REGION3_ENTRY_EMPTY));
1da177e4
LT		 981}
982
b2fa47e6 983static inline void pmd_clear(pmd_t *pmdp)
1da177e4 984{
b8e3b379 985 set_pmd(pmdp, __pmd(_SEGMENT_ENTRY_EMPTY));
1da177e4
LT		 986}
987
4448aaf0 988static inline void pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
1da177e4 989{
b8e3b379 990 set_pte(ptep, __pte(_PAGE_INVALID));
1da177e4
LT		 991}
992
993/*
994 * The following pte modification functions only work if
995 * pte_present() is true. Undefined behaviour if not..
996 */
4448aaf0 997static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
1da177e4 998{
4a366f51
HC		 999 pte = clear_pte_bit(pte, __pgprot(~_PAGE_CHG_MASK));
1000 pte = set_pte_bit(pte, newprot);
0944fe3f 1001 /*
57d7f939
MS		 1002 * newprot for PAGE_NONE, PAGE_RO, PAGE_RX, PAGE_RW and PAGE_RWX
1003 * has the invalid bit set, clear it again for readable, young pages
0944fe3f
MS		 1004 */
1005 if ((pte_val(pte) & _PAGE_YOUNG) && (pte_val(pte) & _PAGE_READ))
4a366f51 1006 pte = clear_pte_bit(pte, __pgprot(_PAGE_INVALID));
0944fe3f 1007 /*
57d7f939
MS		 1008 * newprot for PAGE_RO, PAGE_RX, PAGE_RW and PAGE_RWX has the page
1009 * protection bit set, clear it again for writable, dirty pages
0944fe3f 1010 */
e5098611 1011 if ((pte_val(pte) & _PAGE_DIRTY) && (pte_val(pte) & _PAGE_WRITE))
4a366f51 1012 pte = clear_pte_bit(pte, __pgprot(_PAGE_PROTECT));
1da177e4
LT		 1013 return pte;
1014}
1015
4448aaf0 1016static inline pte_t pte_wrprotect(pte_t pte)
1da177e4 1017{
4a366f51
HC		 1018 pte = clear_pte_bit(pte, __pgprot(_PAGE_WRITE));
1019 return set_pte_bit(pte, __pgprot(_PAGE_PROTECT));
1da177e4
LT		 1020}
1021
2f0584f3 1022static inline pte_t pte_mkwrite_novma(pte_t pte)
1da177e4 1023{
4a366f51 1024 pte = set_pte_bit(pte, __pgprot(_PAGE_WRITE));
e5098611 1025 if (pte_val(pte) & _PAGE_DIRTY)
4a366f51 1026 pte = clear_pte_bit(pte, __pgprot(_PAGE_PROTECT));
1da177e4
LT		 1027 return pte;
1028}
1029
4448aaf0 1030static inline pte_t pte_mkclean(pte_t pte)
1da177e4 1031{
4a366f51
HC		 1032 pte = clear_pte_bit(pte, __pgprot(_PAGE_DIRTY));
1033 return set_pte_bit(pte, __pgprot(_PAGE_PROTECT));
1da177e4
LT		 1034}
1035
4448aaf0 1036static inline pte_t pte_mkdirty(pte_t pte)
1da177e4 1037{
4a366f51 1038 pte = set_pte_bit(pte, __pgprot(_PAGE_DIRTY | _PAGE_SOFT_DIRTY));
e5098611 1039 if (pte_val(pte) & _PAGE_WRITE)
4a366f51 1040 pte = clear_pte_bit(pte, __pgprot(_PAGE_PROTECT));
1da177e4
LT		 1041 return pte;
1042}
1043
4448aaf0 1044static inline pte_t pte_mkold(pte_t pte)
1da177e4 1045{
4a366f51
HC		 1046 pte = clear_pte_bit(pte, __pgprot(_PAGE_YOUNG));
1047 return set_pte_bit(pte, __pgprot(_PAGE_INVALID));
1da177e4
LT		 1048}
1049
4448aaf0 1050static inline pte_t pte_mkyoung(pte_t pte)
1da177e4 1051{
4a366f51 1052 pte = set_pte_bit(pte, __pgprot(_PAGE_YOUNG));
0944fe3f 1053 if (pte_val(pte) & _PAGE_READ)
4a366f51 1054 pte = clear_pte_bit(pte, __pgprot(_PAGE_INVALID));
1da177e4
LT		 1055 return pte;
1056}
1057
7e675137
NP		 1058static inline pte_t pte_mkspecial(pte_t pte)
1059{
4a366f51 1060 return set_pte_bit(pte, __pgprot(_PAGE_SPECIAL));
7e675137
NP		 1061}
1062
84afdcee
HC		 1063#ifdef CONFIG_HUGETLB_PAGE
1064static inline pte_t pte_mkhuge(pte_t pte)
1065{
4a366f51 1066 return set_pte_bit(pte, __pgprot(_PAGE_LARGE));
84afdcee
HC		 1067}
1068#endif
1069
34eeaf37
MS		 1070#define IPTE_GLOBAL 0
1071#define IPTE_LOCAL 1
53e857f3 1072
118bd31b 1073#define IPTE_NODAT 0x400
28c807e5 1074#define IPTE_GUEST_ASCE 0x800
118bd31b 1075
0807b856
GS		 1076static __always_inline void __ptep_rdp(unsigned long addr, pte_t *ptep,
1077 unsigned long opt, unsigned long asce,
1078 int local)
1079{
1080 unsigned long pto;
1081
1082 pto = __pa(ptep) & ~(PTRS_PER_PTE * sizeof(pte_t) - 1);
1083 asm volatile(".insn rrf,0xb98b0000,%[r1],%[r2],%[asce],%[m4]"
1084 : "+m" (*ptep)
1085 : [r1] "a" (pto), [r2] "a" ((addr & PAGE_MASK) | opt),
1086 [asce] "a" (asce), [m4] "i" (local));
1087}
1088
6818b542
HC		 1089static __always_inline void __ptep_ipte(unsigned long address, pte_t *ptep,
1090 unsigned long opt, unsigned long asce,
1091 int local)
1b948d6c 1092{
273cd173 1093 unsigned long pto = __pa(ptep);
1b948d6c 1094
118bd31b
MS		 1095 if (__builtin_constant_p(opt) && opt == 0) {
1096 /* Invalidation + TLB flush for the pte */
1097 asm volatile(
731efc96 1098 " ipte %[r1],%[r2],0,%[m4]"
118bd31b
MS		 1099 : "+m" (*ptep) : [r1] "a" (pto), [r2] "a" (address),
1100 [m4] "i" (local));
1101 return;
1102 }
1103
1104 /* Invalidate ptes with options + TLB flush of the ptes */
28c807e5 1105 opt = opt | (asce & _ASCE_ORIGIN);
1b948d6c 1106 asm volatile(
731efc96 1107 " ipte %[r1],%[r2],%[r3],%[m4]"
118bd31b
MS		 1108 : [r2] "+a" (address), [r3] "+a" (opt)
1109 : [r1] "a" (pto), [m4] "i" (local) : "memory");
1b948d6c
MS		 1110}
1111
6818b542
HC		 1112static __always_inline void __ptep_ipte_range(unsigned long address, int nr,
1113 pte_t *ptep, int local)
cfb0b241 1114{
273cd173 1115 unsigned long pto = __pa(ptep);
cfb0b241 1116
34eeaf37 1117 /* Invalidate a range of ptes + TLB flush of the ptes */
cfb0b241
HC		 1118 do {
1119 asm volatile(
731efc96 1120 " ipte %[r1],%[r2],%[r3],%[m4]"
34eeaf37
MS		 1121 : [r2] "+a" (address), [r3] "+a" (nr)
1122 : [r1] "a" (pto), [m4] "i" (local) : "memory");
cfb0b241
HC		 1123 } while (nr != 255);
1124}
1125
0a61b222 1126/*
ebde765c
MS		 1127 * This is hard to understand. ptep_get_and_clear and ptep_clear_flush
1128 * both clear the TLB for the unmapped pte. The reason is that
1129 * ptep_get_and_clear is used in common code (e.g. change_pte_range)
1130 * to modify an active pte. The sequence is
1131 * 1) ptep_get_and_clear
1132 * 2) set_pte_at
1133 * 3) flush_tlb_range
1134 * On s390 the tlb needs to get flushed with the modification of the pte
1135 * if the pte is active. The only way how this can be implemented is to
1136 * have ptep_get_and_clear do the tlb flush. In exchange flush_tlb_range
1137 * is a nop.
0a61b222 1138 */
ebde765c
MS		 1139pte_t ptep_xchg_direct(struct mm_struct *, unsigned long, pte_t *, pte_t);
1140pte_t ptep_xchg_lazy(struct mm_struct *, unsigned long, pte_t *, pte_t);
0a61b222 1141
0944fe3f
MS		 1142#define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
1143static inline int ptep_test_and_clear_young(struct vm_area_struct *vma,
1144 unsigned long addr, pte_t *ptep)
1145{
ebde765c 1146 pte_t pte = *ptep;
0944fe3f 1147
ebde765c
MS		 1148 pte = ptep_xchg_direct(vma->vm_mm, addr, ptep, pte_mkold(pte));
1149 return pte_young(pte);
0944fe3f
MS		 1150}
1151
1152#define __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH
1153static inline int ptep_clear_flush_young(struct vm_area_struct *vma,
1154 unsigned long address, pte_t *ptep)
1155{
1156 return ptep_test_and_clear_young(vma, address, ptep);
1157}
1158
ba8a9229 1159#define __HAVE_ARCH_PTEP_GET_AND_CLEAR
b2fa47e6 1160static inline pte_t ptep_get_and_clear(struct mm_struct *mm,
ebde765c 1161 unsigned long addr, pte_t *ptep)
b2fa47e6 1162{
214d9bbc
CI		 1163 pte_t res;
1164
1165 res = ptep_xchg_lazy(mm, addr, ptep, __pte(_PAGE_INVALID));
380d97bd 1166 /* At this point the reference through the mapping is still present */
214d9bbc 1167 if (mm_is_protected(mm) && pte_present(res))
380d97bd 1168 uv_convert_owned_from_secure(pte_val(res) & PAGE_MASK);
214d9bbc 1169 return res;
b2fa47e6
MS		 1170}
1171
1172#define __HAVE_ARCH_PTEP_MODIFY_PROT_TRANSACTION
0cbe3e26 1173pte_t ptep_modify_prot_start(struct vm_area_struct *, unsigned long, pte_t *);
04a86453
AK		 1174void ptep_modify_prot_commit(struct vm_area_struct *, unsigned long,
1175 pte_t *, pte_t, pte_t);
ba8a9229
MS		 1176
1177#define __HAVE_ARCH_PTEP_CLEAR_FLUSH
f0e47c22 1178static inline pte_t ptep_clear_flush(struct vm_area_struct *vma,
ebde765c 1179 unsigned long addr, pte_t *ptep)
f0e47c22 1180{
214d9bbc
CI		 1181 pte_t res;
1182
1183 res = ptep_xchg_direct(vma->vm_mm, addr, ptep, __pte(_PAGE_INVALID));
380d97bd 1184 /* At this point the reference through the mapping is still present */
214d9bbc 1185 if (mm_is_protected(vma->vm_mm) && pte_present(res))
380d97bd 1186 uv_convert_owned_from_secure(pte_val(res) & PAGE_MASK);
214d9bbc 1187 return res;
1da177e4
LT		 1188}
1189
ba8a9229
MS		 1190/*
1191 * The batched pte unmap code uses ptep_get_and_clear_full to clear the
1192 * ptes. Here an optimization is possible. tlb_gather_mmu flushes all
1193 * tlbs of an mm if it can guarantee that the ptes of the mm_struct
1194 * cannot be accessed while the batched unmap is running. In this case
1195 * full==1 and a simple pte_clear is enough. See tlb.h.
1196 */
1197#define __HAVE_ARCH_PTEP_GET_AND_CLEAR_FULL
1198static inline pte_t ptep_get_and_clear_full(struct mm_struct *mm,
ebde765c 1199 unsigned long addr,
ba8a9229 1200 pte_t *ptep, int full)
1da177e4 1201{
214d9bbc
CI		 1202 pte_t res;
1203
ebde765c 1204 if (full) {
214d9bbc 1205 res = *ptep;
b8e3b379 1206 set_pte(ptep, __pte(_PAGE_INVALID));
214d9bbc
CI		 1207 } else {
1208 res = ptep_xchg_lazy(mm, addr, ptep, __pte(_PAGE_INVALID));
b2fa47e6 1209 }
9bf811da
CI		 1210 /* Nothing to do */
1211 if (!mm_is_protected(mm) || !pte_present(res))
1212 return res;
1213 /*
1214 * At this point the reference through the mapping is still present.
1215 * The notifier should have destroyed all protected vCPUs at this
1216 * point, so the destroy should be successful.
1217 */
1218 if (full && !uv_destroy_owned_page(pte_val(res) & PAGE_MASK))
1219 return res;
1220 /*
1221 * If something went wrong and the page could not be destroyed, or
1222 * if this is not a mm teardown, the slower export is used as
1223 * fallback instead.
1224 */
1225 uv_convert_owned_from_secure(pte_val(res) & PAGE_MASK);
214d9bbc 1226 return res;
1da177e4
LT		 1227}
1228
ba8a9229 1229#define __HAVE_ARCH_PTEP_SET_WRPROTECT
ebde765c
MS		 1230static inline void ptep_set_wrprotect(struct mm_struct *mm,
1231 unsigned long addr, pte_t *ptep)
b2fa47e6 1232{
b2fa47e6
MS		 1233 pte_t pte = *ptep;
1234
ebde765c
MS		 1235 if (pte_write(pte))
1236 ptep_xchg_lazy(mm, addr, ptep, pte_wrprotect(pte));
b2fa47e6 1237}
ba8a9229 1238
0807b856
GS		 1239/*
1240 * Check if PTEs only differ in _PAGE_PROTECT HW bit, but also allow SW PTE
1241 * bits in the comparison. Those might change e.g. because of dirty and young
1242 * tracking.
1243 */
1244static inline int pte_allow_rdp(pte_t old, pte_t new)
1245{
1246 /*
1247 * Only allow changes from RO to RW
1248 */
1249 if (!(pte_val(old) & _PAGE_PROTECT) || pte_val(new) & _PAGE_PROTECT)
1250 return 0;
1251
1252 return (pte_val(old) & _PAGE_RDP_MASK) == (pte_val(new) & _PAGE_RDP_MASK);
1253}
1254
1255static inline void flush_tlb_fix_spurious_fault(struct vm_area_struct *vma,
99c29133
GS		 1256 unsigned long address,
1257 pte_t *ptep)
0807b856
GS		 1258{
1259 /*
1260 * RDP might not have propagated the PTE protection reset to all CPUs,
1261 * so there could be spurious TLB protection faults.
1262 * NOTE: This will also be called when a racing pagetable update on
1263 * another thread already installed the correct PTE. Both cases cannot
1264 * really be distinguished.
99c29133
GS		 1265 * Therefore, only do the local TLB flush when RDP can be used, and the
1266 * PTE does not have _PAGE_PROTECT set, to avoid unnecessary overhead.
1267 * A local RDP can be used to do the flush.
0807b856 1268 */
99c29133
GS		 1269 if (MACHINE_HAS_RDP && !(pte_val(*ptep) & _PAGE_PROTECT))
1270 __ptep_rdp(address, ptep, 0, 0, 1);
0807b856
GS		 1271}
1272#define flush_tlb_fix_spurious_fault flush_tlb_fix_spurious_fault
1273
1274void ptep_reset_dat_prot(struct mm_struct *mm, unsigned long addr, pte_t *ptep,
1275 pte_t new);
1276
ba8a9229 1277#define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS
b2fa47e6 1278static inline int ptep_set_access_flags(struct vm_area_struct *vma,
ebde765c 1279 unsigned long addr, pte_t *ptep,
b2fa47e6
MS		 1280 pte_t entry, int dirty)
1281{
ebde765c 1282 if (pte_same(*ptep, entry))
b2fa47e6 1283 return 0;
0807b856
GS		 1284 if (MACHINE_HAS_RDP && !mm_has_pgste(vma->vm_mm) && pte_allow_rdp(*ptep, entry))
1285 ptep_reset_dat_prot(vma->vm_mm, addr, ptep, entry);
1286 else
1287 ptep_xchg_direct(vma->vm_mm, addr, ptep, entry);
ebde765c
MS		 1288 return 1;
1289}
b2fa47e6 1290
1e133ab2
MS		 1291/*
1292 * Additional functions to handle KVM guest page tables
1293 */
1294void ptep_set_pte_at(struct mm_struct *mm, unsigned long addr,
1295 pte_t *ptep, pte_t entry);
1296void ptep_set_notify(struct mm_struct *mm, unsigned long addr, pte_t *ptep);
4be130a0
MS		 1297void ptep_notify(struct mm_struct *mm, unsigned long addr,
1298 pte_t *ptep, unsigned long bits);
b2d73b2a 1299int ptep_force_prot(struct mm_struct *mm, unsigned long gaddr,
4be130a0 1300 pte_t *ptep, int prot, unsigned long bit);
1e133ab2
MS		 1301void ptep_zap_unused(struct mm_struct *mm, unsigned long addr,
1302 pte_t *ptep , int reset);
1303void ptep_zap_key(struct mm_struct *mm, unsigned long addr, pte_t *ptep);
4be130a0 1304int ptep_shadow_pte(struct mm_struct *mm, unsigned long saddr,
a9d23e71 1305 pte_t *sptep, pte_t *tptep, pte_t pte);
4be130a0 1306void ptep_unshadow_pte(struct mm_struct *mm, unsigned long saddr, pte_t *ptep);
1e133ab2 1307
0959e168
JF		 1308bool ptep_test_and_clear_uc(struct mm_struct *mm, unsigned long address,
1309 pte_t *ptep);
1e133ab2
MS		 1310int set_guest_storage_key(struct mm_struct *mm, unsigned long addr,
1311 unsigned char key, bool nq);
1824c723
DH		 1312int cond_set_guest_storage_key(struct mm_struct *mm, unsigned long addr,
1313 unsigned char key, unsigned char *oldkey,
1314 bool nq, bool mr, bool mc);
a7e19ab5 1315int reset_guest_reference_bit(struct mm_struct *mm, unsigned long addr);
154c8c19
DH		 1316int get_guest_storage_key(struct mm_struct *mm, unsigned long addr,
1317 unsigned char *key);
b2fa47e6 1318
2d42f947
CI		 1319int set_pgste_bits(struct mm_struct *mm, unsigned long addr,
1320 unsigned long bits, unsigned long value);
1321int get_pgste(struct mm_struct *mm, unsigned long hva, unsigned long *pgstep);
1322int pgste_perform_essa(struct mm_struct *mm, unsigned long hva, int orc,
1323 unsigned long *oldpte, unsigned long *oldpgste);
6a376277
JF		 1324void gmap_pmdp_csp(struct mm_struct *mm, unsigned long vmaddr);
1325void gmap_pmdp_invalidate(struct mm_struct *mm, unsigned long vmaddr);
1326void gmap_pmdp_idte_local(struct mm_struct *mm, unsigned long vmaddr);
1327void gmap_pmdp_idte_global(struct mm_struct *mm, unsigned long vmaddr);
2d42f947 1328
b02002cc
NS		 1329#define pgprot_writecombine pgprot_writecombine
1330pgprot_t pgprot_writecombine(pgprot_t prot);
1331
1332#define pgprot_writethrough pgprot_writethrough
1333pgprot_t pgprot_writethrough(pgprot_t prot);
1334
4555ac8b
DH		 1335#define PFN_PTE_SHIFT PAGE_SHIFT
1336
ebde765c 1337/*
843f9310
MWO		 1338 * Set multiple PTEs to consecutive pages with a single call. All PTEs
1339 * are within the same folio, PMD and VMA.
ebde765c 1340 */
843f9310
MWO		 1341static inline void set_ptes(struct mm_struct *mm, unsigned long addr,
1342 pte_t *ptep, pte_t entry, unsigned int nr)
ebde765c 1343{
a8f60d1f 1344 if (pte_present(entry))
4a366f51 1345 entry = clear_pte_bit(entry, __pgprot(_PAGE_UNUSED));
843f9310
MWO		 1346 if (mm_has_pgste(mm)) {
1347 for (;;) {
1348 ptep_set_pte_at(mm, addr, ptep, entry);
1349 if (--nr == 0)
1350 break;
1351 ptep++;
1352 entry = __pte(pte_val(entry) + PAGE_SIZE);
1353 addr += PAGE_SIZE;
1354 }
1355 } else {
1356 for (;;) {
1357 set_pte(ptep, entry);
1358 if (--nr == 0)
1359 break;
1360 ptep++;
1361 entry = __pte(pte_val(entry) + PAGE_SIZE);
1362 }
1363 }
b2fa47e6 1364}
843f9310 1365#define set_ptes set_ptes
1da177e4 1366
1da177e4
LT		 1367/*
1368 * Conversion functions: convert a page and protection to a page entry,
1369 * and a page entry and page directory to the page they refer to.
1370 */
1371static inline pte_t mk_pte_phys(unsigned long physpage, pgprot_t pgprot)
1372{
1373 pte_t __pte;
b02002cc 1374
4a366f51 1375 __pte = __pte(physpage | pgprot_val(pgprot));
ab874f22 1376 if (!MACHINE_HAS_NX)
4a366f51 1377 __pte = clear_pte_bit(__pte, __pgprot(_PAGE_NOEXEC));
0944fe3f 1378 return pte_mkyoung(__pte);
1da177e4
LT		 1379}
1380
2dcea57a
HC		 1381static inline pte_t mk_pte(struct page *page, pgprot_t pgprot)
1382{
0b2b6e1d 1383 unsigned long physpage = page_to_phys(page);
abf09bed 1384 pte_t __pte = mk_pte_phys(physpage, pgprot);
1da177e4 1385
e5098611
MS		 1386 if (pte_write(__pte) && PageDirty(page))
1387 __pte = pte_mkdirty(__pte);
abf09bed 1388 return __pte;
2dcea57a
HC		 1389}
1390
190a1d72 1391#define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD-1))
1aea9b3f 1392#define p4d_index(address) (((address) >> P4D_SHIFT) & (PTRS_PER_P4D-1))
190a1d72
MS		 1393#define pud_index(address) (((address) >> PUD_SHIFT) & (PTRS_PER_PUD-1))
1394#define pmd_index(address) (((address) >> PMD_SHIFT) & (PTRS_PER_PMD-1))
1da177e4 1395
86c827b3
AG		 1396#define p4d_deref(pud) ((unsigned long)__va(p4d_val(pud) & _REGION_ENTRY_ORIGIN))
1397#define pgd_deref(pgd) ((unsigned long)__va(pgd_val(pgd) & _REGION_ENTRY_ORIGIN))
1da177e4 1398
b0e98aa9
GS		 1399static inline unsigned long pmd_deref(pmd_t pmd)
1400{
1401 unsigned long origin_mask;
1402
1403 origin_mask = _SEGMENT_ENTRY_ORIGIN;
2f709f7b 1404 if (pmd_leaf(pmd))
b0e98aa9 1405 origin_mask = _SEGMENT_ENTRY_ORIGIN_LARGE;
86c827b3 1406 return (unsigned long)__va(pmd_val(pmd) & origin_mask);
b0e98aa9
GS		 1407}
1408
1409static inline unsigned long pmd_pfn(pmd_t pmd)
1410{
86c827b3 1411 return __pa(pmd_deref(pmd)) >> PAGE_SHIFT;
b0e98aa9
GS		 1412}
1413
1414static inline unsigned long pud_deref(pud_t pud)
1415{
1416 unsigned long origin_mask;
1417
1418 origin_mask = _REGION_ENTRY_ORIGIN;
0a845e0f 1419 if (pud_leaf(pud))
b0e98aa9 1420 origin_mask = _REGION3_ENTRY_ORIGIN_LARGE;
86c827b3 1421 return (unsigned long)__va(pud_val(pud) & origin_mask);
b0e98aa9
GS		 1422}
1423
35a76f5c 1424#define pud_pfn pud_pfn
b0e98aa9
GS		 1425static inline unsigned long pud_pfn(pud_t pud)
1426{
86c827b3 1427 return __pa(pud_deref(pud)) >> PAGE_SHIFT;
b0e98aa9
GS		 1428}
1429
d1874a0c
MS		 1430/*
1431 * The pgd_offset function *always* adds the index for the top-level
1432 * region/segment table. This is done to get a sequence like the
1433 * following to work:
1434 * pgdp = pgd_offset(current->mm, addr);
1435 * pgd = READ_ONCE(*pgdp);
1436 * p4dp = p4d_offset(&pgd, addr);
1437 * ...
1438 * The subsequent p4d_offset, pud_offset and pmd_offset functions
1439 * only add an index if they dereferenced the pointer.
1440 */
1441static inline pgd_t *pgd_offset_raw(pgd_t *pgd, unsigned long address)
5a216a20 1442{
d1874a0c
MS		 1443 unsigned long rste;
1444 unsigned int shift;
1aea9b3f 1445
d1874a0c
MS		 1446 /* Get the first entry of the top level table */
1447 rste = pgd_val(*pgd);
1448 /* Pick up the shift from the table type of the first entry */
1449 shift = ((rste & _REGION_ENTRY_TYPE_MASK) >> 2) * 11 + 20;
1450 return pgd + ((address >> shift) & (PTRS_PER_PGD - 1));
1aea9b3f
MS		 1451}
1452
d1874a0c 1453#define pgd_offset(mm, address) pgd_offset_raw(READ_ONCE((mm)->pgd), address)
d1874a0c 1454
d3f7b1bb 1455static inline p4d_t *p4d_offset_lockless(pgd_t *pgdp, pgd_t pgd, unsigned long address)
1aea9b3f 1456{
d3f7b1bb
VG		 1457 if ((pgd_val(pgd) & _REGION_ENTRY_TYPE_MASK) >= _REGION_ENTRY_TYPE_R1)
1458 return (p4d_t *) pgd_deref(pgd) + p4d_index(address);
1459 return (p4d_t *) pgdp;
d1874a0c 1460}
d3f7b1bb 1461#define p4d_offset_lockless p4d_offset_lockless
1aea9b3f 1462
d3f7b1bb 1463static inline p4d_t *p4d_offset(pgd_t *pgdp, unsigned long address)
d1874a0c 1464{
d3f7b1bb
VG		 1465 return p4d_offset_lockless(pgdp, *pgdp, address);
1466}
1467
1468static inline pud_t *pud_offset_lockless(p4d_t *p4dp, p4d_t p4d, unsigned long address)
1469{
1470 if ((p4d_val(p4d) & _REGION_ENTRY_TYPE_MASK) >= _REGION_ENTRY_TYPE_R2)
1471 return (pud_t *) p4d_deref(p4d) + pud_index(address);
1472 return (pud_t *) p4dp;
1473}
1474#define pud_offset_lockless pud_offset_lockless
1475
1476static inline pud_t *pud_offset(p4d_t *p4dp, unsigned long address)
1477{
1478 return pud_offset_lockless(p4dp, *p4dp, address);
5a216a20 1479}
974b9b2c 1480#define pud_offset pud_offset
1da177e4 1481
d3f7b1bb
VG		 1482static inline pmd_t *pmd_offset_lockless(pud_t *pudp, pud_t pud, unsigned long address)
1483{
1484 if ((pud_val(pud) & _REGION_ENTRY_TYPE_MASK) >= _REGION_ENTRY_TYPE_R3)
1485 return (pmd_t *) pud_deref(pud) + pmd_index(address);
1486 return (pmd_t *) pudp;
1487}
1488#define pmd_offset_lockless pmd_offset_lockless
1489
1490static inline pmd_t *pmd_offset(pud_t *pudp, unsigned long address)
1da177e4 1491{
d3f7b1bb 1492 return pmd_offset_lockless(pudp, *pudp, address);
d1874a0c 1493}
974b9b2c 1494#define pmd_offset pmd_offset
1aea9b3f 1495
974b9b2c 1496static inline unsigned long pmd_page_vaddr(pmd_t pmd)
d1874a0c 1497{
974b9b2c 1498 return (unsigned long) pmd_deref(pmd);
1da177e4
LT		 1499}
1500
26f4c328 1501static inline bool gup_fast_permitted(unsigned long start, unsigned long end)
1a42010c 1502{
1a42010c
MS		 1503 return end <= current->mm->context.asce_limit;
1504}
1505#define gup_fast_permitted gup_fast_permitted
1506
0f3bf303 1507#define pfn_pte(pfn, pgprot) mk_pte_phys(((pfn) << PAGE_SHIFT), (pgprot))
190a1d72
MS		 1508#define pte_pfn(x) (pte_val(x) >> PAGE_SHIFT)
1509#define pte_page(x) pfn_to_page(pte_pfn(x))
1da177e4 1510
152125b7 1511#define pmd_page(pmd) pfn_to_page(pmd_pfn(pmd))
d08de8e2 1512#define pud_page(pud) pfn_to_page(pud_pfn(pud))
d0e2eb0a
VG		 1513#define p4d_page(p4d) pfn_to_page(p4d_pfn(p4d))
1514#define pgd_page(pgd) pfn_to_page(pgd_pfn(pgd))
1da177e4 1515
152125b7 1516static inline pmd_t pmd_wrprotect(pmd_t pmd)
0944fe3f 1517{
4a366f51
HC		 1518 pmd = clear_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_WRITE));
1519 return set_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_PROTECT));
152125b7
MS		 1520}
1521
2f0584f3 1522static inline pmd_t pmd_mkwrite_novma(pmd_t pmd)
152125b7 1523{
4a366f51 1524 pmd = set_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_WRITE));
2d1fc1eb 1525 if (pmd_val(pmd) & _SEGMENT_ENTRY_DIRTY)
4a366f51 1526 pmd = clear_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_PROTECT));
152125b7
MS		 1527 return pmd;
1528}
1529
1530static inline pmd_t pmd_mkclean(pmd_t pmd)
1531{
4a366f51
HC		 1532 pmd = clear_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_DIRTY));
1533 return set_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_PROTECT));
152125b7
MS		 1534}
1535
1536static inline pmd_t pmd_mkdirty(pmd_t pmd)
1537{
4a366f51 1538 pmd = set_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_DIRTY | _SEGMENT_ENTRY_SOFT_DIRTY));
2d1fc1eb 1539 if (pmd_val(pmd) & _SEGMENT_ENTRY_WRITE)
4a366f51 1540 pmd = clear_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_PROTECT));
152125b7
MS		 1541 return pmd;
1542}
1543
9e20b4da
HC		 1544static inline pud_t pud_wrprotect(pud_t pud)
1545{
4a366f51
HC		 1546 pud = clear_pud_bit(pud, __pgprot(_REGION3_ENTRY_WRITE));
1547 return set_pud_bit(pud, __pgprot(_REGION_ENTRY_PROTECT));
9e20b4da
HC		 1548}
1549
1550static inline pud_t pud_mkwrite(pud_t pud)
1551{
4a366f51 1552 pud = set_pud_bit(pud, __pgprot(_REGION3_ENTRY_WRITE));
2d1fc1eb 1553 if (pud_val(pud) & _REGION3_ENTRY_DIRTY)
4a366f51 1554 pud = clear_pud_bit(pud, __pgprot(_REGION_ENTRY_PROTECT));
9e20b4da
HC		 1555 return pud;
1556}
1557
1558static inline pud_t pud_mkclean(pud_t pud)
1559{
4a366f51
HC		 1560 pud = clear_pud_bit(pud, __pgprot(_REGION3_ENTRY_DIRTY));
1561 return set_pud_bit(pud, __pgprot(_REGION_ENTRY_PROTECT));
9e20b4da
HC		 1562}
1563
1564static inline pud_t pud_mkdirty(pud_t pud)
1565{
4a366f51 1566 pud = set_pud_bit(pud, __pgprot(_REGION3_ENTRY_DIRTY | _REGION3_ENTRY_SOFT_DIRTY));
2d1fc1eb 1567 if (pud_val(pud) & _REGION3_ENTRY_WRITE)
4a366f51 1568 pud = clear_pud_bit(pud, __pgprot(_REGION_ENTRY_PROTECT));
9e20b4da
HC		 1569 return pud;
1570}
1571
1572#if defined(CONFIG_TRANSPARENT_HUGEPAGE) || defined(CONFIG_HUGETLB_PAGE)
1573static inline unsigned long massage_pgprot_pmd(pgprot_t pgprot)
1574{
1575 /*
57d7f939
MS		 1576 * pgprot is PAGE_NONE, PAGE_RO, PAGE_RX, PAGE_RW or PAGE_RWX
1577 * (see __Pxxx / __Sxxx). Convert to segment table entry format.
9e20b4da
HC		 1578 */
1579 if (pgprot_val(pgprot) == pgprot_val(PAGE_NONE))
1580 return pgprot_val(SEGMENT_NONE);
57d7f939
MS		 1581 if (pgprot_val(pgprot) == pgprot_val(PAGE_RO))
1582 return pgprot_val(SEGMENT_RO);
1583 if (pgprot_val(pgprot) == pgprot_val(PAGE_RX))
1584 return pgprot_val(SEGMENT_RX);
1585 if (pgprot_val(pgprot) == pgprot_val(PAGE_RW))
1586 return pgprot_val(SEGMENT_RW);
1587 return pgprot_val(SEGMENT_RWX);
9e20b4da
HC		 1588}
1589
152125b7
MS		 1590static inline pmd_t pmd_mkyoung(pmd_t pmd)
1591{
4a366f51 1592 pmd = set_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_YOUNG));
2d1fc1eb 1593 if (pmd_val(pmd) & _SEGMENT_ENTRY_READ)
4a366f51 1594 pmd = clear_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_INVALID));
0944fe3f
MS		 1595 return pmd;
1596}
1597
1598static inline pmd_t pmd_mkold(pmd_t pmd)
1599{
4a366f51
HC		 1600 pmd = clear_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_YOUNG));
1601 return set_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_INVALID));
0944fe3f
MS		 1602}
1603
1ae1c1d0
GS		 1604static inline pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot)
1605{
4a366f51
HC		 1606 unsigned long mask;
1607
1608 mask = _SEGMENT_ENTRY_ORIGIN_LARGE;
1609 mask |= _SEGMENT_ENTRY_DIRTY;
1610 mask |= _SEGMENT_ENTRY_YOUNG;
1611 mask |= _SEGMENT_ENTRY_LARGE;
1612 mask |= _SEGMENT_ENTRY_SOFT_DIRTY;
1613 pmd = __pmd(pmd_val(pmd) & mask);
1614 pmd = set_pmd_bit(pmd, __pgprot(massage_pgprot_pmd(newprot)));
2d1fc1eb 1615 if (!(pmd_val(pmd) & _SEGMENT_ENTRY_DIRTY))
4a366f51 1616 pmd = set_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_PROTECT));
2d1fc1eb 1617 if (!(pmd_val(pmd) & _SEGMENT_ENTRY_YOUNG))
4a366f51 1618 pmd = set_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_INVALID));
1ae1c1d0
GS		 1619 return pmd;
1620}
1621
106c992a 1622static inline pmd_t mk_pmd_phys(unsigned long physpage, pgprot_t pgprot)
1ae1c1d0 1623{
4a366f51 1624 return __pmd(physpage + massage_pgprot_pmd(pgprot));
1ae1c1d0
GS		 1625}
1626
106c992a
GS		 1627#endif /* CONFIG_TRANSPARENT_HUGEPAGE || CONFIG_HUGETLB_PAGE */
1628
1b948d6c
MS		 1629static inline void __pmdp_csp(pmd_t *pmdp)
1630{
4ccccc52
HC		 1631 csp((unsigned int *)pmdp + 1, pmd_val(*pmdp),
1632 pmd_val(*pmdp) | _SEGMENT_ENTRY_INVALID);
1b948d6c
MS		 1633}
1634
47e4d851
MS		 1635#define IDTE_GLOBAL 0
1636#define IDTE_LOCAL 1
d08de8e2 1637
118bd31b
MS		 1638#define IDTE_PTOA 0x0800
1639#define IDTE_NODAT 0x1000
28c807e5 1640#define IDTE_GUEST_ASCE 0x2000
118bd31b 1641
6818b542
HC		 1642static __always_inline void __pmdp_idte(unsigned long addr, pmd_t *pmdp,
1643 unsigned long opt, unsigned long asce,
1644 int local)
1b948d6c
MS		 1645{
1646 unsigned long sto;
1647
273cd173 1648 sto = __pa(pmdp) - pmd_index(addr) * sizeof(pmd_t);
28c807e5
MS		 1649 if (__builtin_constant_p(opt) && opt == 0) {
1650 /* flush without guest asce */
1651 asm volatile(
731efc96 1652 " idte %[r1],0,%[r2],%[m4]"
28c807e5
MS		 1653 : "+m" (*pmdp)
1654 : [r1] "a" (sto), [r2] "a" ((addr & HPAGE_MASK)),
1655 [m4] "i" (local)
1656 : "cc" );
1657 } else {
1658 /* flush with guest asce */
1659 asm volatile(
731efc96 1660 " idte %[r1],%[r3],%[r2],%[m4]"
28c807e5
MS		 1661 : "+m" (*pmdp)
1662 : [r1] "a" (sto), [r2] "a" ((addr & HPAGE_MASK) | opt),
1663 [r3] "a" (asce), [m4] "i" (local)
1664 : "cc" );
1665 }
1b948d6c
MS		 1666}
1667
6818b542
HC		 1668static __always_inline void __pudp_idte(unsigned long addr, pud_t *pudp,
1669 unsigned long opt, unsigned long asce,
1670 int local)
d08de8e2
GS		 1671{
1672 unsigned long r3o;
1673
273cd173 1674 r3o = __pa(pudp) - pud_index(addr) * sizeof(pud_t);
d08de8e2 1675 r3o |= _ASCE_TYPE_REGION3;
28c807e5
MS		 1676 if (__builtin_constant_p(opt) && opt == 0) {
1677 /* flush without guest asce */
1678 asm volatile(
731efc96 1679 " idte %[r1],0,%[r2],%[m4]"
28c807e5
MS		 1680 : "+m" (*pudp)
1681 : [r1] "a" (r3o), [r2] "a" ((addr & PUD_MASK)),
1682 [m4] "i" (local)
1683 : "cc");
1684 } else {
1685 /* flush with guest asce */
1686 asm volatile(
731efc96 1687 " idte %[r1],%[r3],%[r2],%[m4]"
28c807e5
MS		 1688 : "+m" (*pudp)
1689 : [r1] "a" (r3o), [r2] "a" ((addr & PUD_MASK) | opt),
1690 [r3] "a" (asce), [m4] "i" (local)
1691 : "cc" );
1692 }
d08de8e2
GS		 1693}
1694
227be799
MS		 1695pmd_t pmdp_xchg_direct(struct mm_struct *, unsigned long, pmd_t *, pmd_t);
1696pmd_t pmdp_xchg_lazy(struct mm_struct *, unsigned long, pmd_t *, pmd_t);
d08de8e2 1697pud_t pudp_xchg_direct(struct mm_struct *, unsigned long, pud_t *, pud_t);
1b948d6c 1698
227be799
MS		 1699#ifdef CONFIG_TRANSPARENT_HUGEPAGE
1700
1701#define __HAVE_ARCH_PGTABLE_DEPOSIT
1702void pgtable_trans_huge_deposit(struct mm_struct *mm, pmd_t *pmdp,
1703 pgtable_t pgtable);
1704
1705#define __HAVE_ARCH_PGTABLE_WITHDRAW
1706pgtable_t pgtable_trans_huge_withdraw(struct mm_struct *mm, pmd_t *pmdp);
1b948d6c 1707
227be799
MS		 1708#define __HAVE_ARCH_PMDP_SET_ACCESS_FLAGS
1709static inline int pmdp_set_access_flags(struct vm_area_struct *vma,
1710 unsigned long addr, pmd_t *pmdp,
1711 pmd_t entry, int dirty)
3eabaee9 1712{
227be799 1713 VM_BUG_ON(addr & ~HPAGE_MASK);
3eabaee9 1714
227be799
MS		 1715 entry = pmd_mkyoung(entry);
1716 if (dirty)
1717 entry = pmd_mkdirty(entry);
1718 if (pmd_val(*pmdp) == pmd_val(entry))
1719 return 0;
1720 pmdp_xchg_direct(vma->vm_mm, addr, pmdp, entry);
1721 return 1;
3eabaee9
MS		 1722}
1723
227be799
MS		 1724#define __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG
1725static inline int pmdp_test_and_clear_young(struct vm_area_struct *vma,
1726 unsigned long addr, pmd_t *pmdp)
1727{
1728 pmd_t pmd = *pmdp;
106c992a 1729
227be799
MS		 1730 pmd = pmdp_xchg_direct(vma->vm_mm, addr, pmdp, pmd_mkold(pmd));
1731 return pmd_young(pmd);
1732}
106c992a 1733
227be799
MS		 1734#define __HAVE_ARCH_PMDP_CLEAR_YOUNG_FLUSH
1735static inline int pmdp_clear_flush_young(struct vm_area_struct *vma,
1736 unsigned long addr, pmd_t *pmdp)
1737{
1738 VM_BUG_ON(addr & ~HPAGE_MASK);
1739 return pmdp_test_and_clear_young(vma, addr, pmdp);
1740}
106c992a 1741
106c992a
GS		 1742static inline void set_pmd_at(struct mm_struct *mm, unsigned long addr,
1743 pmd_t *pmdp, pmd_t entry)
1744{
57d7f939 1745 if (!MACHINE_HAS_NX)
4a366f51 1746 entry = clear_pmd_bit(entry, __pgprot(_SEGMENT_ENTRY_NOEXEC));
b8e3b379 1747 set_pmd(pmdp, entry);
106c992a
GS		 1748}
1749
1750static inline pmd_t pmd_mkhuge(pmd_t pmd)
1751{
4a366f51
HC		 1752 pmd = set_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_LARGE));
1753 pmd = set_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_YOUNG));
1754 return set_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_PROTECT));
1ae1c1d0
GS		 1755}
1756
8809aa2d
AK		 1757#define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR
1758static inline pmd_t pmdp_huge_get_and_clear(struct mm_struct *mm,
227be799 1759 unsigned long addr, pmd_t *pmdp)
1ae1c1d0 1760{
54397bb0 1761 return pmdp_xchg_direct(mm, addr, pmdp, __pmd(_SEGMENT_ENTRY_EMPTY));
1ae1c1d0
GS		 1762}
1763
8809aa2d 1764#define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR_FULL
93a98695 1765static inline pmd_t pmdp_huge_get_and_clear_full(struct vm_area_struct *vma,
227be799 1766 unsigned long addr,
8809aa2d 1767 pmd_t *pmdp, int full)
fcbe08d6 1768{
227be799
MS		 1769 if (full) {
1770 pmd_t pmd = *pmdp;
b8e3b379 1771 set_pmd(pmdp, __pmd(_SEGMENT_ENTRY_EMPTY));
227be799
MS		 1772 return pmd;
1773 }
93a98695 1774 return pmdp_xchg_lazy(vma->vm_mm, addr, pmdp, __pmd(_SEGMENT_ENTRY_EMPTY));
fcbe08d6
MS		 1775}
1776
8809aa2d
AK		 1777#define __HAVE_ARCH_PMDP_HUGE_CLEAR_FLUSH
1778static inline pmd_t pmdp_huge_clear_flush(struct vm_area_struct *vma,
227be799 1779 unsigned long addr, pmd_t *pmdp)
1ae1c1d0 1780{
227be799 1781 return pmdp_huge_get_and_clear(vma->vm_mm, addr, pmdp);
1ae1c1d0
GS		 1782}
1783
1784#define __HAVE_ARCH_PMDP_INVALIDATE
9c4563f1 1785static inline pmd_t pmdp_invalidate(struct vm_area_struct *vma,
227be799 1786 unsigned long addr, pmd_t *pmdp)
1ae1c1d0 1787{
3a5a8d34 1788 pmd_t pmd;
91c575b3 1789
3a5a8d34
RR		 1790 VM_WARN_ON_ONCE(!pmd_present(*pmdp));
1791 pmd = __pmd(pmd_val(*pmdp) | _SEGMENT_ENTRY_INVALID);
9c4563f1 1792 return pmdp_xchg_direct(vma->vm_mm, addr, pmdp, pmd);
1ae1c1d0
GS		 1793}
1794
be328650
GS		 1795#define __HAVE_ARCH_PMDP_SET_WRPROTECT
1796static inline void pmdp_set_wrprotect(struct mm_struct *mm,
227be799 1797 unsigned long addr, pmd_t *pmdp)
be328650
GS		 1798{
1799 pmd_t pmd = *pmdp;
1800
227be799
MS		 1801 if (pmd_write(pmd))
1802 pmd = pmdp_xchg_lazy(mm, addr, pmdp, pmd_wrprotect(pmd));
be328650
GS		 1803}
1804
f28b6ff8
AK		 1805static inline pmd_t pmdp_collapse_flush(struct vm_area_struct *vma,
1806 unsigned long address,
1807 pmd_t *pmdp)
1808{
8809aa2d 1809 return pmdp_huge_get_and_clear(vma->vm_mm, address, pmdp);
f28b6ff8
AK		 1810}
1811#define pmdp_collapse_flush pmdp_collapse_flush
1812
0f3bf303 1813#define pfn_pmd(pfn, pgprot) mk_pmd_phys(((pfn) << PAGE_SHIFT), (pgprot))
1ae1c1d0
GS		 1814#define mk_pmd(page, pgprot) pfn_pmd(page_to_pfn(page), (pgprot))
1815
1816static inline int pmd_trans_huge(pmd_t pmd)
1817{
1818 return pmd_val(pmd) & _SEGMENT_ENTRY_LARGE;
1819}
1820
fd8cfd30 1821#define has_transparent_hugepage has_transparent_hugepage
1ae1c1d0
GS		 1822static inline int has_transparent_hugepage(void)
1823{
466178fc 1824 return MACHINE_HAS_EDAT1 ? 1 : 0;
1ae1c1d0 1825}
75077afb
GS		 1826#endif /* CONFIG_TRANSPARENT_HUGEPAGE */
1827
1da177e4 1828/*
1da177e4
LT		 1829 * 64 bit swap entry format:
1830 * A page-table entry has some bits we have to treat in a special way.
8043d26c
DH		 1831 * Bits 54 and 63 are used to indicate the page type. Bit 53 marks the pte
1832 * as invalid.
a1c843b8 1833 * A swap pte is indicated by bit pattern (pte & 0x201) == 0x200
92cd58bd 1834 * | offset |E11XX|type |S0|
a1c843b8
MS		 1835 * |0000000000111111111122222222223333333333444444444455|55555|55566|66|
1836 * |0123456789012345678901234567890123456789012345678901|23456|78901|23|
8043d26c
DH		 1837 *
1838 * Bits 0-51 store the offset.
92cd58bd 1839 * Bit 52 (E) is used to remember PG_anon_exclusive.
8043d26c
DH		 1840 * Bits 57-61 store the type.
1841 * Bit 62 (S) is used for softdirty tracking.
92cd58bd 1842 * Bits 55 and 56 (X) are unused.
1da177e4 1843 */
5a79859a 1844
a1c843b8
MS		 1845#define __SWP_OFFSET_MASK ((1UL << 52) - 1)
1846#define __SWP_OFFSET_SHIFT 12
1847#define __SWP_TYPE_MASK ((1UL << 5) - 1)
1848#define __SWP_TYPE_SHIFT 2
5a79859a 1849
4448aaf0 1850static inline pte_t mk_swap_pte(unsigned long type, unsigned long offset)
1da177e4 1851{
4a366f51 1852 unsigned long pteval;
a1c843b8 1853
4a366f51
HC		 1854 pteval = _PAGE_INVALID | _PAGE_PROTECT;
1855 pteval |= (offset & __SWP_OFFSET_MASK) << __SWP_OFFSET_SHIFT;
1856 pteval |= (type & __SWP_TYPE_MASK) << __SWP_TYPE_SHIFT;
1857 return __pte(pteval);
1da177e4
LT		 1858}
1859
a1c843b8
MS		 1860static inline unsigned long __swp_type(swp_entry_t entry)
1861{
1862 return (entry.val >> __SWP_TYPE_SHIFT) & __SWP_TYPE_MASK;
1863}
1864
1865static inline unsigned long __swp_offset(swp_entry_t entry)
1866{
1867 return (entry.val >> __SWP_OFFSET_SHIFT) & __SWP_OFFSET_MASK;
1868}
1869
1870static inline swp_entry_t __swp_entry(unsigned long type, unsigned long offset)
1871{
1872 return (swp_entry_t) { pte_val(mk_swap_pte(type, offset)) };
1873}
1da177e4
LT		 1874
1875#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
1876#define __swp_entry_to_pte(x) ((pte_t) { (x).val })
1877
17f34580 1878extern int vmem_add_mapping(unsigned long start, unsigned long size);
f05f62d0 1879extern void vmem_remove_mapping(unsigned long start, unsigned long size);
4df29d2b
AG		 1880extern int __vmem_map_4k_page(unsigned long addr, unsigned long phys, pgprot_t prot, bool alloc);
1881extern int vmem_map_4k_page(unsigned long addr, unsigned long phys, pgprot_t prot);
1882extern void vmem_unmap_4k_page(unsigned long addr);
2f0e8aae 1883extern pte_t *vmem_get_alloc_pte(unsigned long addr, bool alloc);
402b0862 1884extern int s390_enable_sie(void);
3ac8e380 1885extern int s390_enable_skey(void);
a13cff31 1886extern void s390_reset_cmma(struct mm_struct *mm);
f4eb07c1 1887
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MS		 1888/* s390 has a private copy of get unmapped area to deal with cache synonyms */
1889#define HAVE_ARCH_UNMAPPED_AREA
1890#define HAVE_ARCH_UNMAPPED_AREA_TOPDOWN
1891
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AK		 1892#define pmd_pgtable(pmd) \
1893 ((pgtable_t)__va(pmd_val(pmd) & -sizeof(pte_t)*PTRS_PER_PTE))
1894
1da177e4 1895#endif /* _S390_PAGE_H */
Linux 6.x block layer and io_uring tree(s)