[linux-2.6-block.git] / arch / s390 / include / asm / mmu_context.h

/*
 *  S390 version
 *
 *  Derived from "include/asm-i386/mmu_context.h"
 */

#ifndef __S390_MMU_CONTEXT_H
#define __S390_MMU_CONTEXT_H

#include <asm/pgalloc.h>
#include <asm/uaccess.h>
#include <asm/tlbflush.h>
#include <asm/ctl_reg.h>

static inline int init_new_context(struct task_struct *tsk,
				   struct mm_struct *mm)
{
	cpumask_clear(&mm->context.cpu_attach_mask);
	atomic_set(&mm->context.attach_count, 0);
	mm->context.flush_mm = 0;
	mm->context.asce_bits = _ASCE_TABLE_LENGTH | _ASCE_USER_BITS;
#ifdef CONFIG_64BIT
	mm->context.asce_bits |= _ASCE_TYPE_REGION3;
#endif
	mm->context.has_pgste = 0;
	mm->context.asce_limit = STACK_TOP_MAX;
	crst_table_init((unsigned long *) mm->pgd, pgd_entry_type(mm));
	return 0;
}

#define destroy_context(mm)             do { } while (0)

static inline void update_user_asce(struct mm_struct *mm, int load_primary)
{
	pgd_t *pgd = mm->pgd;

	S390_lowcore.user_asce = mm->context.asce_bits | __pa(pgd);
	if (load_primary)
		__ctl_load(S390_lowcore.user_asce, 1, 1);
	set_fs(current->thread.mm_segment);
}

static inline void clear_user_asce(struct mm_struct *mm, int load_primary)
{
	S390_lowcore.user_asce = S390_lowcore.kernel_asce;

	if (load_primary)
		__ctl_load(S390_lowcore.user_asce, 1, 1);
	__ctl_load(S390_lowcore.user_asce, 7, 7);
}

static inline void update_primary_asce(struct task_struct *tsk)
{
	unsigned long asce;

	__ctl_store(asce, 1, 1);
	if (asce != S390_lowcore.kernel_asce)
		__ctl_load(S390_lowcore.kernel_asce, 1, 1);
	set_tsk_thread_flag(tsk, TIF_ASCE);
}

static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next,
			     struct task_struct *tsk)
{
	int cpu = smp_processor_id();

	update_primary_asce(tsk);
	if (prev == next)
		return;
	if (MACHINE_HAS_TLB_LC)
		cpumask_set_cpu(cpu, &next->context.cpu_attach_mask);
	if (atomic_inc_return(&next->context.attach_count) >> 16) {
		/* Delay update_user_asce until all TLB flushes are done. */
		set_tsk_thread_flag(tsk, TIF_TLB_WAIT);
		/* Clear old ASCE by loading the kernel ASCE. */
		clear_user_asce(next, 0);
	} else {
		cpumask_set_cpu(cpu, mm_cpumask(next));
		update_user_asce(next, 0);
		if (next->context.flush_mm)
			/* Flush pending TLBs */
			__tlb_flush_mm(next);
	}
	atomic_dec(&prev->context.attach_count);
	WARN_ON(atomic_read(&prev->context.attach_count) < 0);
	if (MACHINE_HAS_TLB_LC)
		cpumask_clear_cpu(cpu, &prev->context.cpu_attach_mask);
}

#define finish_arch_post_lock_switch finish_arch_post_lock_switch
static inline void finish_arch_post_lock_switch(void)
{
	struct task_struct *tsk = current;
	struct mm_struct *mm = tsk->mm;

	if (!test_tsk_thread_flag(tsk, TIF_TLB_WAIT))
		return;
	preempt_disable();
	clear_tsk_thread_flag(tsk, TIF_TLB_WAIT);
	while (atomic_read(&mm->context.attach_count) >> 16)
		cpu_relax();

	cpumask_set_cpu(smp_processor_id(), mm_cpumask(mm));
	update_user_asce(mm, 0);
	if (mm->context.flush_mm)
		__tlb_flush_mm(mm);
	preempt_enable();
}

#define enter_lazy_tlb(mm,tsk)	do { } while (0)
#define deactivate_mm(tsk,mm)	do { } while (0)

static inline void activate_mm(struct mm_struct *prev,
                               struct mm_struct *next)
{
        switch_mm(prev, next, current);
}

static inline void arch_dup_mmap(struct mm_struct *oldmm,
				 struct mm_struct *mm)
{
#ifdef CONFIG_64BIT
	if (oldmm->context.asce_limit < mm->context.asce_limit)
		crst_table_downgrade(mm, oldmm->context.asce_limit);
#endif
}

static inline void arch_exit_mmap(struct mm_struct *mm)
{
}

#endif /* __S390_MMU_CONTEXT_H */
Commit	Line	Data
1da177e4	1	/*
1da177e4 LT	2	* S390 version
	3	*
	4	* Derived from "include/asm-i386/mmu_context.h"
	5	*/
	6
	7	#ifndef __S390_MMU_CONTEXT_H
	8	#define __S390_MMU_CONTEXT_H
	9
c1821c2e	10	#include <asm/pgalloc.h>
146e4b3c	11	#include <asm/uaccess.h>
050eef36	12	#include <asm/tlbflush.h>
a0616cde	13	#include <asm/ctl_reg.h>
d6dd61c8	14
6f457e1a MS	15	static inline int init_new_context(struct task_struct *tsk,
	16	struct mm_struct *mm)
	17	{
1b948d6c	18	cpumask_clear(&mm->context.cpu_attach_mask);
050eef36 MS	19	atomic_set(&mm->context.attach_count, 0);
050eef36 MS	20	mm->context.flush_mm = 0;
146e4b3c	21	mm->context.asce_bits = _ASCE_TABLE_LENGTH \| _ASCE_USER_BITS;
6f457e1a	22	#ifdef CONFIG_64BIT
6252d702	23	mm->context.asce_bits \|= _ASCE_TYPE_REGION3;
6f457e1a	24	#endif
3eabaee9	25	mm->context.has_pgste = 0;
6252d702 MS	26	mm->context.asce_limit = STACK_TOP_MAX;
6252d702 MS	27	crst_table_init((unsigned long *) mm->pgd, pgd_entry_type(mm));
6f457e1a MS	28	return 0;
6f457e1a MS	29	}
1da177e4 LT	30
	31	#define destroy_context(mm) do { } while (0)
	32
457f2180	33	static inline void update_user_asce(struct mm_struct *mm, int load_primary)
1da177e4	34	{
146e4b3c MS	35	pgd_t *pgd = mm->pgd;
	36
	37	S390_lowcore.user_asce = mm->context.asce_bits \| __pa(pgd);
457f2180 HC	38	if (load_primary)
457f2180 HC	39	__ctl_load(S390_lowcore.user_asce, 1, 1);
6252d702	40	set_fs(current->thread.mm_segment);
1da177e4 LT	41	}
1da177e4 LT	42
457f2180	43	static inline void clear_user_asce(struct mm_struct *mm, int load_primary)
02a8f3ab MS	44	{
02a8f3ab MS	45	S390_lowcore.user_asce = S390_lowcore.kernel_asce;
457f2180 HC	46
	47	if (load_primary)
	48	__ctl_load(S390_lowcore.user_asce, 1, 1);
	49	__ctl_load(S390_lowcore.user_asce, 7, 7);
	50	}
	51
	52	static inline void update_primary_asce(struct task_struct *tsk)
	53	{
	54	unsigned long asce;
	55
	56	__ctl_store(asce, 1, 1);
	57	if (asce != S390_lowcore.kernel_asce)
	58	__ctl_load(S390_lowcore.kernel_asce, 1, 1);
	59	set_tsk_thread_flag(tsk, TIF_ASCE);
02a8f3ab MS	60	}
02a8f3ab MS	61
1da177e4	62	static inline void switch_mm(struct mm_struct prev, struct mm_struct next,
c1821c2e	63	struct task_struct *tsk)
1da177e4	64	{
53e857f3 MS	65	int cpu = smp_processor_id();
53e857f3 MS	66
457f2180	67	update_primary_asce(tsk);
53e857f3 MS	68	if (prev == next)
53e857f3 MS	69	return;
1b948d6c MS	70	if (MACHINE_HAS_TLB_LC)
1b948d6c MS	71	cpumask_set_cpu(cpu, &next->context.cpu_attach_mask);
53e857f3	72	if (atomic_inc_return(&next->context.attach_count) >> 16) {
02a8f3ab	73	/* Delay update_user_asce until all TLB flushes are done. */
53e857f3	74	set_tsk_thread_flag(tsk, TIF_TLB_WAIT);
02a8f3ab	75	/* Clear old ASCE by loading the kernel ASCE. */
457f2180	76	clear_user_asce(next, 0);
53e857f3 MS	77	} else {
53e857f3 MS	78	cpumask_set_cpu(cpu, mm_cpumask(next));
457f2180	79	update_user_asce(next, 0);
53e857f3 MS	80	if (next->context.flush_mm)
	81	/* Flush pending TLBs */
	82	__tlb_flush_mm(next);
	83	}
050eef36 MS	84	atomic_dec(&prev->context.attach_count);
050eef36 MS	85	WARN_ON(atomic_read(&prev->context.attach_count) < 0);
1b948d6c MS	86	if (MACHINE_HAS_TLB_LC)
1b948d6c MS	87	cpumask_clear_cpu(cpu, &prev->context.cpu_attach_mask);
53e857f3 MS	88	}
	89
	90	#define finish_arch_post_lock_switch finish_arch_post_lock_switch
	91	static inline void finish_arch_post_lock_switch(void)
	92	{
	93	struct task_struct *tsk = current;
	94	struct mm_struct *mm = tsk->mm;
	95
	96	if (!test_tsk_thread_flag(tsk, TIF_TLB_WAIT))
	97	return;
	98	preempt_disable();
	99	clear_tsk_thread_flag(tsk, TIF_TLB_WAIT);
	100	while (atomic_read(&mm->context.attach_count) >> 16)
	101	cpu_relax();
	102
	103	cpumask_set_cpu(smp_processor_id(), mm_cpumask(mm));
457f2180	104	update_user_asce(mm, 0);
53e857f3 MS	105	if (mm->context.flush_mm)
	106	__tlb_flush_mm(mm);
	107	preempt_enable();
1da177e4 LT	108	}
1da177e4 LT	109
3610cce8	110	#define enter_lazy_tlb(mm,tsk) do { } while (0)
1da177e4 LT	111	#define deactivate_mm(tsk,mm) do { } while (0)
1da177e4 LT	112
4448aaf0	113	static inline void activate_mm(struct mm_struct *prev,
1da177e4 LT	114	struct mm_struct *next)
	115	{
	116	switch_mm(prev, next, current);
1da177e4 LT	117	}
1da177e4 LT	118
0f6f281b MS	119	static inline void arch_dup_mmap(struct mm_struct *oldmm,
	120	struct mm_struct *mm)
	121	{
	122	#ifdef CONFIG_64BIT
	123	if (oldmm->context.asce_limit < mm->context.asce_limit)
	124	crst_table_downgrade(mm, oldmm->context.asce_limit);
	125	#endif
	126	}
	127
	128	static inline void arch_exit_mmap(struct mm_struct *mm)
	129	{
	130	}
	131
c1821c2e	132	#endif /* __S390_MMU_CONTEXT_H */