Commit | Line | Data |
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b2441318 | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
1da177e4 | 2 | /* |
1da177e4 LT |
3 | * S390 version |
4 | * | |
5 | * Derived from "include/asm-i386/mmu_context.h" | |
6 | */ | |
7 | ||
8 | #ifndef __S390_MMU_CONTEXT_H | |
9 | #define __S390_MMU_CONTEXT_H | |
10 | ||
c1821c2e | 11 | #include <asm/pgalloc.h> |
7c0f6ba6 | 12 | #include <linux/uaccess.h> |
589ee628 | 13 | #include <linux/mm_types.h> |
050eef36 | 14 | #include <asm/tlbflush.h> |
a0616cde | 15 | #include <asm/ctl_reg.h> |
8e58ab5c | 16 | #include <asm-generic/mm_hooks.h> |
d6dd61c8 | 17 | |
6f457e1a MS |
18 | static inline int init_new_context(struct task_struct *tsk, |
19 | struct mm_struct *mm) | |
20 | { | |
60f07c8e | 21 | spin_lock_init(&mm->context.lock); |
3446c13b MS |
22 | INIT_LIST_HEAD(&mm->context.pgtable_list); |
23 | INIT_LIST_HEAD(&mm->context.gmap_list); | |
1b948d6c | 24 | cpumask_clear(&mm->context.cpu_attach_mask); |
64f31d58 | 25 | atomic_set(&mm->context.flush_count, 0); |
44b6cc81 | 26 | mm->context.gmap_asce = 0; |
050eef36 | 27 | mm->context.flush_mm = 0; |
d1befa65 | 28 | mm->context.compat_mm = 0; |
0b46e0a3 | 29 | #ifdef CONFIG_PGSTE |
23fefe11 MS |
30 | mm->context.alloc_pgste = page_table_allocate_pgste || |
31 | test_thread_flag(TIF_PGSTE) || | |
53c4ab70 | 32 | (current->mm && current->mm->context.alloc_pgste); |
3eabaee9 | 33 | mm->context.has_pgste = 0; |
55531b74 | 34 | mm->context.uses_skeys = 0; |
c9f0a2b8 | 35 | mm->context.uses_cmm = 0; |
a9e00d83 | 36 | mm->context.allow_gmap_hpage_1m = 0; |
0b46e0a3 | 37 | #endif |
723cacbd | 38 | switch (mm->context.asce_limit) { |
f1c1174f | 39 | case _REGION2_SIZE: |
723cacbd GS |
40 | /* |
41 | * forked 3-level task, fall through to set new asce with new | |
42 | * mm->pgd | |
43 | */ | |
44 | case 0: | |
3446c13b | 45 | /* context created by exec, set asce limit to 4TB */ |
3446c13b | 46 | mm->context.asce_limit = STACK_TOP_MAX; |
723cacbd GS |
47 | mm->context.asce = __pa(mm->pgd) | _ASCE_TABLE_LENGTH | |
48 | _ASCE_USER_BITS | _ASCE_TYPE_REGION3; | |
b4e98d9a KS |
49 | /* pgd_alloc() did not account this pud */ |
50 | mm_inc_nr_puds(mm); | |
723cacbd | 51 | break; |
0b89ede6 MS |
52 | case -PAGE_SIZE: |
53 | /* forked 5-level task, set new asce with new_mm->pgd */ | |
54 | mm->context.asce = __pa(mm->pgd) | _ASCE_TABLE_LENGTH | | |
55 | _ASCE_USER_BITS | _ASCE_TYPE_REGION1; | |
56 | break; | |
f1c1174f | 57 | case _REGION1_SIZE: |
723cacbd GS |
58 | /* forked 4-level task, set new asce with new mm->pgd */ |
59 | mm->context.asce = __pa(mm->pgd) | _ASCE_TABLE_LENGTH | | |
60 | _ASCE_USER_BITS | _ASCE_TYPE_REGION2; | |
61 | break; | |
f1c1174f | 62 | case _REGION3_SIZE: |
723cacbd GS |
63 | /* forked 2-level compat task, set new asce with new mm->pgd */ |
64 | mm->context.asce = __pa(mm->pgd) | _ASCE_TABLE_LENGTH | | |
65 | _ASCE_USER_BITS | _ASCE_TYPE_SEGMENT; | |
b4e98d9a | 66 | /* pgd_alloc() did not account this pmd */ |
3446c13b | 67 | mm_inc_nr_pmds(mm); |
61e18270 | 68 | mm_inc_nr_puds(mm); |
3446c13b | 69 | } |
6252d702 | 70 | crst_table_init((unsigned long *) mm->pgd, pgd_entry_type(mm)); |
6f457e1a MS |
71 | return 0; |
72 | } | |
1da177e4 LT |
73 | |
74 | #define destroy_context(mm) do { } while (0) | |
75 | ||
beef560b | 76 | static inline void set_user_asce(struct mm_struct *mm) |
1da177e4 | 77 | { |
723cacbd | 78 | S390_lowcore.user_asce = mm->context.asce; |
0aaba41b MS |
79 | __ctl_load(S390_lowcore.user_asce, 1, 1); |
80 | clear_cpu_flag(CIF_ASCE_PRIMARY); | |
1da177e4 LT |
81 | } |
82 | ||
beef560b | 83 | static inline void clear_user_asce(void) |
02a8f3ab MS |
84 | { |
85 | S390_lowcore.user_asce = S390_lowcore.kernel_asce; | |
0aaba41b | 86 | __ctl_load(S390_lowcore.kernel_asce, 1, 1); |
606aa4aa | 87 | set_cpu_flag(CIF_ASCE_PRIMARY); |
02a8f3ab MS |
88 | } |
89 | ||
0aaba41b MS |
90 | mm_segment_t enable_sacf_uaccess(void); |
91 | void disable_sacf_uaccess(mm_segment_t old_fs); | |
92 | ||
1da177e4 | 93 | static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next, |
c1821c2e | 94 | struct task_struct *tsk) |
1da177e4 | 95 | { |
53e857f3 MS |
96 | int cpu = smp_processor_id(); |
97 | ||
98 | if (prev == next) | |
99 | return; | |
0aaba41b | 100 | S390_lowcore.user_asce = next->context.asce; |
64f31d58 | 101 | cpumask_set_cpu(cpu, &next->context.cpu_attach_mask); |
0aaba41b MS |
102 | /* Clear previous user-ASCE from CR1 and CR7 */ |
103 | if (!test_cpu_flag(CIF_ASCE_PRIMARY)) { | |
104 | __ctl_load(S390_lowcore.kernel_asce, 1, 1); | |
105 | set_cpu_flag(CIF_ASCE_PRIMARY); | |
106 | } | |
107 | if (test_cpu_flag(CIF_ASCE_SECONDARY)) { | |
108 | __ctl_load(S390_lowcore.vdso_asce, 7, 7); | |
109 | clear_cpu_flag(CIF_ASCE_SECONDARY); | |
110 | } | |
64f31d58 | 111 | cpumask_clear_cpu(cpu, &prev->context.cpu_attach_mask); |
53e857f3 MS |
112 | } |
113 | ||
114 | #define finish_arch_post_lock_switch finish_arch_post_lock_switch | |
115 | static inline void finish_arch_post_lock_switch(void) | |
116 | { | |
117 | struct task_struct *tsk = current; | |
118 | struct mm_struct *mm = tsk->mm; | |
119 | ||
f8b13505 MS |
120 | if (mm) { |
121 | preempt_disable(); | |
64f31d58 | 122 | while (atomic_read(&mm->context.flush_count)) |
f8b13505 | 123 | cpu_relax(); |
b3e5dc45 | 124 | cpumask_set_cpu(smp_processor_id(), mm_cpumask(mm)); |
60f07c8e | 125 | __tlb_flush_mm_lazy(mm); |
f8b13505 MS |
126 | preempt_enable(); |
127 | } | |
128 | set_fs(current->thread.mm_segment); | |
1da177e4 LT |
129 | } |
130 | ||
3610cce8 | 131 | #define enter_lazy_tlb(mm,tsk) do { } while (0) |
1da177e4 LT |
132 | #define deactivate_mm(tsk,mm) do { } while (0) |
133 | ||
4448aaf0 | 134 | static inline void activate_mm(struct mm_struct *prev, |
1da177e4 LT |
135 | struct mm_struct *next) |
136 | { | |
beef560b | 137 | switch_mm(prev, next, current); |
b3e5dc45 | 138 | cpumask_set_cpu(smp_processor_id(), mm_cpumask(next)); |
beef560b | 139 | set_user_asce(next); |
1da177e4 LT |
140 | } |
141 | ||
c1821c2e | 142 | #endif /* __S390_MMU_CONTEXT_H */ |