[linux-block.git] / arch / s390 / include / asm / mmu_context.h

/* SPDX-License-Identifier: GPL-2.0 */
/*
 *  S390 version
 *
 *  Derived from "include/asm-i386/mmu_context.h"
 */

#ifndef __S390_MMU_CONTEXT_H
#define __S390_MMU_CONTEXT_H

#include <asm/pgalloc.h>
#include <linux/uaccess.h>
#include <linux/mm_types.h>
#include <asm/tlbflush.h>
#include <asm/ctl_reg.h>
#include <asm-generic/mm_hooks.h>

static inline int init_new_context(struct task_struct *tsk,
				   struct mm_struct *mm)
{
	spin_lock_init(&mm->context.lock);
	INIT_LIST_HEAD(&mm->context.pgtable_list);
	INIT_LIST_HEAD(&mm->context.gmap_list);
	cpumask_clear(&mm->context.cpu_attach_mask);
	atomic_set(&mm->context.flush_count, 0);
	mm->context.gmap_asce = 0;
	mm->context.flush_mm = 0;
#ifdef CONFIG_PGSTE
	mm->context.alloc_pgste = page_table_allocate_pgste ||
		test_thread_flag(TIF_PGSTE) ||
		(current->mm && current->mm->context.alloc_pgste);
	mm->context.has_pgste = 0;
	mm->context.use_skey = 0;
	mm->context.use_cmma = 0;
#endif
	switch (mm->context.asce_limit) {
	case _REGION2_SIZE:
		/*
		 * forked 3-level task, fall through to set new asce with new
		 * mm->pgd
		 */
	case 0:
		/* context created by exec, set asce limit to 4TB */
		mm->context.asce_limit = STACK_TOP_MAX;
		mm->context.asce = __pa(mm->pgd) | _ASCE_TABLE_LENGTH |
				   _ASCE_USER_BITS | _ASCE_TYPE_REGION3;
		/* pgd_alloc() did not account this pud */
		mm_inc_nr_puds(mm);
		break;
	case -PAGE_SIZE:
		/* forked 5-level task, set new asce with new_mm->pgd */
		mm->context.asce = __pa(mm->pgd) | _ASCE_TABLE_LENGTH |
			_ASCE_USER_BITS | _ASCE_TYPE_REGION1;
		break;
	case _REGION1_SIZE:
		/* forked 4-level task, set new asce with new mm->pgd */
		mm->context.asce = __pa(mm->pgd) | _ASCE_TABLE_LENGTH |
				   _ASCE_USER_BITS | _ASCE_TYPE_REGION2;
		break;
	case _REGION3_SIZE:
		/* forked 2-level compat task, set new asce with new mm->pgd */
		mm->context.asce = __pa(mm->pgd) | _ASCE_TABLE_LENGTH |
				   _ASCE_USER_BITS | _ASCE_TYPE_SEGMENT;
		/* pgd_alloc() did not account this pmd */
		mm_inc_nr_pmds(mm);
		mm_inc_nr_puds(mm);
	}
	crst_table_init((unsigned long *) mm->pgd, pgd_entry_type(mm));
	return 0;
}

#define destroy_context(mm)             do { } while (0)

static inline void set_user_asce(struct mm_struct *mm)
{
	S390_lowcore.user_asce = mm->context.asce;
	__ctl_load(S390_lowcore.user_asce, 1, 1);
	clear_cpu_flag(CIF_ASCE_PRIMARY);
}

static inline void clear_user_asce(void)
{
	S390_lowcore.user_asce = S390_lowcore.kernel_asce;
	__ctl_load(S390_lowcore.kernel_asce, 1, 1);
	set_cpu_flag(CIF_ASCE_PRIMARY);
}

mm_segment_t enable_sacf_uaccess(void);
void disable_sacf_uaccess(mm_segment_t old_fs);

static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next,
			     struct task_struct *tsk)
{
	int cpu = smp_processor_id();

	if (prev == next)
		return;
	S390_lowcore.user_asce = next->context.asce;
	cpumask_set_cpu(cpu, &next->context.cpu_attach_mask);
	/* Clear previous user-ASCE from CR1 and CR7 */
	if (!test_cpu_flag(CIF_ASCE_PRIMARY)) {
		__ctl_load(S390_lowcore.kernel_asce, 1, 1);
		set_cpu_flag(CIF_ASCE_PRIMARY);
	}
	if (test_cpu_flag(CIF_ASCE_SECONDARY)) {
		__ctl_load(S390_lowcore.vdso_asce, 7, 7);
		clear_cpu_flag(CIF_ASCE_SECONDARY);
	}
	cpumask_clear_cpu(cpu, &prev->context.cpu_attach_mask);
}

#define finish_arch_post_lock_switch finish_arch_post_lock_switch
static inline void finish_arch_post_lock_switch(void)
{
	struct task_struct *tsk = current;
	struct mm_struct *mm = tsk->mm;

	if (mm) {
		preempt_disable();
		while (atomic_read(&mm->context.flush_count))
			cpu_relax();
		cpumask_set_cpu(smp_processor_id(), mm_cpumask(mm));
		__tlb_flush_mm_lazy(mm);
		preempt_enable();
	}
	set_fs(current->thread.mm_segment);
}

#define enter_lazy_tlb(mm,tsk)	do { } while (0)
#define deactivate_mm(tsk,mm)	do { } while (0)

static inline void activate_mm(struct mm_struct *prev,
                               struct mm_struct *next)
{
	switch_mm(prev, next, current);
	cpumask_set_cpu(smp_processor_id(), mm_cpumask(next));
	set_user_asce(next);
}

#endif /* __S390_MMU_CONTEXT_H */
Commit	Line	Data
b2441318	1	/* SPDX-License-Identifier: GPL-2.0 */
1da177e4	2	/*
1da177e4 LT	3	* S390 version
	4	*
	5	* Derived from "include/asm-i386/mmu_context.h"
	6	*/
	7
	8	#ifndef __S390_MMU_CONTEXT_H
	9	#define __S390_MMU_CONTEXT_H
	10
c1821c2e	11	#include <asm/pgalloc.h>
7c0f6ba6	12	#include <linux/uaccess.h>
589ee628	13	#include <linux/mm_types.h>
050eef36	14	#include <asm/tlbflush.h>
a0616cde	15	#include <asm/ctl_reg.h>
8e58ab5c	16	#include <asm-generic/mm_hooks.h>
d6dd61c8	17
6f457e1a MS	18	static inline int init_new_context(struct task_struct *tsk,
	19	struct mm_struct *mm)
	20	{
60f07c8e	21	spin_lock_init(&mm->context.lock);
3446c13b MS	22	INIT_LIST_HEAD(&mm->context.pgtable_list);
3446c13b MS	23	INIT_LIST_HEAD(&mm->context.gmap_list);
1b948d6c	24	cpumask_clear(&mm->context.cpu_attach_mask);
64f31d58	25	atomic_set(&mm->context.flush_count, 0);
44b6cc81	26	mm->context.gmap_asce = 0;
050eef36	27	mm->context.flush_mm = 0;
0b46e0a3	28	#ifdef CONFIG_PGSTE
23fefe11 MS	29	mm->context.alloc_pgste = page_table_allocate_pgste \|\|
23fefe11 MS	30	test_thread_flag(TIF_PGSTE) \|\|
53c4ab70	31	(current->mm && current->mm->context.alloc_pgste);
3eabaee9	32	mm->context.has_pgste = 0;
693ffc08	33	mm->context.use_skey = 0;
aa824e13	34	mm->context.use_cmma = 0;
0b46e0a3	35	#endif
723cacbd	36	switch (mm->context.asce_limit) {
f1c1174f	37	case _REGION2_SIZE:
723cacbd GS	38	/*
	39	* forked 3-level task, fall through to set new asce with new
	40	* mm->pgd
	41	*/
	42	case 0:
3446c13b	43	/* context created by exec, set asce limit to 4TB */
3446c13b	44	mm->context.asce_limit = STACK_TOP_MAX;
723cacbd GS	45	mm->context.asce = __pa(mm->pgd) \| _ASCE_TABLE_LENGTH \|
723cacbd GS	46	_ASCE_USER_BITS \| _ASCE_TYPE_REGION3;
b4e98d9a KS	47	/* pgd_alloc() did not account this pud */
b4e98d9a KS	48	mm_inc_nr_puds(mm);
723cacbd	49	break;
0b89ede6 MS	50	case -PAGE_SIZE:
	51	/* forked 5-level task, set new asce with new_mm->pgd */
	52	mm->context.asce = __pa(mm->pgd) \| _ASCE_TABLE_LENGTH \|
	53	_ASCE_USER_BITS \| _ASCE_TYPE_REGION1;
	54	break;
f1c1174f	55	case _REGION1_SIZE:
723cacbd GS	56	/* forked 4-level task, set new asce with new mm->pgd */
	57	mm->context.asce = __pa(mm->pgd) \| _ASCE_TABLE_LENGTH \|
	58	_ASCE_USER_BITS \| _ASCE_TYPE_REGION2;
	59	break;
f1c1174f	60	case _REGION3_SIZE:
723cacbd GS	61	/* forked 2-level compat task, set new asce with new mm->pgd */
	62	mm->context.asce = __pa(mm->pgd) \| _ASCE_TABLE_LENGTH \|
	63	_ASCE_USER_BITS \| _ASCE_TYPE_SEGMENT;
b4e98d9a	64	/* pgd_alloc() did not account this pmd */
3446c13b	65	mm_inc_nr_pmds(mm);
61e18270	66	mm_inc_nr_puds(mm);
3446c13b	67	}
6252d702	68	crst_table_init((unsigned long *) mm->pgd, pgd_entry_type(mm));
6f457e1a MS	69	return 0;
6f457e1a MS	70	}
1da177e4 LT	71
	72	#define destroy_context(mm) do { } while (0)
	73
beef560b	74	static inline void set_user_asce(struct mm_struct *mm)
1da177e4	75	{
723cacbd	76	S390_lowcore.user_asce = mm->context.asce;
0aaba41b MS	77	__ctl_load(S390_lowcore.user_asce, 1, 1);
0aaba41b MS	78	clear_cpu_flag(CIF_ASCE_PRIMARY);
1da177e4 LT	79	}
1da177e4 LT	80
beef560b	81	static inline void clear_user_asce(void)
02a8f3ab MS	82	{
02a8f3ab MS	83	S390_lowcore.user_asce = S390_lowcore.kernel_asce;
0aaba41b	84	__ctl_load(S390_lowcore.kernel_asce, 1, 1);
606aa4aa	85	set_cpu_flag(CIF_ASCE_PRIMARY);
02a8f3ab MS	86	}
02a8f3ab MS	87
0aaba41b MS	88	mm_segment_t enable_sacf_uaccess(void);
	89	void disable_sacf_uaccess(mm_segment_t old_fs);
	90
1da177e4	91	static inline void switch_mm(struct mm_struct prev, struct mm_struct next,
c1821c2e	92	struct task_struct *tsk)
1da177e4	93	{
53e857f3 MS	94	int cpu = smp_processor_id();
	95
	96	if (prev == next)
	97	return;
0aaba41b	98	S390_lowcore.user_asce = next->context.asce;
64f31d58	99	cpumask_set_cpu(cpu, &next->context.cpu_attach_mask);
0aaba41b MS	100	/* Clear previous user-ASCE from CR1 and CR7 */
	101	if (!test_cpu_flag(CIF_ASCE_PRIMARY)) {
	102	__ctl_load(S390_lowcore.kernel_asce, 1, 1);
	103	set_cpu_flag(CIF_ASCE_PRIMARY);
	104	}
	105	if (test_cpu_flag(CIF_ASCE_SECONDARY)) {
	106	__ctl_load(S390_lowcore.vdso_asce, 7, 7);
	107	clear_cpu_flag(CIF_ASCE_SECONDARY);
	108	}
64f31d58	109	cpumask_clear_cpu(cpu, &prev->context.cpu_attach_mask);
53e857f3 MS	110	}
	111
	112	#define finish_arch_post_lock_switch finish_arch_post_lock_switch
	113	static inline void finish_arch_post_lock_switch(void)
	114	{
	115	struct task_struct *tsk = current;
	116	struct mm_struct *mm = tsk->mm;
	117
f8b13505 MS	118	if (mm) {
f8b13505 MS	119	preempt_disable();
64f31d58	120	while (atomic_read(&mm->context.flush_count))
f8b13505	121	cpu_relax();
b3e5dc45	122	cpumask_set_cpu(smp_processor_id(), mm_cpumask(mm));
60f07c8e	123	__tlb_flush_mm_lazy(mm);
f8b13505 MS	124	preempt_enable();
	125	}
	126	set_fs(current->thread.mm_segment);
1da177e4 LT	127	}
1da177e4 LT	128
3610cce8	129	#define enter_lazy_tlb(mm,tsk) do { } while (0)
1da177e4 LT	130	#define deactivate_mm(tsk,mm) do { } while (0)
1da177e4 LT	131
4448aaf0	132	static inline void activate_mm(struct mm_struct *prev,
1da177e4 LT	133	struct mm_struct *next)
1da177e4 LT	134	{
beef560b	135	switch_mm(prev, next, current);
b3e5dc45	136	cpumask_set_cpu(smp_processor_id(), mm_cpumask(next));
beef560b	137	set_user_asce(next);
1da177e4 LT	138	}
1da177e4 LT	139
c1821c2e	140	#endif /* __S390_MMU_CONTEXT_H */