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a0616cde DH |
1 | /* |
2 | * Copyright IBM Corp. 1999, 2009 | |
3 | * | |
4 | * Author(s): Martin Schwidefsky <schwidefsky@de.ibm.com> | |
5 | */ | |
6 | ||
7 | #ifndef __ASM_BARRIER_H | |
8 | #define __ASM_BARRIER_H | |
9 | ||
10 | /* | |
11 | * Force strict CPU ordering. | |
12 | * And yes, this is required on UP too when we're talking | |
13 | * to devices. | |
14 | * | |
15 | * This is very similar to the ppc eieio/sync instruction in that is | |
16 | * does a checkpoint syncronisation & makes sure that | |
17 | * all memory ops have completed wrt other CPU's ( see 7-15 POP DJB ). | |
18 | */ | |
19 | ||
20 | #define eieio() asm volatile("bcr 15,0" : : : "memory") | |
21 | #define SYNC_OTHER_CORES(x) eieio() | |
22 | #define mb() eieio() | |
23 | #define rmb() eieio() | |
24 | #define wmb() eieio() | |
25 | #define read_barrier_depends() do { } while(0) | |
26 | #define smp_mb() mb() | |
27 | #define smp_rmb() rmb() | |
28 | #define smp_wmb() wmb() | |
29 | #define smp_read_barrier_depends() read_barrier_depends() | |
30 | #define smp_mb__before_clear_bit() smp_mb() | |
31 | #define smp_mb__after_clear_bit() smp_mb() | |
32 | ||
33 | #define set_mb(var, value) do { var = value; mb(); } while (0) | |
34 | ||
35 | #endif /* __ASM_BARRIER_H */ |