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50acfb2b | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
5d8544e2 PD |
2 | /* |
3 | * Copyright (C) 2013 Regents of the University of California | |
5d8544e2 PD |
4 | */ |
5 | ||
6 | ||
7 | #include <linux/linkage.h> | |
8 | #include <asm/asm.h> | |
9 | ||
10 | /* void *memset(void *, int, size_t) */ | |
8ad8b727 NH |
11 | ENTRY(__memset) |
12 | WEAK(memset) | |
5d8544e2 PD |
13 | move t0, a0 /* Preserve return value */ |
14 | ||
15 | /* Defer to byte-oriented fill for small sizes */ | |
16 | sltiu a3, a2, 16 | |
17 | bnez a3, 4f | |
18 | ||
19 | /* | |
20 | * Round to nearest XLEN-aligned address | |
21 | * greater than or equal to start address | |
22 | */ | |
23 | addi a3, t0, SZREG-1 | |
24 | andi a3, a3, ~(SZREG-1) | |
25 | beq a3, t0, 2f /* Skip if already aligned */ | |
26 | /* Handle initial misalignment */ | |
27 | sub a4, a3, t0 | |
28 | 1: | |
29 | sb a1, 0(t0) | |
30 | addi t0, t0, 1 | |
31 | bltu t0, a3, 1b | |
32 | sub a2, a2, a4 /* Update count */ | |
33 | ||
34 | 2: /* Duff's device with 32 XLEN stores per iteration */ | |
35 | /* Broadcast value into all bytes */ | |
36 | andi a1, a1, 0xff | |
37 | slli a3, a1, 8 | |
38 | or a1, a3, a1 | |
39 | slli a3, a1, 16 | |
40 | or a1, a3, a1 | |
41 | #ifdef CONFIG_64BIT | |
42 | slli a3, a1, 32 | |
43 | or a1, a3, a1 | |
44 | #endif | |
45 | ||
46 | /* Calculate end address */ | |
47 | andi a4, a2, ~(SZREG-1) | |
48 | add a3, t0, a4 | |
49 | ||
50 | andi a4, a4, 31*SZREG /* Calculate remainder */ | |
51 | beqz a4, 3f /* Shortcut if no remainder */ | |
52 | neg a4, a4 | |
53 | addi a4, a4, 32*SZREG /* Calculate initial offset */ | |
54 | ||
55 | /* Adjust start address with offset */ | |
56 | sub t0, t0, a4 | |
57 | ||
58 | /* Jump into loop body */ | |
59 | /* Assumes 32-bit instruction lengths */ | |
60 | la a5, 3f | |
61 | #ifdef CONFIG_64BIT | |
62 | srli a4, a4, 1 | |
63 | #endif | |
64 | add a5, a5, a4 | |
65 | jr a5 | |
66 | 3: | |
67 | REG_S a1, 0(t0) | |
68 | REG_S a1, SZREG(t0) | |
69 | REG_S a1, 2*SZREG(t0) | |
70 | REG_S a1, 3*SZREG(t0) | |
71 | REG_S a1, 4*SZREG(t0) | |
72 | REG_S a1, 5*SZREG(t0) | |
73 | REG_S a1, 6*SZREG(t0) | |
74 | REG_S a1, 7*SZREG(t0) | |
75 | REG_S a1, 8*SZREG(t0) | |
76 | REG_S a1, 9*SZREG(t0) | |
77 | REG_S a1, 10*SZREG(t0) | |
78 | REG_S a1, 11*SZREG(t0) | |
79 | REG_S a1, 12*SZREG(t0) | |
80 | REG_S a1, 13*SZREG(t0) | |
81 | REG_S a1, 14*SZREG(t0) | |
82 | REG_S a1, 15*SZREG(t0) | |
83 | REG_S a1, 16*SZREG(t0) | |
84 | REG_S a1, 17*SZREG(t0) | |
85 | REG_S a1, 18*SZREG(t0) | |
86 | REG_S a1, 19*SZREG(t0) | |
87 | REG_S a1, 20*SZREG(t0) | |
88 | REG_S a1, 21*SZREG(t0) | |
89 | REG_S a1, 22*SZREG(t0) | |
90 | REG_S a1, 23*SZREG(t0) | |
91 | REG_S a1, 24*SZREG(t0) | |
92 | REG_S a1, 25*SZREG(t0) | |
93 | REG_S a1, 26*SZREG(t0) | |
94 | REG_S a1, 27*SZREG(t0) | |
95 | REG_S a1, 28*SZREG(t0) | |
96 | REG_S a1, 29*SZREG(t0) | |
97 | REG_S a1, 30*SZREG(t0) | |
98 | REG_S a1, 31*SZREG(t0) | |
99 | addi t0, t0, 32*SZREG | |
100 | bltu t0, a3, 3b | |
101 | andi a2, a2, SZREG-1 /* Update count */ | |
102 | ||
103 | 4: | |
104 | /* Handle trailing misalignment */ | |
105 | beqz a2, 6f | |
106 | add a3, t0, a2 | |
107 | 5: | |
108 | sb a1, 0(t0) | |
109 | addi t0, t0, 1 | |
110 | bltu t0, a3, 5b | |
111 | 6: | |
112 | ret | |
8ad8b727 | 113 | END(__memset) |