[linux-2.6-block.git] / arch / riscv / kernel / cpu.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (C) 2012 Regents of the University of California
 */

#include <linux/acpi.h>
#include <linux/cpu.h>
#include <linux/ctype.h>
#include <linux/init.h>
#include <linux/seq_file.h>
#include <linux/of.h>
#include <asm/acpi.h>
#include <asm/cpufeature.h>
#include <asm/csr.h>
#include <asm/hwcap.h>
#include <asm/sbi.h>
#include <asm/smp.h>
#include <asm/pgtable.h>
#include <asm/vendor_extensions.h>

bool arch_match_cpu_phys_id(int cpu, u64 phys_id)
{
	return phys_id == cpuid_to_hartid_map(cpu);
}

/*
 * Returns the hart ID of the given device tree node, or -ENODEV if the node
 * isn't an enabled and valid RISC-V hart node.
 */
int riscv_of_processor_hartid(struct device_node *node, unsigned long *hart)
{
	int cpu;

	*hart = (unsigned long)of_get_cpu_hwid(node, 0);
	if (*hart == ~0UL) {
		pr_warn("Found CPU without hart ID\n");
		return -ENODEV;
	}

	cpu = riscv_hartid_to_cpuid(*hart);
	if (cpu < 0)
		return cpu;

	if (!cpu_possible(cpu))
		return -ENODEV;

	return 0;
}

int __init riscv_early_of_processor_hartid(struct device_node *node, unsigned long *hart)
{
	const char *isa;

	if (!of_device_is_compatible(node, "riscv")) {
		pr_warn("Found incompatible CPU\n");
		return -ENODEV;
	}

	*hart = (unsigned long)of_get_cpu_hwid(node, 0);
	if (*hart == ~0UL) {
		pr_warn("Found CPU without hart ID\n");
		return -ENODEV;
	}

	if (!of_device_is_available(node)) {
		pr_info("CPU with hartid=%lu is not available\n", *hart);
		return -ENODEV;
	}

	if (of_property_read_string(node, "riscv,isa-base", &isa))
		goto old_interface;

	if (IS_ENABLED(CONFIG_32BIT) && strncasecmp(isa, "rv32i", 5)) {
		pr_warn("CPU with hartid=%lu does not support rv32i", *hart);
		return -ENODEV;
	}

	if (IS_ENABLED(CONFIG_64BIT) && strncasecmp(isa, "rv64i", 5)) {
		pr_warn("CPU with hartid=%lu does not support rv64i", *hart);
		return -ENODEV;
	}

	if (!of_property_present(node, "riscv,isa-extensions"))
		return -ENODEV;

	if (of_property_match_string(node, "riscv,isa-extensions", "i") < 0 ||
	    of_property_match_string(node, "riscv,isa-extensions", "m") < 0 ||
	    of_property_match_string(node, "riscv,isa-extensions", "a") < 0) {
		pr_warn("CPU with hartid=%lu does not support ima", *hart);
		return -ENODEV;
	}

	return 0;

old_interface:
	if (!riscv_isa_fallback) {
		pr_warn("CPU with hartid=%lu is invalid: this kernel does not parse \"riscv,isa\"",
			*hart);
		return -ENODEV;
	}

	if (of_property_read_string(node, "riscv,isa", &isa)) {
		pr_warn("CPU with hartid=%lu has no \"riscv,isa-base\" or \"riscv,isa\" property\n",
			*hart);
		return -ENODEV;
	}

	if (IS_ENABLED(CONFIG_32BIT) && strncasecmp(isa, "rv32ima", 7)) {
		pr_warn("CPU with hartid=%lu does not support rv32ima", *hart);
		return -ENODEV;
	}

	if (IS_ENABLED(CONFIG_64BIT) && strncasecmp(isa, "rv64ima", 7)) {
		pr_warn("CPU with hartid=%lu does not support rv64ima", *hart);
		return -ENODEV;
	}

	return 0;
}

/*
 * Find hart ID of the CPU DT node under which given DT node falls.
 *
 * To achieve this, we walk up the DT tree until we find an active
 * RISC-V core (HART) node and extract the cpuid from it.
 */
int riscv_of_parent_hartid(struct device_node *node, unsigned long *hartid)
{
	for (; node; node = node->parent) {
		if (of_device_is_compatible(node, "riscv")) {
			*hartid = (unsigned long)of_get_cpu_hwid(node, 0);
			if (*hartid == ~0UL) {
				pr_warn("Found CPU without hart ID\n");
				return -ENODEV;
			}
			return 0;
		}
	}

	return -1;
}

unsigned long __init riscv_get_marchid(void)
{
	struct riscv_cpuinfo *ci = this_cpu_ptr(&riscv_cpuinfo);

#if IS_ENABLED(CONFIG_RISCV_SBI)
	ci->marchid = sbi_spec_is_0_1() ? 0 : sbi_get_marchid();
#elif IS_ENABLED(CONFIG_RISCV_M_MODE)
	ci->marchid = csr_read(CSR_MARCHID);
#else
	ci->marchid = 0;
#endif
	return ci->marchid;
}

unsigned long __init riscv_get_mvendorid(void)
{
	struct riscv_cpuinfo *ci = this_cpu_ptr(&riscv_cpuinfo);

#if IS_ENABLED(CONFIG_RISCV_SBI)
	ci->mvendorid = sbi_spec_is_0_1() ? 0 : sbi_get_mvendorid();
#elif IS_ENABLED(CONFIG_RISCV_M_MODE)
	ci->mvendorid = csr_read(CSR_MVENDORID);
#else
	ci->mvendorid = 0;
#endif
	return ci->mvendorid;
}

DEFINE_PER_CPU(struct riscv_cpuinfo, riscv_cpuinfo);

unsigned long riscv_cached_mvendorid(unsigned int cpu_id)
{
	struct riscv_cpuinfo *ci = per_cpu_ptr(&riscv_cpuinfo, cpu_id);

	return ci->mvendorid;
}
EXPORT_SYMBOL(riscv_cached_mvendorid);

unsigned long riscv_cached_marchid(unsigned int cpu_id)
{
	struct riscv_cpuinfo *ci = per_cpu_ptr(&riscv_cpuinfo, cpu_id);

	return ci->marchid;
}
EXPORT_SYMBOL(riscv_cached_marchid);

unsigned long riscv_cached_mimpid(unsigned int cpu_id)
{
	struct riscv_cpuinfo *ci = per_cpu_ptr(&riscv_cpuinfo, cpu_id);

	return ci->mimpid;
}
EXPORT_SYMBOL(riscv_cached_mimpid);

static int riscv_cpuinfo_starting(unsigned int cpu)
{
	struct riscv_cpuinfo *ci = this_cpu_ptr(&riscv_cpuinfo);

#if IS_ENABLED(CONFIG_RISCV_SBI)
	if (!ci->mvendorid)
		ci->mvendorid = sbi_spec_is_0_1() ? 0 : sbi_get_mvendorid();
	if (!ci->marchid)
		ci->marchid = sbi_spec_is_0_1() ? 0 : sbi_get_marchid();
	ci->mimpid = sbi_spec_is_0_1() ? 0 : sbi_get_mimpid();
#elif IS_ENABLED(CONFIG_RISCV_M_MODE)
	if (!ci->mvendorid)
		ci->mvendorid = csr_read(CSR_MVENDORID);
	if (!ci->marchid)
		ci->marchid = csr_read(CSR_MARCHID);
	ci->mimpid = csr_read(CSR_MIMPID);
#else
	ci->mvendorid = 0;
	ci->marchid = 0;
	ci->mimpid = 0;
#endif

	return 0;
}

static int __init riscv_cpuinfo_init(void)
{
	int ret;

	ret = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "riscv/cpuinfo:starting",
				riscv_cpuinfo_starting, NULL);
	if (ret < 0) {
		pr_err("cpuinfo: failed to register hotplug callbacks.\n");
		return ret;
	}

	return 0;
}
arch_initcall(riscv_cpuinfo_init);

#ifdef CONFIG_PROC_FS

#define ALL_CPUS -1

static void print_vendor_isa(struct seq_file *f, int cpu)
{
	struct riscv_isavendorinfo *vendor_bitmap;
	struct riscv_isa_vendor_ext_data_list *ext_list;
	const struct riscv_isa_ext_data *ext_data;

	for (int i = 0; i < riscv_isa_vendor_ext_list_size; i++) {
		ext_list = riscv_isa_vendor_ext_list[i];
		ext_data = riscv_isa_vendor_ext_list[i]->ext_data;

		if (cpu == ALL_CPUS)
			vendor_bitmap = &ext_list->all_harts_isa_bitmap;
		else
			vendor_bitmap = &ext_list->per_hart_isa_bitmap[cpu];

		for (int j = 0; j < ext_list->ext_data_count; j++) {
			if (!__riscv_isa_extension_available(vendor_bitmap->isa, ext_data[j].id))
				continue;

			seq_printf(f, "_%s", ext_data[j].name);
		}
	}
}

static void print_isa(struct seq_file *f, const unsigned long *isa_bitmap, int cpu)
{

	if (IS_ENABLED(CONFIG_32BIT))
		seq_write(f, "rv32", 4);
	else
		seq_write(f, "rv64", 4);

	for (int i = 0; i < riscv_isa_ext_count; i++) {
		if (!__riscv_isa_extension_available(isa_bitmap, riscv_isa_ext[i].id))
			continue;

		/* Only multi-letter extensions are split by underscores */
		if (strnlen(riscv_isa_ext[i].name, 2) != 1)
			seq_puts(f, "_");

		seq_printf(f, "%s", riscv_isa_ext[i].name);
	}

	print_vendor_isa(f, cpu);

	seq_puts(f, "\n");
}

static void print_mmu(struct seq_file *f)
{
	const char *sv_type;

#ifdef CONFIG_MMU
#if defined(CONFIG_32BIT)
	sv_type = "sv32";
#elif defined(CONFIG_64BIT)
	if (pgtable_l5_enabled)
		sv_type = "sv57";
	else if (pgtable_l4_enabled)
		sv_type = "sv48";
	else
		sv_type = "sv39";
#endif
#else
	sv_type = "none";
#endif /* CONFIG_MMU */
	seq_printf(f, "mmu\t\t: %s\n", sv_type);
}

static void *c_start(struct seq_file *m, loff_t *pos)
{
	if (*pos == nr_cpu_ids)
		return NULL;

	*pos = cpumask_next(*pos - 1, cpu_online_mask);
	if ((*pos) < nr_cpu_ids)
		return (void *)(uintptr_t)(1 + *pos);
	return NULL;
}

static void *c_next(struct seq_file *m, void *v, loff_t *pos)
{
	(*pos)++;
	return c_start(m, pos);
}

static void c_stop(struct seq_file *m, void *v)
{
}

static int c_show(struct seq_file *m, void *v)
{
	unsigned long cpu_id = (unsigned long)v - 1;
	struct riscv_cpuinfo *ci = per_cpu_ptr(&riscv_cpuinfo, cpu_id);
	struct device_node *node;
	const char *compat;

	seq_printf(m, "processor\t: %lu\n", cpu_id);
	seq_printf(m, "hart\t\t: %lu\n", cpuid_to_hartid_map(cpu_id));

	/*
	 * For historical raisins, the isa: line is limited to the lowest common
	 * denominator of extensions supported across all harts. A true list of
	 * extensions supported on this hart is printed later in the hart isa:
	 * line.
	 */
	seq_puts(m, "isa\t\t: ");
	print_isa(m, NULL, ALL_CPUS);
	print_mmu(m);

	if (acpi_disabled) {
		node = of_get_cpu_node(cpu_id, NULL);

		if (!of_property_read_string(node, "compatible", &compat) &&
		    strcmp(compat, "riscv"))
			seq_printf(m, "uarch\t\t: %s\n", compat);

		of_node_put(node);
	}

	seq_printf(m, "mvendorid\t: 0x%lx\n", ci->mvendorid);
	seq_printf(m, "marchid\t\t: 0x%lx\n", ci->marchid);
	seq_printf(m, "mimpid\t\t: 0x%lx\n", ci->mimpid);

	/*
	 * Print the ISA extensions specific to this hart, which may show
	 * additional extensions not present across all harts.
	 */
	seq_puts(m, "hart isa\t: ");
	print_isa(m, hart_isa[cpu_id].isa, cpu_id);
	seq_puts(m, "\n");

	return 0;
}

const struct seq_operations cpuinfo_op = {
	.start	= c_start,
	.next	= c_next,
	.stop	= c_stop,
	.show	= c_show
};

#endif /* CONFIG_PROC_FS */
Commit	Line	Data
50acfb2b	1	// SPDX-License-Identifier: GPL-2.0-only
76d2a049 PD	2	/*
76d2a049 PD	3	* Copyright (C) 2012 Regents of the University of California
76d2a049 PD	4	*/
76d2a049 PD	5
0b144c81	6	#include <linux/acpi.h>
3baca1a4	7	#include <linux/cpu.h>
255b34d7	8	#include <linux/ctype.h>
76d2a049 PD	9	#include <linux/init.h>
	10	#include <linux/seq_file.h>
	11	#include <linux/of.h>
0b144c81	12	#include <asm/acpi.h>
ff77cf5b	13	#include <asm/cpufeature.h>
3baca1a4	14	#include <asm/csr.h>
a9b20260	15	#include <asm/hwcap.h>
3baca1a4	16	#include <asm/sbi.h>
f99fb607	17	#include <asm/smp.h>
73c7c8f6	18	#include <asm/pgtable.h>
9448d9ac	19	#include <asm/vendor_extensions.h>
76d2a049	20
6514f81e SH	21	bool arch_match_cpu_phys_id(int cpu, u64 phys_id)
	22	{
	23	return phys_id == cpuid_to_hartid_map(cpu);
	24	}
	25
b2f8cfa7	26	/*
149820c6 JH	27	* Returns the hart ID of the given device tree node, or -ENODEV if the node
149820c6 JH	28	* isn't an enabled and valid RISC-V hart node.
b2f8cfa7	29	*/
ad635e72	30	int riscv_of_processor_hartid(struct device_node node, unsigned long hart)
2ac87434 CD	31	{
	32	int cpu;
	33
	34	*hart = (unsigned long)of_get_cpu_hwid(node, 0);
	35	if (*hart == ~0UL) {
	36	pr_warn("Found CPU without hart ID\n");
	37	return -ENODEV;
	38	}
	39
	40	cpu = riscv_hartid_to_cpuid(*hart);
	41	if (cpu < 0)
	42	return cpu;
	43
	44	if (!cpu_possible(cpu))
	45	return -ENODEV;
	46
	47	return 0;
	48	}
	49
496ea826	50	int __init riscv_early_of_processor_hartid(struct device_node node, unsigned long hart)
76d2a049	51	{
e3d794d5	52	const char *isa;
76d2a049 PD	53
	54	if (!of_device_is_compatible(node, "riscv")) {
	55	pr_warn("Found incompatible CPU\n");
149820c6	56	return -ENODEV;
76d2a049 PD	57	}
76d2a049 PD	58
2ac87434	59	*hart = (unsigned long)of_get_cpu_hwid(node, 0);
ad635e72	60	if (*hart == ~0UL) {
76d2a049	61	pr_warn("Found CPU without hart ID\n");
149820c6	62	return -ENODEV;
76d2a049	63	}
76d2a049	64
e3d794d5	65	if (!of_device_is_available(node)) {
ad635e72	66	pr_info("CPU with hartid=%lu is not available\n", *hart);
149820c6	67	return -ENODEV;
76d2a049 PD	68	}
76d2a049 PD	69
c98f136a CD	70	if (of_property_read_string(node, "riscv,isa-base", &isa))
	71	goto old_interface;
	72
	73	if (IS_ENABLED(CONFIG_32BIT) && strncasecmp(isa, "rv32i", 5)) {
	74	pr_warn("CPU with hartid=%lu does not support rv32i", *hart);
	75	return -ENODEV;
	76	}
	77
	78	if (IS_ENABLED(CONFIG_64BIT) && strncasecmp(isa, "rv64i", 5)) {
	79	pr_warn("CPU with hartid=%lu does not support rv64i", *hart);
	80	return -ENODEV;
	81	}
	82
	83	if (!of_property_present(node, "riscv,isa-extensions"))
	84	return -ENODEV;
	85
	86	if (of_property_match_string(node, "riscv,isa-extensions", "i") < 0 \|\|
	87	of_property_match_string(node, "riscv,isa-extensions", "m") < 0 \|\|
	88	of_property_match_string(node, "riscv,isa-extensions", "a") < 0) {
	89	pr_warn("CPU with hartid=%lu does not support ima", *hart);
	90	return -ENODEV;
	91	}
	92
	93	return 0;
	94
	95	old_interface:
496ea826 CD	96	if (!riscv_isa_fallback) {
	97	pr_warn("CPU with hartid=%lu is invalid: this kernel does not parse \"riscv,isa\"",
	98	*hart);
	99	return -ENODEV;
	100	}
	101
76d2a049	102	if (of_property_read_string(node, "riscv,isa", &isa)) {
c98f136a CD	103	pr_warn("CPU with hartid=%lu has no \"riscv,isa-base\" or \"riscv,isa\" property\n",
c98f136a CD	104	*hart);
149820c6	105	return -ENODEV;
76d2a049	106	}
069b0d51	107
23059893 PD	108	if (IS_ENABLED(CONFIG_32BIT) && strncasecmp(isa, "rv32ima", 7)) {
23059893 PD	109	pr_warn("CPU with hartid=%lu does not support rv32ima", *hart);
069b0d51	110	return -ENODEV;
23059893	111	}
069b0d51	112
23059893 PD	113	if (IS_ENABLED(CONFIG_64BIT) && strncasecmp(isa, "rv64ima", 7)) {
23059893 PD	114	pr_warn("CPU with hartid=%lu does not support rv64ima", *hart);
149820c6	115	return -ENODEV;
23059893	116	}
76d2a049	117
ad635e72	118	return 0;
76d2a049 PD	119	}
76d2a049 PD	120
d175d699 AP	121	/*
	122	* Find hart ID of the CPU DT node under which given DT node falls.
	123	*
	124	* To achieve this, we walk up the DT tree until we find an active
	125	* RISC-V core (HART) node and extract the cpuid from it.
	126	*/
ad635e72	127	int riscv_of_parent_hartid(struct device_node node, unsigned long hartid)
d175d699 AP	128	{
d175d699 AP	129	for (; node; node = node->parent) {
ad635e72	130	if (of_device_is_compatible(node, "riscv")) {
c4676f8d AP	131	*hartid = (unsigned long)of_get_cpu_hwid(node, 0);
	132	if (*hartid == ~0UL) {
	133	pr_warn("Found CPU without hart ID\n");
	134	return -ENODEV;
	135	}
	136	return 0;
ad635e72	137	}
d175d699 AP	138	}
	139
	140	return -1;
	141	}
	142
e482eab4 CJ	143	unsigned long __init riscv_get_marchid(void)
	144	{
	145	struct riscv_cpuinfo *ci = this_cpu_ptr(&riscv_cpuinfo);
	146
	147	#if IS_ENABLED(CONFIG_RISCV_SBI)
	148	ci->marchid = sbi_spec_is_0_1() ? 0 : sbi_get_marchid();
	149	#elif IS_ENABLED(CONFIG_RISCV_M_MODE)
	150	ci->marchid = csr_read(CSR_MARCHID);
	151	#else
	152	ci->marchid = 0;
	153	#endif
	154	return ci->marchid;
	155	}
	156
	157	unsigned long __init riscv_get_mvendorid(void)
	158	{
	159	struct riscv_cpuinfo *ci = this_cpu_ptr(&riscv_cpuinfo);
	160
	161	#if IS_ENABLED(CONFIG_RISCV_SBI)
	162	ci->mvendorid = sbi_spec_is_0_1() ? 0 : sbi_get_mvendorid();
	163	#elif IS_ENABLED(CONFIG_RISCV_M_MODE)
	164	ci->mvendorid = csr_read(CSR_MVENDORID);
	165	#else
	166	ci->mvendorid = 0;
	167	#endif
	168	return ci->mvendorid;
	169	}
	170
ff77cf5b	171	DEFINE_PER_CPU(struct riscv_cpuinfo, riscv_cpuinfo);
3baca1a4	172
5e9c68ea HS	173	unsigned long riscv_cached_mvendorid(unsigned int cpu_id)
	174	{
	175	struct riscv_cpuinfo *ci = per_cpu_ptr(&riscv_cpuinfo, cpu_id);
	176
	177	return ci->mvendorid;
	178	}
	179	EXPORT_SYMBOL(riscv_cached_mvendorid);
	180
	181	unsigned long riscv_cached_marchid(unsigned int cpu_id)
	182	{
	183	struct riscv_cpuinfo *ci = per_cpu_ptr(&riscv_cpuinfo, cpu_id);
	184
	185	return ci->marchid;
	186	}
	187	EXPORT_SYMBOL(riscv_cached_marchid);
	188
	189	unsigned long riscv_cached_mimpid(unsigned int cpu_id)
	190	{
	191	struct riscv_cpuinfo *ci = per_cpu_ptr(&riscv_cpuinfo, cpu_id);
	192
	193	return ci->mimpid;
	194	}
	195	EXPORT_SYMBOL(riscv_cached_mimpid);
	196
3baca1a4 AP	197	static int riscv_cpuinfo_starting(unsigned int cpu)
	198	{
	199	struct riscv_cpuinfo *ci = this_cpu_ptr(&riscv_cpuinfo);
	200
	201	#if IS_ENABLED(CONFIG_RISCV_SBI)
e482eab4 CJ	202	if (!ci->mvendorid)
	203	ci->mvendorid = sbi_spec_is_0_1() ? 0 : sbi_get_mvendorid();
	204	if (!ci->marchid)
	205	ci->marchid = sbi_spec_is_0_1() ? 0 : sbi_get_marchid();
3baca1a4 AP	206	ci->mimpid = sbi_spec_is_0_1() ? 0 : sbi_get_mimpid();
3baca1a4 AP	207	#elif IS_ENABLED(CONFIG_RISCV_M_MODE)
e482eab4 CJ	208	if (!ci->mvendorid)
	209	ci->mvendorid = csr_read(CSR_MVENDORID);
	210	if (!ci->marchid)
	211	ci->marchid = csr_read(CSR_MARCHID);
3baca1a4 AP	212	ci->mimpid = csr_read(CSR_MIMPID);
	213	#else
	214	ci->mvendorid = 0;
	215	ci->marchid = 0;
	216	ci->mimpid = 0;
	217	#endif
	218
	219	return 0;
	220	}
	221
	222	static int __init riscv_cpuinfo_init(void)
	223	{
	224	int ret;
	225
	226	ret = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "riscv/cpuinfo:starting",
	227	riscv_cpuinfo_starting, NULL);
	228	if (ret < 0) {
	229	pr_err("cpuinfo: failed to register hotplug callbacks.\n");
	230	return ret;
	231	}
	232
	233	return 0;
	234	}
5e9c68ea HS	235	arch_initcall(riscv_cpuinfo_init);
	236
	237	#ifdef CONFIG_PROC_FS
3baca1a4	238
9448d9ac CJ	239	#define ALL_CPUS -1
	240
	241	static void print_vendor_isa(struct seq_file *f, int cpu)
	242	{
	243	struct riscv_isavendorinfo *vendor_bitmap;
	244	struct riscv_isa_vendor_ext_data_list *ext_list;
	245	const struct riscv_isa_ext_data *ext_data;
	246
	247	for (int i = 0; i < riscv_isa_vendor_ext_list_size; i++) {
	248	ext_list = riscv_isa_vendor_ext_list[i];
	249	ext_data = riscv_isa_vendor_ext_list[i]->ext_data;
	250
	251	if (cpu == ALL_CPUS)
	252	vendor_bitmap = &ext_list->all_harts_isa_bitmap;
	253	else
	254	vendor_bitmap = &ext_list->per_hart_isa_bitmap[cpu];
	255
	256	for (int j = 0; j < ext_list->ext_data_count; j++) {
	257	if (!__riscv_isa_extension_available(vendor_bitmap->isa, ext_data[j].id))
	258	continue;
	259
	260	seq_printf(f, "_%s", ext_data[j].name);
	261	}
	262	}
	263	}
	264
	265	static void print_isa(struct seq_file f, const unsigned long isa_bitmap, int cpu)
a9b20260	266	{
a9b20260	267
67270fb3 HS	268	if (IS_ENABLED(CONFIG_32BIT))
	269	seq_write(f, "rv32", 4);
	270	else
	271	seq_write(f, "rv64", 4);
a9b20260	272
effc122a	273	for (int i = 0; i < riscv_isa_ext_count; i++) {
d3d2cf1a	274	if (!__riscv_isa_extension_available(isa_bitmap, riscv_isa_ext[i].id))
a9b20260	275	continue;
a9b20260	276
effc122a CD	277	/* Only multi-letter extensions are split by underscores */
	278	if (strnlen(riscv_isa_ext[i].name, 2) != 1)
	279	seq_puts(f, "_");
76d2a049	280
effc122a	281	seq_printf(f, "%s", riscv_isa_ext[i].name);
a9b20260	282	}
effc122a	283
9448d9ac CJ	284	print_vendor_isa(f, cpu);
9448d9ac CJ	285
4b26d22f	286	seq_puts(f, "\n");
19ccf29b PD	287	}
19ccf29b PD	288
73c7c8f6	289	static void print_mmu(struct seq_file *f)
19ccf29b	290	{
12d61a1b	291	const char *sv_type;
73c7c8f6	292
8810d7fe	293	#ifdef CONFIG_MMU
19ccf29b	294	#if defined(CONFIG_32BIT)
12d61a1b	295	sv_type = "sv32";
19ccf29b	296	#elif defined(CONFIG_64BIT)
011f09d1	297	if (pgtable_l5_enabled)
12d61a1b	298	sv_type = "sv57";
011f09d1	299	else if (pgtable_l4_enabled)
12d61a1b	300	sv_type = "sv48";
73c7c8f6	301	else
12d61a1b	302	sv_type = "sv39";
19ccf29b	303	#endif
8810d7fe	304	#else
12d61a1b	305	sv_type = "none";
8810d7fe	306	#endif /* CONFIG_MMU */
73c7c8f6	307	seq_printf(f, "mmu\t\t: %s\n", sv_type);
19ccf29b PD	308	}
19ccf29b PD	309
76d2a049 PD	310	static void c_start(struct seq_file m, loff_t *pos)
76d2a049 PD	311	{
d14e99bf AJ	312	if (*pos == nr_cpu_ids)
	313	return NULL;
	314
76d2a049 PD	315	pos = cpumask_next(pos - 1, cpu_online_mask);
	316	if ((*pos) < nr_cpu_ids)
	317	return (void )(uintptr_t)(1 + pos);
	318	return NULL;
	319	}
	320
	321	static void c_next(struct seq_file m, void v, loff_t pos)
	322	{
	323	(*pos)++;
	324	return c_start(m, pos);
	325	}
	326
	327	static void c_stop(struct seq_file m, void v)
	328	{
	329	}
	330
	331	static int c_show(struct seq_file m, void v)
	332	{
f99fb607	333	unsigned long cpu_id = (unsigned long)v - 1;
3baca1a4	334	struct riscv_cpuinfo *ci = per_cpu_ptr(&riscv_cpuinfo, cpu_id);
0b144c81	335	struct device_node *node;
67270fb3	336	const char *compat;
76d2a049	337
4b26d22f AP	338	seq_printf(m, "processor\t: %lu\n", cpu_id);
4b26d22f AP	339	seq_printf(m, "hart\t\t: %lu\n", cpuid_to_hartid_map(cpu_id));
d3d2cf1a EG	340
	341	/*
	342	* For historical raisins, the isa: line is limited to the lowest common
	343	* denominator of extensions supported across all harts. A true list of
	344	* extensions supported on this hart is printed later in the hart isa:
	345	* line.
	346	*/
	347	seq_puts(m, "isa\t\t: ");
9448d9ac	348	print_isa(m, NULL, ALL_CPUS);
67270fb3	349	print_mmu(m);
0b144c81 S	350
	351	if (acpi_disabled) {
	352	node = of_get_cpu_node(cpu_id, NULL);
0b144c81	353
0b144c81 S	354	if (!of_property_read_string(node, "compatible", &compat) &&
	355	strcmp(compat, "riscv"))
	356	seq_printf(m, "uarch\t\t: %s\n", compat);
	357
	358	of_node_put(node);
0b144c81 S	359	}
0b144c81 S	360
3baca1a4 AP	361	seq_printf(m, "mvendorid\t: 0x%lx\n", ci->mvendorid);
	362	seq_printf(m, "marchid\t\t: 0x%lx\n", ci->marchid);
	363	seq_printf(m, "mimpid\t\t: 0x%lx\n", ci->mimpid);
d3d2cf1a EG	364
	365	/*
	366	* Print the ISA extensions specific to this hart, which may show
	367	* additional extensions not present across all harts.
	368	*/
	369	seq_puts(m, "hart isa\t: ");
9448d9ac	370	print_isa(m, hart_isa[cpu_id].isa, cpu_id);
76d2a049 PD	371	seq_puts(m, "\n");
	372
	373	return 0;
	374	}
	375
	376	const struct seq_operations cpuinfo_op = {
	377	.start = c_start,
	378	.next = c_next,
	379	.stop = c_stop,
	380	.show = c_show
	381	};
	382
	383	#endif /* CONFIG_PROC_FS */