[linux-2.6-block.git] / arch / riscv / include / asm / hwcap.h

/* SPDX-License-Identifier: GPL-2.0-only */
/*
 * Copied from arch/arm64/include/asm/hwcap.h
 *
 * Copyright (C) 2012 ARM Ltd.
 * Copyright (C) 2017 SiFive
 */
#ifndef _ASM_RISCV_HWCAP_H
#define _ASM_RISCV_HWCAP_H

#include <uapi/asm/hwcap.h>

#define RISCV_ISA_EXT_a		('a' - 'a')
#define RISCV_ISA_EXT_c		('c' - 'a')
#define RISCV_ISA_EXT_d		('d' - 'a')
#define RISCV_ISA_EXT_f		('f' - 'a')
#define RISCV_ISA_EXT_h		('h' - 'a')
#define RISCV_ISA_EXT_i		('i' - 'a')
#define RISCV_ISA_EXT_m		('m' - 'a')
#define RISCV_ISA_EXT_q		('q' - 'a')
#define RISCV_ISA_EXT_v		('v' - 'a')

/*
 * These macros represent the logical IDs of each multi-letter RISC-V ISA
 * extension and are used in the ISA bitmap. The logical IDs start from
 * RISCV_ISA_EXT_BASE, which allows the 0-25 range to be reserved for single
 * letter extensions. The maximum, RISCV_ISA_EXT_MAX, is defined in order
 * to allocate the bitmap and may be increased when necessary.
 *
 * New extensions should just be added to the bottom, rather than added
 * alphabetically, in order to avoid unnecessary shuffling.
 */
#define RISCV_ISA_EXT_BASE		26

#define RISCV_ISA_EXT_SSCOFPMF		26
#define RISCV_ISA_EXT_SSTC		27
#define RISCV_ISA_EXT_SVINVAL		28
#define RISCV_ISA_EXT_SVPBMT		29
#define RISCV_ISA_EXT_ZBB		30
#define RISCV_ISA_EXT_ZICBOM		31
#define RISCV_ISA_EXT_ZIHINTPAUSE	32
#define RISCV_ISA_EXT_SVNAPOT		33
#define RISCV_ISA_EXT_ZICBOZ		34
#define RISCV_ISA_EXT_SMAIA		35
#define RISCV_ISA_EXT_SSAIA		36
#define RISCV_ISA_EXT_ZBA		37
#define RISCV_ISA_EXT_ZBS		38
#define RISCV_ISA_EXT_ZICNTR		39
#define RISCV_ISA_EXT_ZICSR		40
#define RISCV_ISA_EXT_ZIFENCEI		41
#define RISCV_ISA_EXT_ZIHPM		42
#define RISCV_ISA_EXT_SMSTATEEN		43
#define RISCV_ISA_EXT_ZICOND		44
#define RISCV_ISA_EXT_ZBC		45
#define RISCV_ISA_EXT_ZBKB		46
#define RISCV_ISA_EXT_ZBKC		47
#define RISCV_ISA_EXT_ZBKX		48
#define RISCV_ISA_EXT_ZKND		49
#define RISCV_ISA_EXT_ZKNE		50
#define RISCV_ISA_EXT_ZKNH		51
#define RISCV_ISA_EXT_ZKR		52
#define RISCV_ISA_EXT_ZKSED		53
#define RISCV_ISA_EXT_ZKSH		54
#define RISCV_ISA_EXT_ZKT		55
#define RISCV_ISA_EXT_ZVBB		56
#define RISCV_ISA_EXT_ZVBC		57
#define RISCV_ISA_EXT_ZVKB		58
#define RISCV_ISA_EXT_ZVKG		59
#define RISCV_ISA_EXT_ZVKNED		60
#define RISCV_ISA_EXT_ZVKNHA		61
#define RISCV_ISA_EXT_ZVKNHB		62
#define RISCV_ISA_EXT_ZVKSED		63
#define RISCV_ISA_EXT_ZVKSH		64
#define RISCV_ISA_EXT_ZVKT		65
#define RISCV_ISA_EXT_ZFH		66
#define RISCV_ISA_EXT_ZFHMIN		67
#define RISCV_ISA_EXT_ZIHINTNTL		68
#define RISCV_ISA_EXT_ZVFH		69
#define RISCV_ISA_EXT_ZVFHMIN		70
#define RISCV_ISA_EXT_ZFA		71
#define RISCV_ISA_EXT_ZTSO		72
#define RISCV_ISA_EXT_ZACAS		73

#define RISCV_ISA_EXT_XLINUXENVCFG	127

#define RISCV_ISA_EXT_MAX		128
#define RISCV_ISA_EXT_INVALID		U32_MAX

#ifdef CONFIG_RISCV_M_MODE
#define RISCV_ISA_EXT_SxAIA		RISCV_ISA_EXT_SMAIA
#else
#define RISCV_ISA_EXT_SxAIA		RISCV_ISA_EXT_SSAIA
#endif

#endif /* _ASM_RISCV_HWCAP_H */
Commit	Line	Data
caab277b	1	/* SPDX-License-Identifier: GPL-2.0-only */
2129a235 PD	2	/*
	3	* Copied from arch/arm64/include/asm/hwcap.h
	4	*
	5	* Copyright (C) 2012 ARM Ltd.
	6	* Copyright (C) 2017 SiFive
2129a235	7	*/
6b57ba8e ZL	8	#ifndef _ASM_RISCV_HWCAP_H
6b57ba8e ZL	9	#define _ASM_RISCV_HWCAP_H
2129a235 PD	10
	11	#include <uapi/asm/hwcap.h>
	12
6bcff515 AP	13	#define RISCV_ISA_EXT_a ('a' - 'a')
	14	#define RISCV_ISA_EXT_c ('c' - 'a')
	15	#define RISCV_ISA_EXT_d ('d' - 'a')
	16	#define RISCV_ISA_EXT_f ('f' - 'a')
	17	#define RISCV_ISA_EXT_h ('h' - 'a')
	18	#define RISCV_ISA_EXT_i ('i' - 'a')
	19	#define RISCV_ISA_EXT_m ('m' - 'a')
c30556e3	20	#define RISCV_ISA_EXT_q ('q' - 'a')
dc6667a4	21	#define RISCV_ISA_EXT_v ('v' - 'a')
6bcff515	22
02d52fbd	23	/*
dac8bf14 AJ	24	* These macros represent the logical IDs of each multi-letter RISC-V ISA
	25	* extension and are used in the ISA bitmap. The logical IDs start from
	26	* RISCV_ISA_EXT_BASE, which allows the 0-25 range to be reserved for single
	27	* letter extensions. The maximum, RISCV_ISA_EXT_MAX, is defined in order
	28	* to allocate the bitmap and may be increased when necessary.
	29	*
	30	* New extensions should just be added to the bottom, rather than added
	31	* alphabetically, in order to avoid unnecessary shuffling.
02d52fbd	32	*/
dac8bf14	33	#define RISCV_ISA_EXT_BASE 26
02d52fbd	34
dac8bf14 AJ	35	#define RISCV_ISA_EXT_SSCOFPMF 26
	36	#define RISCV_ISA_EXT_SSTC 27
	37	#define RISCV_ISA_EXT_SVINVAL 28
	38	#define RISCV_ISA_EXT_SVPBMT 29
	39	#define RISCV_ISA_EXT_ZBB 30
	40	#define RISCV_ISA_EXT_ZICBOM 31
	41	#define RISCV_ISA_EXT_ZIHINTPAUSE 32
4a4c4598	42	#define RISCV_ISA_EXT_SVNAPOT 33
4b740779	43	#define RISCV_ISA_EXT_ZICBOZ 34
d4fba4df PB	44	#define RISCV_ISA_EXT_SMAIA 35
d4fba4df PB	45	#define RISCV_ISA_EXT_SSAIA 36
c6699baf EG	46	#define RISCV_ISA_EXT_ZBA 37
c6699baf EG	47	#define RISCV_ISA_EXT_ZBS 38
42b89447 PD	48	#define RISCV_ISA_EXT_ZICNTR 39
	49	#define RISCV_ISA_EXT_ZICSR 40
	50	#define RISCV_ISA_EXT_ZIFENCEI 41
	51	#define RISCV_ISA_EXT_ZIHPM 42
9dbaf381	52	#define RISCV_ISA_EXT_SMSTATEEN 43
662a601a	53	#define RISCV_ISA_EXT_ZICOND 44
e45f463a	54	#define RISCV_ISA_EXT_ZBC 45
0d8295ed EG	55	#define RISCV_ISA_EXT_ZBKB 46
	56	#define RISCV_ISA_EXT_ZBKC 47
	57	#define RISCV_ISA_EXT_ZBKX 48
	58	#define RISCV_ISA_EXT_ZKND 49
	59	#define RISCV_ISA_EXT_ZKNE 50
	60	#define RISCV_ISA_EXT_ZKNH 51
	61	#define RISCV_ISA_EXT_ZKR 52
	62	#define RISCV_ISA_EXT_ZKSED 53
	63	#define RISCV_ISA_EXT_ZKSH 54
	64	#define RISCV_ISA_EXT_ZKT 55
aec33539 CL	65	#define RISCV_ISA_EXT_ZVBB 56
	66	#define RISCV_ISA_EXT_ZVBC 57
	67	#define RISCV_ISA_EXT_ZVKB 58
	68	#define RISCV_ISA_EXT_ZVKG 59
	69	#define RISCV_ISA_EXT_ZVKNED 60
	70	#define RISCV_ISA_EXT_ZVKNHA 61
	71	#define RISCV_ISA_EXT_ZVKNHB 62
	72	#define RISCV_ISA_EXT_ZVKSED 63
	73	#define RISCV_ISA_EXT_ZVKSH 64
	74	#define RISCV_ISA_EXT_ZVKT 65
11e8e1ee CL	75	#define RISCV_ISA_EXT_ZFH 66
11e8e1ee CL	76	#define RISCV_ISA_EXT_ZFHMIN 67
eddbfa0d	77	#define RISCV_ISA_EXT_ZIHINTNTL 68
f4961b78 CL	78	#define RISCV_ISA_EXT_ZVFH 69
f4961b78 CL	79	#define RISCV_ISA_EXT_ZVFHMIN 70
fe987e84	80	#define RISCV_ISA_EXT_ZFA 71
1ec9f381	81	#define RISCV_ISA_EXT_ZTSO 72
188a2122	82	#define RISCV_ISA_EXT_ZACAS 73
02d52fbd	83
4774848f SH	84	#define RISCV_ISA_EXT_XLINUXENVCFG 127
4774848f SH	85
aec33539	86	#define RISCV_ISA_EXT_MAX 128
0d8295ed	87	#define RISCV_ISA_EXT_INVALID U32_MAX
6bcff515	88
54e43320 AP	89	#ifdef CONFIG_RISCV_M_MODE
	90	#define RISCV_ISA_EXT_SxAIA RISCV_ISA_EXT_SMAIA
	91	#else
	92	#define RISCV_ISA_EXT_SxAIA RISCV_ISA_EXT_SSAIA
	93	#endif
	94
6b57ba8e	95	#endif /* _ASM_RISCV_HWCAP_H */