[linux-block.git] / arch / riscv / include / asm / errata_list.h

/* SPDX-License-Identifier: GPL-2.0-only */
/*
 * Copyright (C) 2021 Sifive.
 */
#ifndef ASM_ERRATA_LIST_H
#define ASM_ERRATA_LIST_H

#include <asm/alternative.h>
#include <asm/csr.h>
#include <asm/insn-def.h>
#include <asm/hwcap.h>
#include <asm/vendorid_list.h>

#ifdef CONFIG_ERRATA_ANDES
#define ERRATA_ANDESTECH_NO_IOCP	0
#define ERRATA_ANDESTECH_NUMBER		1
#endif

#ifdef CONFIG_ERRATA_SIFIVE
#define	ERRATA_SIFIVE_CIP_453 0
#define	ERRATA_SIFIVE_CIP_1200 1
#define	ERRATA_SIFIVE_NUMBER 2
#endif

#ifdef CONFIG_ERRATA_THEAD
#define	ERRATA_THEAD_PBMT 0
#define	ERRATA_THEAD_CMO 1
#define	ERRATA_THEAD_PMU 2
#define	ERRATA_THEAD_NUMBER 3
#endif

#ifdef __ASSEMBLY__

#define ALT_INSN_FAULT(x)						\
ALTERNATIVE(__stringify(RISCV_PTR do_trap_insn_fault),			\
	    __stringify(RISCV_PTR sifive_cip_453_insn_fault_trp),	\
	    SIFIVE_VENDOR_ID, ERRATA_SIFIVE_CIP_453,			\
	    CONFIG_ERRATA_SIFIVE_CIP_453)

#define ALT_PAGE_FAULT(x)						\
ALTERNATIVE(__stringify(RISCV_PTR do_page_fault),			\
	    __stringify(RISCV_PTR sifive_cip_453_page_fault_trp),	\
	    SIFIVE_VENDOR_ID, ERRATA_SIFIVE_CIP_453,			\
	    CONFIG_ERRATA_SIFIVE_CIP_453)
#else /* !__ASSEMBLY__ */

#define ALT_FLUSH_TLB_PAGE(x)						\
asm(ALTERNATIVE("sfence.vma %0", "sfence.vma", SIFIVE_VENDOR_ID,	\
		ERRATA_SIFIVE_CIP_1200, CONFIG_ERRATA_SIFIVE_CIP_1200)	\
		: : "r" (addr) : "memory")

/*
 * _val is marked as "will be overwritten", so need to set it to 0
 * in the default case.
 */
#define ALT_SVPBMT_SHIFT 61
#define ALT_THEAD_PBMT_SHIFT 59
#define ALT_SVPBMT(_val, prot)						\
asm(ALTERNATIVE_2("li %0, 0\t\nnop",					\
		  "li %0, %1\t\nslli %0,%0,%3", 0,			\
			RISCV_ISA_EXT_SVPBMT, CONFIG_RISCV_ISA_SVPBMT,	\
		  "li %0, %2\t\nslli %0,%0,%4", THEAD_VENDOR_ID,	\
			ERRATA_THEAD_PBMT, CONFIG_ERRATA_THEAD_PBMT)	\
		: "=r"(_val)						\
		: "I"(prot##_SVPBMT >> ALT_SVPBMT_SHIFT),		\
		  "I"(prot##_THEAD >> ALT_THEAD_PBMT_SHIFT),		\
		  "I"(ALT_SVPBMT_SHIFT),				\
		  "I"(ALT_THEAD_PBMT_SHIFT))

#ifdef CONFIG_ERRATA_THEAD_PBMT
/*
 * IO/NOCACHE memory types are handled together with svpbmt,
 * so on T-Head chips, check if no other memory type is set,
 * and set the non-0 PMA type if applicable.
 */
#define ALT_THEAD_PMA(_val)						\
asm volatile(ALTERNATIVE(						\
	__nops(7),							\
	"li      t3, %1\n\t"						\
	"slli    t3, t3, %3\n\t"					\
	"and     t3, %0, t3\n\t"					\
	"bne     t3, zero, 2f\n\t"					\
	"li      t3, %2\n\t"						\
	"slli    t3, t3, %3\n\t"					\
	"or      %0, %0, t3\n\t"					\
	"2:",  THEAD_VENDOR_ID,						\
		ERRATA_THEAD_PBMT, CONFIG_ERRATA_THEAD_PBMT)		\
	: "+r"(_val)							\
	: "I"(_PAGE_MTMASK_THEAD >> ALT_THEAD_PBMT_SHIFT),		\
	  "I"(_PAGE_PMA_THEAD >> ALT_THEAD_PBMT_SHIFT),			\
	  "I"(ALT_THEAD_PBMT_SHIFT)					\
	: "t3")
#else
#define ALT_THEAD_PMA(_val)
#endif

/*
 * dcache.ipa rs1 (invalidate, physical address)
 * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 |
 *   0000001    01010      rs1       000      00000  0001011
 * dache.iva rs1 (invalida, virtual address)
 *   0000001    00110      rs1       000      00000  0001011
 *
 * dcache.cpa rs1 (clean, physical address)
 * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 |
 *   0000001    01001      rs1       000      00000  0001011
 * dcache.cva rs1 (clean, virtual address)
 *   0000001    00101      rs1       000      00000  0001011
 *
 * dcache.cipa rs1 (clean then invalidate, physical address)
 * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 |
 *   0000001    01011      rs1       000      00000  0001011
 * dcache.civa rs1 (... virtual address)
 *   0000001    00111      rs1       000      00000  0001011
 *
 * sync.s (make sure all cache operations finished)
 * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 |
 *   0000000    11001     00000      000      00000  0001011
 */
#define THEAD_inval_A0	".long 0x0265000b"
#define THEAD_clean_A0	".long 0x0255000b"
#define THEAD_flush_A0	".long 0x0275000b"
#define THEAD_SYNC_S	".long 0x0190000b"

#define ALT_CMO_OP(_op, _start, _size, _cachesize)			\
asm volatile(ALTERNATIVE_2(						\
	__nops(6),							\
	"mv a0, %1\n\t"							\
	"j 2f\n\t"							\
	"3:\n\t"							\
	CBO_##_op(a0)							\
	"add a0, a0, %0\n\t"						\
	"2:\n\t"							\
	"bltu a0, %2, 3b\n\t"						\
	"nop", 0, RISCV_ISA_EXT_ZICBOM, CONFIG_RISCV_ISA_ZICBOM,	\
	"mv a0, %1\n\t"							\
	"j 2f\n\t"							\
	"3:\n\t"							\
	THEAD_##_op##_A0 "\n\t"						\
	"add a0, a0, %0\n\t"						\
	"2:\n\t"							\
	"bltu a0, %2, 3b\n\t"						\
	THEAD_SYNC_S, THEAD_VENDOR_ID,					\
			ERRATA_THEAD_CMO, CONFIG_ERRATA_THEAD_CMO)	\
	: : "r"(_cachesize),						\
	    "r"((unsigned long)(_start) & ~((_cachesize) - 1UL)),	\
	    "r"((unsigned long)(_start) + (_size))			\
	: "a0")

#define THEAD_C9XX_RV_IRQ_PMU			17
#define THEAD_C9XX_CSR_SCOUNTEROF		0x5c5

#define ALT_SBI_PMU_OVERFLOW(__ovl)					\
asm volatile(ALTERNATIVE(						\
	"csrr %0, " __stringify(CSR_SSCOUNTOVF),			\
	"csrr %0, " __stringify(THEAD_C9XX_CSR_SCOUNTEROF),		\
		THEAD_VENDOR_ID, ERRATA_THEAD_PMU,			\
		CONFIG_ERRATA_THEAD_PMU)				\
	: "=r" (__ovl) :						\
	: "memory")

#endif /* __ASSEMBLY__ */

#endif
Commit	Line	Data
6f4eea90 VC	1	/* SPDX-License-Identifier: GPL-2.0-only */
	2	/*
	3	* Copyright (C) 2021 Sifive.
	4	*/
	5	#ifndef ASM_ERRATA_LIST_H
	6	#define ASM_ERRATA_LIST_H
	7
800149a7	8	#include <asm/alternative.h>
65e9fb08	9	#include <asm/csr.h>
dd23e953	10	#include <asm/insn-def.h>
4bf88607	11	#include <asm/hwcap.h>
800149a7 VC	12	#include <asm/vendorid_list.h>
800149a7 VC	13
e021ae7f LP	14	#ifdef CONFIG_ERRATA_ANDES
	15	#define ERRATA_ANDESTECH_NO_IOCP 0
	16	#define ERRATA_ANDESTECH_NUMBER 1
	17	#endif
	18
6f4eea90	19	#ifdef CONFIG_ERRATA_SIFIVE
800149a7	20	#define ERRATA_SIFIVE_CIP_453 0
bff3ff52 VC	21	#define ERRATA_SIFIVE_CIP_1200 1
bff3ff52 VC	22	#define ERRATA_SIFIVE_NUMBER 2
6f4eea90 VC	23	#endif
6f4eea90 VC	24
a35707c3 HS	25	#ifdef CONFIG_ERRATA_THEAD
a35707c3 HS	26	#define ERRATA_THEAD_PBMT 0
d20ec752	27	#define ERRATA_THEAD_CMO 1
65e9fb08 HS	28	#define ERRATA_THEAD_PMU 2
65e9fb08 HS	29	#define ERRATA_THEAD_NUMBER 3
a35707c3 HS	30	#endif
a35707c3 HS	31
800149a7 VC	32	#ifdef __ASSEMBLY__
	33
	34	#define ALT_INSN_FAULT(x) \
	35	ALTERNATIVE(__stringify(RISCV_PTR do_trap_insn_fault), \
	36	__stringify(RISCV_PTR sifive_cip_453_insn_fault_trp), \
	37	SIFIVE_VENDOR_ID, ERRATA_SIFIVE_CIP_453, \
	38	CONFIG_ERRATA_SIFIVE_CIP_453)
	39
	40	#define ALT_PAGE_FAULT(x) \
	41	ALTERNATIVE(__stringify(RISCV_PTR do_page_fault), \
	42	__stringify(RISCV_PTR sifive_cip_453_page_fault_trp), \
	43	SIFIVE_VENDOR_ID, ERRATA_SIFIVE_CIP_453, \
	44	CONFIG_ERRATA_SIFIVE_CIP_453)
bff3ff52 VC	45	#else /* !__ASSEMBLY__ */
	46
	47	#define ALT_FLUSH_TLB_PAGE(x) \
	48	asm(ALTERNATIVE("sfence.vma %0", "sfence.vma", SIFIVE_VENDOR_ID, \
	49	ERRATA_SIFIVE_CIP_1200, CONFIG_ERRATA_SIFIVE_CIP_1200) \
	50	: : "r" (addr) : "memory")
	51
ff689fd2 HS	52	/*
	53	* _val is marked as "will be overwritten", so need to set it to 0
	54	* in the default case.
	55	*/
	56	#define ALT_SVPBMT_SHIFT 61
a35707c3	57	#define ALT_THEAD_PBMT_SHIFT 59
ff689fd2	58	#define ALT_SVPBMT(_val, prot) \
a35707c3 HS	59	asm(ALTERNATIVE_2("li %0, 0\t\nnop", \
a35707c3 HS	60	"li %0, %1\t\nslli %0,%0,%3", 0, \
4bf88607	61	RISCV_ISA_EXT_SVPBMT, CONFIG_RISCV_ISA_SVPBMT, \
a35707c3 HS	62	"li %0, %2\t\nslli %0,%0,%4", THEAD_VENDOR_ID, \
a35707c3 HS	63	ERRATA_THEAD_PBMT, CONFIG_ERRATA_THEAD_PBMT) \
ff689fd2 HS	64	: "=r"(_val) \
ff689fd2 HS	65	: "I"(prot##_SVPBMT >> ALT_SVPBMT_SHIFT), \
a35707c3 HS	66	"I"(prot##_THEAD >> ALT_THEAD_PBMT_SHIFT), \
	67	"I"(ALT_SVPBMT_SHIFT), \
	68	"I"(ALT_THEAD_PBMT_SHIFT))
	69
	70	#ifdef CONFIG_ERRATA_THEAD_PBMT
	71	/*
	72	* IO/NOCACHE memory types are handled together with svpbmt,
	73	* so on T-Head chips, check if no other memory type is set,
	74	* and set the non-0 PMA type if applicable.
	75	*/
	76	#define ALT_THEAD_PMA(_val) \
	77	asm volatile(ALTERNATIVE( \
9c2ea4a3	78	__nops(7), \
e8303156 NC	79	"li t3, %1\n\t" \
e8303156 NC	80	"slli t3, t3, %3\n\t" \
a35707c3 HS	81	"and t3, %0, t3\n\t" \
a35707c3 HS	82	"bne t3, zero, 2f\n\t" \
e8303156 NC	83	"li t3, %2\n\t" \
e8303156 NC	84	"slli t3, t3, %3\n\t" \
a35707c3 HS	85	"or %0, %0, t3\n\t" \
	86	"2:", THEAD_VENDOR_ID, \
	87	ERRATA_THEAD_PBMT, CONFIG_ERRATA_THEAD_PBMT) \
	88	: "+r"(_val) \
e8303156	89	: "I"(_PAGE_MTMASK_THEAD >> ALT_THEAD_PBMT_SHIFT), \
a35707c3	90	"I"(_PAGE_PMA_THEAD >> ALT_THEAD_PBMT_SHIFT), \
e8303156 NC	91	"I"(ALT_THEAD_PBMT_SHIFT) \
e8303156 NC	92	: "t3")
a35707c3 HS	93	#else
	94	#define ALT_THEAD_PMA(_val)
	95	#endif
ff689fd2	96
d20ec752 HS	97	/*
	98	* dcache.ipa rs1 (invalidate, physical address)
	99	* \| 31 - 25 \| 24 - 20 \| 19 - 15 \| 14 - 12 \| 11 - 7 \| 6 - 0 \|
	100	* 0000001 01010 rs1 000 00000 0001011
	101	* dache.iva rs1 (invalida, virtual address)
	102	* 0000001 00110 rs1 000 00000 0001011
	103	*
	104	* dcache.cpa rs1 (clean, physical address)
	105	* \| 31 - 25 \| 24 - 20 \| 19 - 15 \| 14 - 12 \| 11 - 7 \| 6 - 0 \|
	106	* 0000001 01001 rs1 000 00000 0001011
	107	* dcache.cva rs1 (clean, virtual address)
8eb8fe67	108	* 0000001 00101 rs1 000 00000 0001011
d20ec752 HS	109	*
	110	* dcache.cipa rs1 (clean then invalidate, physical address)
	111	* \| 31 - 25 \| 24 - 20 \| 19 - 15 \| 14 - 12 \| 11 - 7 \| 6 - 0 \|
	112	* 0000001 01011 rs1 000 00000 0001011
	113	* dcache.civa rs1 (... virtual address)
	114	* 0000001 00111 rs1 000 00000 0001011
	115	*
	116	* sync.s (make sure all cache operations finished)
	117	* \| 31 - 25 \| 24 - 20 \| 19 - 15 \| 14 - 12 \| 11 - 7 \| 6 - 0 \|
	118	* 0000000 11001 00000 000 00000 0001011
	119	*/
	120	#define THEAD_inval_A0 ".long 0x0265000b"
8eb8fe67	121	#define THEAD_clean_A0 ".long 0x0255000b"
d20ec752 HS	122	#define THEAD_flush_A0 ".long 0x0275000b"
	123	#define THEAD_SYNC_S ".long 0x0190000b"
	124
1631ba12	125	#define ALT_CMO_OP(_op, _start, _size, _cachesize) \
d20ec752 HS	126	asm volatile(ALTERNATIVE_2( \
d20ec752 HS	127	__nops(6), \
1631ba12 HS	128	"mv a0, %1\n\t" \
	129	"j 2f\n\t" \
	130	"3:\n\t" \
dd23e953	131	CBO_##_op(a0) \
1631ba12 HS	132	"add a0, a0, %0\n\t" \
1631ba12 HS	133	"2:\n\t" \
d20ec752	134	"bltu a0, %2, 3b\n\t" \
4bf88607	135	"nop", 0, RISCV_ISA_EXT_ZICBOM, CONFIG_RISCV_ISA_ZICBOM, \
d20ec752 HS	136	"mv a0, %1\n\t" \
	137	"j 2f\n\t" \
	138	"3:\n\t" \
	139	THEAD_##_op##_A0 "\n\t" \
	140	"add a0, a0, %0\n\t" \
	141	"2:\n\t" \
	142	"bltu a0, %2, 3b\n\t" \
	143	THEAD_SYNC_S, THEAD_VENDOR_ID, \
	144	ERRATA_THEAD_CMO, CONFIG_ERRATA_THEAD_CMO) \
1631ba12 HS	145	: : "r"(_cachesize), \
	146	"r"((unsigned long)(_start) & ~((_cachesize) - 1UL)), \
	147	"r"((unsigned long)(_start) + (_size)) \
	148	: "a0")
	149
65e9fb08 HS	150	#define THEAD_C9XX_RV_IRQ_PMU 17
	151	#define THEAD_C9XX_CSR_SCOUNTEROF 0x5c5
	152
	153	#define ALT_SBI_PMU_OVERFLOW(__ovl) \
	154	asm volatile(ALTERNATIVE( \
	155	"csrr %0, " __stringify(CSR_SSCOUNTOVF), \
	156	"csrr %0, " __stringify(THEAD_C9XX_CSR_SCOUNTEROF), \
	157	THEAD_VENDOR_ID, ERRATA_THEAD_PMU, \
	158	CONFIG_ERRATA_THEAD_PMU) \
	159	: "=r" (__ovl) : \
	160	: "memory")
	161
800149a7 VC	162	#endif /* __ASSEMBLY__ */
800149a7 VC	163
6f4eea90	164	#endif