Commit | Line | Data |
---|---|---|
50acfb2b | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
5d8544e2 PD |
2 | /* |
3 | * Copyright (C) 2015 Regents of the University of California | |
5d8544e2 PD |
4 | */ |
5 | ||
6 | #ifndef _ASM_RISCV_CSR_H | |
7 | #define _ASM_RISCV_CSR_H | |
8 | ||
a3182c91 | 9 | #include <asm/asm.h> |
5d8544e2 PD |
10 | #include <linux/const.h> |
11 | ||
12 | /* Status register flags */ | |
196a14d4 | 13 | #define SR_SIE _AC(0x00000002, UL) /* Supervisor Interrupt Enable */ |
a4c3733d | 14 | #define SR_MIE _AC(0x00000008, UL) /* Machine Interrupt Enable */ |
196a14d4 | 15 | #define SR_SPIE _AC(0x00000020, UL) /* Previous Supervisor IE */ |
a4c3733d | 16 | #define SR_MPIE _AC(0x00000080, UL) /* Previous Machine IE */ |
196a14d4 | 17 | #define SR_SPP _AC(0x00000100, UL) /* Previously Supervisor */ |
a4c3733d | 18 | #define SR_MPP _AC(0x00001800, UL) /* Previously Machine */ |
196a14d4 | 19 | #define SR_SUM _AC(0x00040000, UL) /* Supervisor User Memory Access */ |
5d8544e2 | 20 | |
196a14d4 AP |
21 | #define SR_FS _AC(0x00006000, UL) /* Floating-point Status */ |
22 | #define SR_FS_OFF _AC(0x00000000, UL) | |
23 | #define SR_FS_INITIAL _AC(0x00002000, UL) | |
24 | #define SR_FS_CLEAN _AC(0x00004000, UL) | |
25 | #define SR_FS_DIRTY _AC(0x00006000, UL) | |
5d8544e2 | 26 | |
196a14d4 AP |
27 | #define SR_XS _AC(0x00018000, UL) /* Extension Status */ |
28 | #define SR_XS_OFF _AC(0x00000000, UL) | |
29 | #define SR_XS_INITIAL _AC(0x00008000, UL) | |
30 | #define SR_XS_CLEAN _AC(0x00010000, UL) | |
31 | #define SR_XS_DIRTY _AC(0x00018000, UL) | |
5d8544e2 PD |
32 | |
33 | #ifndef CONFIG_64BIT | |
196a14d4 | 34 | #define SR_SD _AC(0x80000000, UL) /* FS/XS dirty */ |
5d8544e2 | 35 | #else |
196a14d4 | 36 | #define SR_SD _AC(0x8000000000000000, UL) /* FS/XS dirty */ |
5d8544e2 PD |
37 | #endif |
38 | ||
7549cdf5 | 39 | /* SATP flags */ |
196a14d4 AP |
40 | #ifndef CONFIG_64BIT |
41 | #define SATP_PPN _AC(0x003FFFFF, UL) | |
42 | #define SATP_MODE_32 _AC(0x80000000, UL) | |
43 | #define SATP_MODE SATP_MODE_32 | |
5d8544e2 | 44 | #else |
196a14d4 AP |
45 | #define SATP_PPN _AC(0x00000FFFFFFFFFFF, UL) |
46 | #define SATP_MODE_39 _AC(0x8000000000000000, UL) | |
47 | #define SATP_MODE SATP_MODE_39 | |
5d8544e2 PD |
48 | #endif |
49 | ||
a4c3733d CH |
50 | /* Exception cause high bit - is an interrupt if set */ |
51 | #define CAUSE_IRQ_FLAG (_AC(1, UL) << (__riscv_xlen - 1)) | |
6dcaf004 | 52 | |
a4c3733d | 53 | /* Interrupt causes (minus the high bit) */ |
6dcaf004 AP |
54 | #define IRQ_U_SOFT 0 |
55 | #define IRQ_S_SOFT 1 | |
56 | #define IRQ_M_SOFT 3 | |
57 | #define IRQ_U_TIMER 4 | |
58 | #define IRQ_S_TIMER 5 | |
59 | #define IRQ_M_TIMER 7 | |
60 | #define IRQ_U_EXT 8 | |
61 | #define IRQ_S_EXT 9 | |
62 | #define IRQ_M_EXT 11 | |
5d8544e2 | 63 | |
a4c3733d | 64 | /* Exception causes */ |
196a14d4 AP |
65 | #define EXC_INST_MISALIGNED 0 |
66 | #define EXC_INST_ACCESS 1 | |
67 | #define EXC_BREAKPOINT 3 | |
68 | #define EXC_LOAD_ACCESS 5 | |
69 | #define EXC_STORE_ACCESS 7 | |
70 | #define EXC_SYSCALL 8 | |
71 | #define EXC_INST_PAGE_FAULT 12 | |
72 | #define EXC_LOAD_PAGE_FAULT 13 | |
73 | #define EXC_STORE_PAGE_FAULT 15 | |
5d8544e2 | 74 | |
a4c3733d | 75 | /* symbolic CSR names: */ |
a3182c91 AP |
76 | #define CSR_CYCLE 0xc00 |
77 | #define CSR_TIME 0xc01 | |
78 | #define CSR_INSTRET 0xc02 | |
a4c3733d CH |
79 | #define CSR_CYCLEH 0xc80 |
80 | #define CSR_TIMEH 0xc81 | |
81 | #define CSR_INSTRETH 0xc82 | |
82 | ||
a3182c91 AP |
83 | #define CSR_SSTATUS 0x100 |
84 | #define CSR_SIE 0x104 | |
85 | #define CSR_STVEC 0x105 | |
86 | #define CSR_SCOUNTEREN 0x106 | |
87 | #define CSR_SSCRATCH 0x140 | |
88 | #define CSR_SEPC 0x141 | |
89 | #define CSR_SCAUSE 0x142 | |
90 | #define CSR_STVAL 0x143 | |
91 | #define CSR_SIP 0x144 | |
92 | #define CSR_SATP 0x180 | |
a4c3733d CH |
93 | |
94 | #define CSR_MSTATUS 0x300 | |
9e806356 | 95 | #define CSR_MISA 0x301 |
a4c3733d CH |
96 | #define CSR_MIE 0x304 |
97 | #define CSR_MTVEC 0x305 | |
98 | #define CSR_MSCRATCH 0x340 | |
99 | #define CSR_MEPC 0x341 | |
100 | #define CSR_MCAUSE 0x342 | |
101 | #define CSR_MTVAL 0x343 | |
102 | #define CSR_MIP 0x344 | |
accb9dbc | 103 | #define CSR_MHARTID 0xf14 |
a4c3733d CH |
104 | |
105 | #ifdef CONFIG_RISCV_M_MODE | |
106 | # define CSR_STATUS CSR_MSTATUS | |
107 | # define CSR_IE CSR_MIE | |
108 | # define CSR_TVEC CSR_MTVEC | |
109 | # define CSR_SCRATCH CSR_MSCRATCH | |
110 | # define CSR_EPC CSR_MEPC | |
111 | # define CSR_CAUSE CSR_MCAUSE | |
112 | # define CSR_TVAL CSR_MTVAL | |
113 | # define CSR_IP CSR_MIP | |
114 | ||
115 | # define SR_IE SR_MIE | |
116 | # define SR_PIE SR_MPIE | |
117 | # define SR_PP SR_MPP | |
118 | ||
2f3035da PW |
119 | # define RV_IRQ_SOFT IRQ_M_SOFT |
120 | # define RV_IRQ_TIMER IRQ_M_TIMER | |
121 | # define RV_IRQ_EXT IRQ_M_EXT | |
a4c3733d CH |
122 | #else /* CONFIG_RISCV_M_MODE */ |
123 | # define CSR_STATUS CSR_SSTATUS | |
124 | # define CSR_IE CSR_SIE | |
125 | # define CSR_TVEC CSR_STVEC | |
126 | # define CSR_SCRATCH CSR_SSCRATCH | |
127 | # define CSR_EPC CSR_SEPC | |
128 | # define CSR_CAUSE CSR_SCAUSE | |
129 | # define CSR_TVAL CSR_STVAL | |
130 | # define CSR_IP CSR_SIP | |
131 | ||
132 | # define SR_IE SR_SIE | |
133 | # define SR_PIE SR_SPIE | |
134 | # define SR_PP SR_SPP | |
135 | ||
2f3035da PW |
136 | # define RV_IRQ_SOFT IRQ_S_SOFT |
137 | # define RV_IRQ_TIMER IRQ_S_TIMER | |
138 | # define RV_IRQ_EXT IRQ_S_EXT | |
a4c3733d CH |
139 | #endif /* CONFIG_RISCV_M_MODE */ |
140 | ||
141 | /* IE/IP (Supervisor/Machine Interrupt Enable/Pending) flags */ | |
2f3035da PW |
142 | #define IE_SIE (_AC(0x1, UL) << RV_IRQ_SOFT) |
143 | #define IE_TIE (_AC(0x1, UL) << RV_IRQ_TIMER) | |
144 | #define IE_EIE (_AC(0x1, UL) << RV_IRQ_EXT) | |
a3182c91 | 145 | |
5d8544e2 PD |
146 | #ifndef __ASSEMBLY__ |
147 | ||
148 | #define csr_swap(csr, val) \ | |
149 | ({ \ | |
150 | unsigned long __v = (unsigned long)(val); \ | |
a3182c91 | 151 | __asm__ __volatile__ ("csrrw %0, " __ASM_STR(csr) ", %1"\ |
5d8544e2 PD |
152 | : "=r" (__v) : "rK" (__v) \ |
153 | : "memory"); \ | |
154 | __v; \ | |
155 | }) | |
156 | ||
157 | #define csr_read(csr) \ | |
158 | ({ \ | |
159 | register unsigned long __v; \ | |
a3182c91 | 160 | __asm__ __volatile__ ("csrr %0, " __ASM_STR(csr) \ |
5d8544e2 PD |
161 | : "=r" (__v) : \ |
162 | : "memory"); \ | |
163 | __v; \ | |
164 | }) | |
165 | ||
166 | #define csr_write(csr, val) \ | |
167 | ({ \ | |
168 | unsigned long __v = (unsigned long)(val); \ | |
a3182c91 | 169 | __asm__ __volatile__ ("csrw " __ASM_STR(csr) ", %0" \ |
5d8544e2 PD |
170 | : : "rK" (__v) \ |
171 | : "memory"); \ | |
172 | }) | |
173 | ||
174 | #define csr_read_set(csr, val) \ | |
175 | ({ \ | |
176 | unsigned long __v = (unsigned long)(val); \ | |
a3182c91 | 177 | __asm__ __volatile__ ("csrrs %0, " __ASM_STR(csr) ", %1"\ |
5d8544e2 PD |
178 | : "=r" (__v) : "rK" (__v) \ |
179 | : "memory"); \ | |
180 | __v; \ | |
181 | }) | |
182 | ||
183 | #define csr_set(csr, val) \ | |
184 | ({ \ | |
185 | unsigned long __v = (unsigned long)(val); \ | |
a3182c91 | 186 | __asm__ __volatile__ ("csrs " __ASM_STR(csr) ", %0" \ |
5d8544e2 PD |
187 | : : "rK" (__v) \ |
188 | : "memory"); \ | |
189 | }) | |
190 | ||
191 | #define csr_read_clear(csr, val) \ | |
192 | ({ \ | |
193 | unsigned long __v = (unsigned long)(val); \ | |
a3182c91 | 194 | __asm__ __volatile__ ("csrrc %0, " __ASM_STR(csr) ", %1"\ |
5d8544e2 PD |
195 | : "=r" (__v) : "rK" (__v) \ |
196 | : "memory"); \ | |
197 | __v; \ | |
198 | }) | |
199 | ||
200 | #define csr_clear(csr, val) \ | |
201 | ({ \ | |
202 | unsigned long __v = (unsigned long)(val); \ | |
a3182c91 | 203 | __asm__ __volatile__ ("csrc " __ASM_STR(csr) ", %0" \ |
5d8544e2 PD |
204 | : : "rK" (__v) \ |
205 | : "memory"); \ | |
206 | }) | |
207 | ||
208 | #endif /* __ASSEMBLY__ */ | |
209 | ||
210 | #endif /* _ASM_RISCV_CSR_H */ |