[linux-block.git] / arch / riscv / Kconfig.errata

menu "CPU errata selection"

config ERRATA_ANDES
	bool "Andes AX45MP errata"
	depends on RISCV_ALTERNATIVE && RISCV_SBI
	help
	  All Andes errata Kconfig depend on this Kconfig. Disabling
	  this Kconfig will disable all Andes errata. Please say "Y"
	  here if your platform uses Andes CPU cores.

	  Otherwise, please say "N" here to avoid unnecessary overhead.

config ERRATA_ANDES_CMO
	bool "Apply Andes cache management errata"
	depends on ERRATA_ANDES && ARCH_R9A07G043
	select RISCV_DMA_NONCOHERENT
	default y
	help
	  This will apply the cache management errata to handle the
	  non-standard handling on non-coherent operations on Andes cores.

	  If you don't know what to do here, say "Y".

config ERRATA_SIFIVE
	bool "SiFive errata"
	depends on RISCV_ALTERNATIVE
	help
	  All SiFive errata Kconfig depend on this Kconfig. Disabling
	  this Kconfig will disable all SiFive errata. Please say "Y"
	  here if your platform uses SiFive CPU cores.

	  Otherwise, please say "N" here to avoid unnecessary overhead.

config ERRATA_SIFIVE_CIP_453
	bool "Apply SiFive errata CIP-453"
	depends on ERRATA_SIFIVE && 64BIT
	default y
	help
	  This will apply the SiFive CIP-453 errata to add sign extension
	  to the $badaddr when exception type is instruction page fault
	  and instruction access fault.

	  If you don't know what to do here, say "Y".

config ERRATA_SIFIVE_CIP_1200
	bool "Apply SiFive errata CIP-1200"
	depends on ERRATA_SIFIVE && 64BIT
	default y
	help
	  This will apply the SiFive CIP-1200 errata to repalce all
	  "sfence.vma addr" with "sfence.vma" to ensure that the addr
	  has been flushed from TLB.

	  If you don't know what to do here, say "Y".

config ERRATA_THEAD
	bool "T-HEAD errata"
	depends on RISCV_ALTERNATIVE
	help
	  All T-HEAD errata Kconfig depend on this Kconfig. Disabling
	  this Kconfig will disable all T-HEAD errata. Please say "Y"
	  here if your platform uses T-HEAD CPU cores.

	  Otherwise, please say "N" here to avoid unnecessary overhead.

config ERRATA_THEAD_PBMT
	bool "Apply T-Head memory type errata"
	depends on ERRATA_THEAD && 64BIT && MMU
	select RISCV_ALTERNATIVE_EARLY
	default y
	help
	  This will apply the memory type errata to handle the non-standard
	  memory type bits in page-table-entries on T-Head SoCs.

	  If you don't know what to do here, say "Y".

config ERRATA_THEAD_CMO
	bool "Apply T-Head cache management errata"
	depends on ERRATA_THEAD && MMU
	select RISCV_DMA_NONCOHERENT
	default y
	help
	  This will apply the cache management errata to handle the
	  non-standard handling on non-coherent operations on T-Head SoCs.

	  If you don't know what to do here, say "Y".

config ERRATA_THEAD_PMU
	bool "Apply T-Head PMU errata"
	depends on ERRATA_THEAD && RISCV_PMU_SBI
	default y
	help
	  The T-Head C9xx cores implement a PMU overflow extension very
	  similar to the core SSCOFPMF extension.

	  This will apply the overflow errata to handle the non-standard
	  behaviour via the regular SBI PMU driver and interface.

	  If you don't know what to do here, say "Y".

endmenu # "CPU errata selection"
Commit	Line	Data
6f4eea90 VC	1	menu "CPU errata selection"
6f4eea90 VC	2
e021ae7f LP	3	config ERRATA_ANDES
e021ae7f LP	4	bool "Andes AX45MP errata"
2f73b35d	5	depends on RISCV_ALTERNATIVE && RISCV_SBI
e021ae7f LP	6	help
	7	All Andes errata Kconfig depend on this Kconfig. Disabling
	8	this Kconfig will disable all Andes errata. Please say "Y"
	9	here if your platform uses Andes CPU cores.
	10
	11	Otherwise, please say "N" here to avoid unnecessary overhead.
	12
	13	config ERRATA_ANDES_CMO
	14	bool "Apply Andes cache management errata"
54adc24c	15	depends on ERRATA_ANDES && ARCH_R9A07G043
e021ae7f LP	16	select RISCV_DMA_NONCOHERENT
	17	default y
	18	help
	19	This will apply the cache management errata to handle the
	20	non-standard handling on non-coherent operations on Andes cores.
	21
	22	If you don't know what to do here, say "Y".
	23
1a0e5dbd VC	24	config ERRATA_SIFIVE
1a0e5dbd VC	25	bool "SiFive errata"
1ee7fc3f	26	depends on RISCV_ALTERNATIVE
1a0e5dbd VC	27	help
	28	All SiFive errata Kconfig depend on this Kconfig. Disabling
	29	this Kconfig will disable all SiFive errata. Please say "Y"
	30	here if your platform uses SiFive CPU cores.
	31
	32	Otherwise, please say "N" here to avoid unnecessary overhead.
	33
800149a7 VC	34	config ERRATA_SIFIVE_CIP_453
800149a7 VC	35	bool "Apply SiFive errata CIP-453"
0e0d4992	36	depends on ERRATA_SIFIVE && 64BIT
800149a7 VC	37	default y
	38	help
	39	This will apply the SiFive CIP-453 errata to add sign extension
	40	to the $badaddr when exception type is instruction page fault
	41	and instruction access fault.
	42
	43	If you don't know what to do here, say "Y".
	44
bff3ff52 VC	45	config ERRATA_SIFIVE_CIP_1200
bff3ff52 VC	46	bool "Apply SiFive errata CIP-1200"
0e0d4992	47	depends on ERRATA_SIFIVE && 64BIT
bff3ff52 VC	48	default y
	49	help
	50	This will apply the SiFive CIP-1200 errata to repalce all
	51	"sfence.vma addr" with "sfence.vma" to ensure that the addr
	52	has been flushed from TLB.
	53
	54	If you don't know what to do here, say "Y".
	55
a35707c3 HS	56	config ERRATA_THEAD
a35707c3 HS	57	bool "T-HEAD errata"
1ee7fc3f	58	depends on RISCV_ALTERNATIVE
a35707c3 HS	59	help
	60	All T-HEAD errata Kconfig depend on this Kconfig. Disabling
	61	this Kconfig will disable all T-HEAD errata. Please say "Y"
	62	here if your platform uses T-HEAD CPU cores.
	63
	64	Otherwise, please say "N" here to avoid unnecessary overhead.
	65
	66	config ERRATA_THEAD_PBMT
	67	bool "Apply T-Head memory type errata"
2a2018c3	68	depends on ERRATA_THEAD && 64BIT && MMU
a35707c3 HS	69	select RISCV_ALTERNATIVE_EARLY
	70	default y
	71	help
	72	This will apply the memory type errata to handle the non-standard
	73	memory type bits in page-table-entries on T-Head SoCs.
	74
	75	If you don't know what to do here, say "Y".
	76
d20ec752 HS	77	config ERRATA_THEAD_CMO
d20ec752 HS	78	bool "Apply T-Head cache management errata"
2a2018c3	79	depends on ERRATA_THEAD && MMU
d20ec752 HS	80	select RISCV_DMA_NONCOHERENT
	81	default y
	82	help
	83	This will apply the cache management errata to handle the
	84	non-standard handling on non-coherent operations on T-Head SoCs.
	85
	86	If you don't know what to do here, say "Y".
	87
65e9fb08 HS	88	config ERRATA_THEAD_PMU
	89	bool "Apply T-Head PMU errata"
	90	depends on ERRATA_THEAD && RISCV_PMU_SBI
	91	default y
	92	help
	93	The T-Head C9xx cores implement a PMU overflow extension very
	94	similar to the core SSCOFPMF extension.
	95
	96	This will apply the overflow errata to handle the non-standard
	97	behaviour via the regular SBI PMU driver and interface.
	98
	99	If you don't know what to do here, say "Y".
	100
84b10f78	101	endmenu # "CPU errata selection"