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ppc64: Add a `primary' argument to pci_process_bridge_OF_ranges
[linux-2.6-block.git] / arch / ppc64 / kernel / pci.c
CommitLineData
1da177e4
LT		 1/*
2 * Port for PPC64 David Engebretsen, IBM Corp.
3 * Contains common pci routines for ppc64 platform, pSeries and iSeries brands.
4 *
5 * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM
6 * Rework, based on alpha PCI code.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * as published by the Free Software Foundation; either version
11 * 2 of the License, or (at your option) any later version.
12 */
13
14#undef DEBUG
15
16#include <linux/config.h>
17#include <linux/kernel.h>
18#include <linux/pci.h>
19#include <linux/string.h>
20#include <linux/init.h>
21#include <linux/bootmem.h>
22#include <linux/mm.h>
23#include <linux/list.h>
b2ad7b5e 24#include <linux/syscalls.h>
1da177e4
LT		 25
26#include <asm/processor.h>
27#include <asm/io.h>
28#include <asm/prom.h>
29#include <asm/pci-bridge.h>
30#include <asm/byteorder.h>
31#include <asm/irq.h>
32#include <asm/machdep.h>
33#include <asm/udbg.h>
d387899f 34#include <asm/ppc-pci.h>
1da177e4
LT		 35
36#ifdef DEBUG
37#define DBG(fmt...) udbg_printf(fmt)
38#else
39#define DBG(fmt...)
40#endif
41
42unsigned long pci_probe_only = 1;
43unsigned long pci_assign_all_buses = 0;
44
45/*
46 * legal IO pages under MAX_ISA_PORT. This is to ensure we don't touch
47 * devices we don't have access to.
48 */
49unsigned long io_page_mask;
50
51EXPORT_SYMBOL(io_page_mask);
52
4267292b
PM		 53#ifdef CONFIG_PPC_MULTIPLATFORM
54static void fixup_resource(struct resource *res, struct pci_dev *dev);
55static void do_bus_setup(struct pci_bus *bus);
56#endif
1da177e4
LT		 57
58unsigned int pcibios_assign_all_busses(void)
59{
60 return pci_assign_all_buses;
61}
62
63/* pci_io_base -- the base address from which io bars are offsets.
64 * This is the lowest I/O base address (so bar values are always positive),
65 * and it *must* be the start of ISA space if an ISA bus exists because
66 * ISA drivers use hard coded offsets. If no ISA bus exists a dummy
67 * page is mapped and isa_io_limit prevents access to it.
68 */
69unsigned long isa_io_base; /* NULL if no ISA bus */
70EXPORT_SYMBOL(isa_io_base);
71unsigned long pci_io_base;
72EXPORT_SYMBOL(pci_io_base);
73
74void iSeries_pcibios_init(void);
75
76LIST_HEAD(hose_list);
77
78struct dma_mapping_ops pci_dma_ops;
79EXPORT_SYMBOL(pci_dma_ops);
80
81int global_phb_number; /* Global phb counter */
82
83/* Cached ISA bridge dev. */
84struct pci_dev *ppc64_isabridge_dev = NULL;
85
86static void fixup_broken_pcnet32(struct pci_dev* dev)
87{
88 if ((dev->class>>8 == PCI_CLASS_NETWORK_ETHERNET)) {
89 dev->vendor = PCI_VENDOR_ID_AMD;
90 pci_write_config_word(dev, PCI_VENDOR_ID, PCI_VENDOR_ID_AMD);
1da177e4
LT		 91 }
92}
93DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TRIDENT, PCI_ANY_ID, fixup_broken_pcnet32);
94
95void pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
96 struct resource *res)
97{
98 unsigned long offset = 0;
99 struct pci_controller *hose = pci_bus_to_host(dev->bus);
100
101 if (!hose)
102 return;
103
104 if (res->flags & IORESOURCE_IO)
105 offset = (unsigned long)hose->io_base_virt - pci_io_base;
106
107 if (res->flags & IORESOURCE_MEM)
108 offset = hose->pci_mem_offset;
109
110 region->start = res->start - offset;
111 region->end = res->end - offset;
112}
113
43c34735
DB		 114void pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
115 struct pci_bus_region *region)
116{
117 unsigned long offset = 0;
118 struct pci_controller *hose = pci_bus_to_host(dev->bus);
119
120 if (!hose)
121 return;
122
123 if (res->flags & IORESOURCE_IO)
124 offset = (unsigned long)hose->io_base_virt - pci_io_base;
125
126 if (res->flags & IORESOURCE_MEM)
127 offset = hose->pci_mem_offset;
128
129 res->start = region->start + offset;
130 res->end = region->end + offset;
131}
132
1da177e4
LT		 133#ifdef CONFIG_HOTPLUG
134EXPORT_SYMBOL(pcibios_resource_to_bus);
43c34735 135EXPORT_SYMBOL(pcibios_bus_to_resource);
1da177e4
LT		 136#endif
137
138/*
139 * We need to avoid collisions with `mirrored' VGA ports
140 * and other strange ISA hardware, so we always want the
141 * addresses to be allocated in the 0x000-0x0ff region
142 * modulo 0x400.
143 *
144 * Why? Because some silly external IO cards only decode
145 * the low 10 bits of the IO address. The 0x00-0xff region
146 * is reserved for motherboard devices that decode all 16
147 * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
148 * but we want to try to avoid allocating at 0x2900-0x2bff
149 * which might have be mirrored at 0x0100-0x03ff..
150 */
151void pcibios_align_resource(void *data, struct resource *res,
152 unsigned long size, unsigned long align)
153{
154 struct pci_dev *dev = data;
155 struct pci_controller *hose = pci_bus_to_host(dev->bus);
156 unsigned long start = res->start;
157 unsigned long alignto;
158
159 if (res->flags & IORESOURCE_IO) {
160 unsigned long offset = (unsigned long)hose->io_base_virt -
161 pci_io_base;
162 /* Make sure we start at our min on all hoses */
163 if (start - offset < PCIBIOS_MIN_IO)
164 start = PCIBIOS_MIN_IO + offset;
165
166 /*
167 * Put everything into 0x00-0xff region modulo 0x400
168 */
169 if (start & 0x300)
170 start = (start + 0x3ff) & ~0x3ff;
171
172 } else if (res->flags & IORESOURCE_MEM) {
173 /* Make sure we start at our min on all hoses */
174 if (start - hose->pci_mem_offset < PCIBIOS_MIN_MEM)
175 start = PCIBIOS_MIN_MEM + hose->pci_mem_offset;
176
177 /* Align to multiple of size of minimum base. */
178 alignto = max(0x1000UL, align);
179 start = ALIGN(start, alignto);
180 }
181
182 res->start = start;
183}
184
185static DEFINE_SPINLOCK(hose_spinlock);
186
187/*
188 * pci_controller(phb) initialized common variables.
189 */
190void __devinit pci_setup_pci_controller(struct pci_controller *hose)
191{
192 memset(hose, 0, sizeof(struct pci_controller));
193
194 spin_lock(&hose_spinlock);
195 hose->global_number = global_phb_number++;
196 list_add_tail(&hose->list_node, &hose_list);
197 spin_unlock(&hose_spinlock);
198}
199
200static void __init pcibios_claim_one_bus(struct pci_bus *b)
201{
202 struct pci_dev *dev;
203 struct pci_bus *child_bus;
204
205 list_for_each_entry(dev, &b->devices, bus_list) {
206 int i;
207
208 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
209 struct resource *r = &dev->resource[i];
210
211 if (r->parent || !r->start || !r->flags)
212 continue;
213 pci_claim_resource(dev, i);
214 }
215 }
216
217 list_for_each_entry(child_bus, &b->children, node)
218 pcibios_claim_one_bus(child_bus);
219}
220
221#ifndef CONFIG_PPC_ISERIES
222static void __init pcibios_claim_of_setup(void)
223{
224 struct pci_bus *b;
225
226 list_for_each_entry(b, &pci_root_buses, node)
227 pcibios_claim_one_bus(b);
228}
229#endif
230
4267292b
PM		 231#ifdef CONFIG_PPC_MULTIPLATFORM
232static u32 get_int_prop(struct device_node *np, const char *name, u32 def)
233{
234 u32 *prop;
235 int len;
236
237 prop = (u32 *) get_property(np, name, &len);
238 if (prop && len >= 4)
239 return *prop;
240 return def;
241}
242
243static unsigned int pci_parse_of_flags(u32 addr0)
244{
245 unsigned int flags = 0;
246
247 if (addr0 & 0x02000000) {
d79e743e
PM		 248 flags = IORESOURCE_MEM | PCI_BASE_ADDRESS_SPACE_MEMORY;
249 flags |= (addr0 >> 22) & PCI_BASE_ADDRESS_MEM_TYPE_64;
250 flags |= (addr0 >> 28) & PCI_BASE_ADDRESS_MEM_TYPE_1M;
4267292b 251 if (addr0 & 0x40000000)
d79e743e
PM		 252 flags |= IORESOURCE_PREFETCH
253 | PCI_BASE_ADDRESS_MEM_PREFETCH;
4267292b 254 } else if (addr0 & 0x01000000)
d79e743e 255 flags = IORESOURCE_IO | PCI_BASE_ADDRESS_SPACE_IO;
4267292b
PM		 256 return flags;
257}
258
259#define GET_64BIT(prop, i) ((((u64) (prop)[(i)]) << 32) | (prop)[(i)+1])
260
261static void pci_parse_of_addrs(struct device_node *node, struct pci_dev *dev)
262{
263 u64 base, size;
264 unsigned int flags;
265 struct resource *res;
266 u32 *addrs, i;
267 int proplen;
268
269 addrs = (u32 *) get_property(node, "assigned-addresses", &proplen);
270 if (!addrs)
271 return;
272 for (; proplen >= 20; proplen -= 20, addrs += 5) {
273 flags = pci_parse_of_flags(addrs[0]);
274 if (!flags)
275 continue;
276 base = GET_64BIT(addrs, 1);
277 size = GET_64BIT(addrs, 3);
278 if (!size)
279 continue;
280 i = addrs[0] & 0xff;
281 if (PCI_BASE_ADDRESS_0 <= i && i <= PCI_BASE_ADDRESS_5) {
282 res = &dev->resource[(i - PCI_BASE_ADDRESS_0) >> 2];
283 } else if (i == dev->rom_base_reg) {
284 res = &dev->resource[PCI_ROM_RESOURCE];
285 flags |= IORESOURCE_READONLY | IORESOURCE_CACHEABLE;
286 } else {
287 printk(KERN_ERR "PCI: bad cfg reg num 0x%x\n", i);
288 continue;
289 }
290 res->start = base;
291 res->end = base + size - 1;
292 res->flags = flags;
293 res->name = pci_name(dev);
294 fixup_resource(res, dev);
295 }
296}
297
298static struct pci_dev *of_create_pci_dev(struct device_node *node,
299 struct pci_bus *bus, int devfn)
300{
301 struct pci_dev *dev;
302 const char *type;
303
304 dev = kmalloc(sizeof(struct pci_dev), GFP_KERNEL);
305 if (!dev)
306 return NULL;
307 type = get_property(node, "device_type", NULL);
308 if (type == NULL)
309 type = "";
310
311 memset(dev, 0, sizeof(struct pci_dev));
312 dev->bus = bus;
313 dev->sysdata = node;
314 dev->dev.parent = bus->bridge;
315 dev->dev.bus = &pci_bus_type;
316 dev->devfn = devfn;
317 dev->multifunction = 0; /* maybe a lie? */
318
319 dev->vendor = get_int_prop(node, "vendor-id", 0xffff);
320 dev->device = get_int_prop(node, "device-id", 0xffff);
321 dev->subsystem_vendor = get_int_prop(node, "subsystem-vendor-id", 0);
322 dev->subsystem_device = get_int_prop(node, "subsystem-id", 0);
323
324 dev->cfg_size = 256; /*pci_cfg_space_size(dev);*/
325
326 sprintf(pci_name(dev), "%04x:%02x:%02x.%d", pci_domain_nr(bus),
327 dev->bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn));
328 dev->class = get_int_prop(node, "class-code", 0);
329
330 dev->current_state = 4; /* unknown power state */
331
332 if (!strcmp(type, "pci")) {
333 /* a PCI-PCI bridge */
334 dev->hdr_type = PCI_HEADER_TYPE_BRIDGE;
335 dev->rom_base_reg = PCI_ROM_ADDRESS1;
336 } else if (!strcmp(type, "cardbus")) {
337 dev->hdr_type = PCI_HEADER_TYPE_CARDBUS;
338 } else {
339 dev->hdr_type = PCI_HEADER_TYPE_NORMAL;
340 dev->rom_base_reg = PCI_ROM_ADDRESS;
341 dev->irq = NO_IRQ;
342 if (node->n_intrs > 0) {
343 dev->irq = node->intrs[0].line;
344 pci_write_config_byte(dev, PCI_INTERRUPT_LINE,
345 dev->irq);
346 }
347 }
348
349 pci_parse_of_addrs(node, dev);
350
351 pci_device_add(dev, bus);
352
353 /* XXX pci_scan_msi_device(dev); */
354
355 return dev;
356}
357
358static void of_scan_pci_bridge(struct device_node *node, struct pci_dev *dev);
359
360static void __devinit of_scan_bus(struct device_node *node,
361 struct pci_bus *bus)
362{
363 struct device_node *child = NULL;
364 u32 *reg;
365 int reglen, devfn;
366 struct pci_dev *dev;
367
368 while ((child = of_get_next_child(node, child)) != NULL) {
369 reg = (u32 *) get_property(child, "reg", &reglen);
370 if (reg == NULL || reglen < 20)
371 continue;
372 devfn = (reg[0] >> 8) & 0xff;
373 /* create a new pci_dev for this device */
374 dev = of_create_pci_dev(child, bus, devfn);
375 if (!dev)
376 continue;
377 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
378 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS)
379 of_scan_pci_bridge(child, dev);
380 }
381
382 do_bus_setup(bus);
383}
384
385static void __devinit of_scan_pci_bridge(struct device_node *node,
386 struct pci_dev *dev)
387{
388 struct pci_bus *bus;
389 u32 *busrange, *ranges;
390 int len, i, mode;
391 struct resource *res;
392 unsigned int flags;
393 u64 size;
394
395 /* parse bus-range property */
396 busrange = (u32 *) get_property(node, "bus-range", &len);
397 if (busrange == NULL || len != 8) {
398 printk(KERN_ERR "Can't get bus-range for PCI-PCI bridge %s\n",
399 node->full_name);
400 return;
401 }
402 ranges = (u32 *) get_property(node, "ranges", &len);
403 if (ranges == NULL) {
404 printk(KERN_ERR "Can't get ranges for PCI-PCI bridge %s\n",
405 node->full_name);
406 return;
407 }
408
409 bus = pci_add_new_bus(dev->bus, dev, busrange[0]);
410 if (!bus) {
411 printk(KERN_ERR "Failed to create pci bus for %s\n",
412 node->full_name);
413 return;
414 }
415
416 bus->primary = dev->bus->number;
417 bus->subordinate = busrange[1];
418 bus->bridge_ctl = 0;
419 bus->sysdata = node;
420
421 /* parse ranges property */
422 /* PCI #address-cells == 3 and #size-cells == 2 always */
423 res = &dev->resource[PCI_BRIDGE_RESOURCES];
424 for (i = 0; i < PCI_NUM_RESOURCES - PCI_BRIDGE_RESOURCES; ++i) {
425 res->flags = 0;
426 bus->resource[i] = res;
427 ++res;
428 }
429 i = 1;
430 for (; len >= 32; len -= 32, ranges += 8) {
431 flags = pci_parse_of_flags(ranges[0]);
432 size = GET_64BIT(ranges, 6);
433 if (flags == 0 || size == 0)
434 continue;
435 if (flags & IORESOURCE_IO) {
436 res = bus->resource[0];
437 if (res->flags) {
438 printk(KERN_ERR "PCI: ignoring extra I/O range"
439 " for bridge %s\n", node->full_name);
440 continue;
441 }
442 } else {
443 if (i >= PCI_NUM_RESOURCES - PCI_BRIDGE_RESOURCES) {
444 printk(KERN_ERR "PCI: too many memory ranges"
445 " for bridge %s\n", node->full_name);
446 continue;
447 }
448 res = bus->resource[i];
449 ++i;
450 }
451 res->start = GET_64BIT(ranges, 1);
452 res->end = res->start + size - 1;
453 res->flags = flags;
454 fixup_resource(res, dev);
455 }
456 sprintf(bus->name, "PCI Bus %04x:%02x", pci_domain_nr(bus),
457 bus->number);
458
459 mode = PCI_PROBE_NORMAL;
460 if (ppc_md.pci_probe_mode)
461 mode = ppc_md.pci_probe_mode(bus);
462 if (mode == PCI_PROBE_DEVTREE)
463 of_scan_bus(node, bus);
464 else if (mode == PCI_PROBE_NORMAL)
465 pci_scan_child_bus(bus);
466}
467#endif /* CONFIG_PPC_MULTIPLATFORM */
468
469static void __devinit scan_phb(struct pci_controller *hose)
470{
471 struct pci_bus *bus;
472 struct device_node *node = hose->arch_data;
473 int i, mode;
474 struct resource *res;
475
476 bus = pci_create_bus(NULL, hose->first_busno, hose->ops, node);
477 if (bus == NULL) {
478 printk(KERN_ERR "Failed to create bus for PCI domain %04x\n",
479 hose->global_number);
480 return;
481 }
482 bus->secondary = hose->first_busno;
483 hose->bus = bus;
484
485 bus->resource[0] = res = &hose->io_resource;
486 if (res->flags && request_resource(&ioport_resource, res))
487 printk(KERN_ERR "Failed to request PCI IO region "
488 "on PCI domain %04x\n", hose->global_number);
489
490 for (i = 0; i < 3; ++i) {
491 res = &hose->mem_resources[i];
492 bus->resource[i+1] = res;
493 if (res->flags && request_resource(&iomem_resource, res))
494 printk(KERN_ERR "Failed to request PCI memory region "
495 "on PCI domain %04x\n", hose->global_number);
496 }
497
498 mode = PCI_PROBE_NORMAL;
499#ifdef CONFIG_PPC_MULTIPLATFORM
500 if (ppc_md.pci_probe_mode)
501 mode = ppc_md.pci_probe_mode(bus);
502 if (mode == PCI_PROBE_DEVTREE) {
503 bus->subordinate = hose->last_busno;
504 of_scan_bus(node, bus);
505 }
506#endif /* CONFIG_PPC_MULTIPLATFORM */
507 if (mode == PCI_PROBE_NORMAL)
508 hose->last_busno = bus->subordinate = pci_scan_child_bus(bus);
509 pci_bus_add_devices(bus);
510}
511
1da177e4
LT		 512static int __init pcibios_init(void)
513{
514 struct pci_controller *hose, *tmp;
1da177e4
LT		 515
516 /* For now, override phys_mem_access_prot. If we need it,
517 * later, we may move that initialization to each ppc_md
518 */
519 ppc_md.phys_mem_access_prot = pci_phys_mem_access_prot;
520
521#ifdef CONFIG_PPC_ISERIES
522 iSeries_pcibios_init();
523#endif
524
525 printk("PCI: Probing PCI hardware\n");
526
527 /* Scan all of the recorded PCI controllers. */
4267292b
PM		 528 list_for_each_entry_safe(hose, tmp, &hose_list, list_node)
529 scan_phb(hose);
1da177e4
LT		 530
531#ifndef CONFIG_PPC_ISERIES
532 if (pci_probe_only)
533 pcibios_claim_of_setup();
534 else
535 /* FIXME: `else' will be removed when
536 pci_assign_unassigned_resources() is able to work
537 correctly with [partially] allocated PCI tree. */
538 pci_assign_unassigned_resources();
539#endif /* !CONFIG_PPC_ISERIES */
540
541 /* Call machine dependent final fixup */
542 if (ppc_md.pcibios_fixup)
543 ppc_md.pcibios_fixup();
544
545 /* Cache the location of the ISA bridge (if we have one) */
546 ppc64_isabridge_dev = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL);
547 if (ppc64_isabridge_dev != NULL)
548 printk("ISA bridge at %s\n", pci_name(ppc64_isabridge_dev));
549
550 printk("PCI: Probing PCI hardware done\n");
551
552 return 0;
553}
554
555subsys_initcall(pcibios_init);
556
557char __init *pcibios_setup(char *str)
558{
559 return str;
560}
561
562int pcibios_enable_device(struct pci_dev *dev, int mask)
563{
564 u16 cmd, oldcmd;
565 int i;
566
567 pci_read_config_word(dev, PCI_COMMAND, &cmd);
568 oldcmd = cmd;
569
570 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
571 struct resource *res = &dev->resource[i];
572
573 /* Only set up the requested stuff */
574 if (!(mask & (1<<i)))
575 continue;
576
577 if (res->flags & IORESOURCE_IO)
578 cmd |= PCI_COMMAND_IO;
579 if (res->flags & IORESOURCE_MEM)
580 cmd |= PCI_COMMAND_MEMORY;
581 }
582
583 if (cmd != oldcmd) {
584 printk(KERN_DEBUG "PCI: Enabling device: (%s), cmd %x\n",
585 pci_name(dev), cmd);
586 /* Enable the appropriate bits in the PCI command register. */
587 pci_write_config_word(dev, PCI_COMMAND, cmd);
588 }
589 return 0;
590}
591
592/*
593 * Return the domain number for this bus.
594 */
595int pci_domain_nr(struct pci_bus *bus)
596{
597#ifdef CONFIG_PPC_ISERIES
598 return 0;
599#else
600 struct pci_controller *hose = pci_bus_to_host(bus);
601
602 return hose->global_number;
603#endif
604}
605
606EXPORT_SYMBOL(pci_domain_nr);
607
608/* Decide whether to display the domain number in /proc */
609int pci_proc_domain(struct pci_bus *bus)
610{
611#ifdef CONFIG_PPC_ISERIES
612 return 0;
613#else
614 struct pci_controller *hose = pci_bus_to_host(bus);
615 return hose->buid;
616#endif
617}
618
619/*
620 * Platform support for /proc/bus/pci/X/Y mmap()s,
621 * modelled on the sparc64 implementation by Dave Miller.
622 * -- paulus.
623 */
624
625/*
626 * Adjust vm_pgoff of VMA such that it is the physical page offset
627 * corresponding to the 32-bit pci bus offset for DEV requested by the user.
628 *
629 * Basically, the user finds the base address for his device which he wishes
630 * to mmap. They read the 32-bit value from the config space base register,
631 * add whatever PAGE_SIZE multiple offset they wish, and feed this into the
632 * offset parameter of mmap on /proc/bus/pci/XXX for that device.
633 *
634 * Returns negative error code on failure, zero on success.
635 */
636static struct resource *__pci_mmap_make_offset(struct pci_dev *dev,
637 unsigned long *offset,
638 enum pci_mmap_state mmap_state)
639{
640 struct pci_controller *hose = pci_bus_to_host(dev->bus);
641 unsigned long io_offset = 0;
642 int i, res_bit;
643
644 if (hose == 0)
645 return NULL; /* should never happen */
646
647 /* If memory, add on the PCI bridge address offset */
648 if (mmap_state == pci_mmap_mem) {
649 *offset += hose->pci_mem_offset;
650 res_bit = IORESOURCE_MEM;
651 } else {
2311b1f2 652 io_offset = (unsigned long)hose->io_base_virt - pci_io_base;
1da177e4
LT		 653 *offset += io_offset;
654 res_bit = IORESOURCE_IO;
655 }
656
657 /*
658 * Check that the offset requested corresponds to one of the
659 * resources of the device.
660 */
661 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
662 struct resource *rp = &dev->resource[i];
663 int flags = rp->flags;
664
665 /* treat ROM as memory (should be already) */
666 if (i == PCI_ROM_RESOURCE)
667 flags |= IORESOURCE_MEM;
668
669 /* Active and same type? */
670 if ((flags & res_bit) == 0)
671 continue;
672
673 /* In the range of this resource? */
674 if (*offset < (rp->start & PAGE_MASK) || *offset > rp->end)
675 continue;
676
677 /* found it! construct the final physical address */
678 if (mmap_state == pci_mmap_io)
2311b1f2 679 *offset += hose->io_base_phys - io_offset;
1da177e4
LT		 680 return rp;
681 }
682
683 return NULL;
684}
685
686/*
687 * Set vm_page_prot of VMA, as appropriate for this architecture, for a pci
688 * device mapping.
689 */
690static pgprot_t __pci_mmap_set_pgprot(struct pci_dev *dev, struct resource *rp,
691 pgprot_t protection,
692 enum pci_mmap_state mmap_state,
693 int write_combine)
694{
695 unsigned long prot = pgprot_val(protection);
696
697 /* Write combine is always 0 on non-memory space mappings. On
698 * memory space, if the user didn't pass 1, we check for a
699 * "prefetchable" resource. This is a bit hackish, but we use
700 * this to workaround the inability of /sysfs to provide a write
701 * combine bit
702 */
703 if (mmap_state != pci_mmap_mem)
704 write_combine = 0;
705 else if (write_combine == 0) {
706 if (rp->flags & IORESOURCE_PREFETCH)
707 write_combine = 1;
708 }
709
710 /* XXX would be nice to have a way to ask for write-through */
711 prot |= _PAGE_NO_CACHE;
712 if (write_combine)
713 prot &= ~_PAGE_GUARDED;
714 else
715 prot |= _PAGE_GUARDED;
716
717 printk("PCI map for %s:%lx, prot: %lx\n", pci_name(dev), rp->start,
718 prot);
719
720 return __pgprot(prot);
721}
722
723/*
724 * This one is used by /dev/mem and fbdev who have no clue about the
725 * PCI device, it tries to find the PCI device first and calls the
726 * above routine
727 */
728pgprot_t pci_phys_mem_access_prot(struct file *file,
729 unsigned long offset,
730 unsigned long size,
731 pgprot_t protection)
732{
733 struct pci_dev *pdev = NULL;
734 struct resource *found = NULL;
735 unsigned long prot = pgprot_val(protection);
736 int i;
737
738 if (page_is_ram(offset >> PAGE_SHIFT))
1f8d419e 739 return __pgprot(prot);
1da177e4
LT		 740
741 prot |= _PAGE_NO_CACHE | _PAGE_GUARDED;
742
743 for_each_pci_dev(pdev) {
744 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
745 struct resource *rp = &pdev->resource[i];
746 int flags = rp->flags;
747
748 /* Active and same type? */
749 if ((flags & IORESOURCE_MEM) == 0)
750 continue;
751 /* In the range of this resource? */
752 if (offset < (rp->start & PAGE_MASK) ||
753 offset > rp->end)
754 continue;
755 found = rp;
756 break;
757 }
758 if (found)
759 break;
760 }
761 if (found) {
762 if (found->flags & IORESOURCE_PREFETCH)
763 prot &= ~_PAGE_GUARDED;
764 pci_dev_put(pdev);
765 }
766
767 DBG("non-PCI map for %lx, prot: %lx\n", offset, prot);
768
769 return __pgprot(prot);
770}
771
772
773/*
774 * Perform the actual remap of the pages for a PCI device mapping, as
775 * appropriate for this architecture. The region in the process to map
776 * is described by vm_start and vm_end members of VMA, the base physical
777 * address is found in vm_pgoff.
778 * The pci device structure is provided so that architectures may make mapping
779 * decisions on a per-device or per-bus basis.
780 *
781 * Returns a negative error code on failure, zero on success.
782 */
783int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
784 enum pci_mmap_state mmap_state,
785 int write_combine)
786{
787 unsigned long offset = vma->vm_pgoff << PAGE_SHIFT;
788 struct resource *rp;
789 int ret;
790
791 rp = __pci_mmap_make_offset(dev, &offset, mmap_state);
792 if (rp == NULL)
793 return -EINVAL;
794
795 vma->vm_pgoff = offset >> PAGE_SHIFT;
796 vma->vm_flags |= VM_SHM | VM_LOCKED | VM_IO;
797 vma->vm_page_prot = __pci_mmap_set_pgprot(dev, rp,
798 vma->vm_page_prot,
799 mmap_state, write_combine);
800
801 ret = remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
802 vma->vm_end - vma->vm_start, vma->vm_page_prot);
803
804 return ret;
805}
806
807#ifdef CONFIG_PPC_MULTIPLATFORM
ff381d22 808static ssize_t pci_show_devspec(struct device *dev, struct device_attribute *attr, char *buf)
1da177e4
LT		 809{
810 struct pci_dev *pdev;
811 struct device_node *np;
812
813 pdev = to_pci_dev (dev);
814 np = pci_device_to_OF_node(pdev);
815 if (np == NULL || np->full_name == NULL)
816 return 0;
817 return sprintf(buf, "%s", np->full_name);
818}
819static DEVICE_ATTR(devspec, S_IRUGO, pci_show_devspec, NULL);
820#endif /* CONFIG_PPC_MULTIPLATFORM */
821
822void pcibios_add_platform_entries(struct pci_dev *pdev)
823{
824#ifdef CONFIG_PPC_MULTIPLATFORM
825 device_create_file(&pdev->dev, &dev_attr_devspec);
826#endif /* CONFIG_PPC_MULTIPLATFORM */
827}
828
829#ifdef CONFIG_PPC_MULTIPLATFORM
830
831#define ISA_SPACE_MASK 0x1
832#define ISA_SPACE_IO 0x1
833
834static void __devinit pci_process_ISA_OF_ranges(struct device_node *isa_node,
835 unsigned long phb_io_base_phys,
836 void __iomem * phb_io_base_virt)
837{
838 struct isa_range *range;
839 unsigned long pci_addr;
840 unsigned int isa_addr;
841 unsigned int size;
842 int rlen = 0;
843
844 range = (struct isa_range *) get_property(isa_node, "ranges", &rlen);
845 if (range == NULL || (rlen < sizeof(struct isa_range))) {
846 printk(KERN_ERR "no ISA ranges or unexpected isa range size,"
847 "mapping 64k\n");
dfbacdc1
BH		 848 __ioremap_explicit(phb_io_base_phys,
849 (unsigned long)phb_io_base_virt,
850 0x10000, _PAGE_NO_CACHE | _PAGE_GUARDED);
1da177e4
LT		 851 return;
852 }
853
854 /* From "ISA Binding to 1275"
855 * The ranges property is laid out as an array of elements,
856 * each of which comprises:
857 * cells 0 - 1: an ISA address
858 * cells 2 - 4: a PCI address
859 * (size depending on dev->n_addr_cells)
860 * cell 5: the size of the range
861 */
862 if ((range->isa_addr.a_hi && ISA_SPACE_MASK) == ISA_SPACE_IO) {
863 isa_addr = range->isa_addr.a_lo;
864 pci_addr = (unsigned long) range->pci_addr.a_mid << 32 |
865 range->pci_addr.a_lo;
866
867 /* Assume these are both zero */
868 if ((pci_addr != 0) || (isa_addr != 0)) {
869 printk(KERN_ERR "unexpected isa to pci mapping: %s\n",
870 __FUNCTION__);
871 return;
872 }
873
874 size = PAGE_ALIGN(range->size);
875
876 __ioremap_explicit(phb_io_base_phys,
877 (unsigned long) phb_io_base_virt,
dfbacdc1 878 size, _PAGE_NO_CACHE | _PAGE_GUARDED);
1da177e4
LT		 879 }
880}
881
882void __devinit pci_process_bridge_OF_ranges(struct pci_controller *hose,
f7abbc19 883 struct device_node *dev, int prim)
1da177e4 884{
f7abbc19 885 unsigned int *ranges, pci_space;
1da177e4
LT		 886 unsigned long size;
887 int rlen = 0;
888 int memno = 0;
889 struct resource *res;
890 int np, na = prom_n_addr_cells(dev);
891 unsigned long pci_addr, cpu_phys_addr;
892
893 np = na + 5;
894
895 /* From "PCI Binding to 1275"
896 * The ranges property is laid out as an array of elements,
897 * each of which comprises:
898 * cells 0 - 2: a PCI address
899 * cells 3 or 3+4: a CPU physical address
900 * (size depending on dev->n_addr_cells)
901 * cells 4+5 or 5+6: the size of the range
902 */
903 rlen = 0;
904 hose->io_base_phys = 0;
905 ranges = (unsigned int *) get_property(dev, "ranges", &rlen);
906 while ((rlen -= np * sizeof(unsigned int)) >= 0) {
907 res = NULL;
f7abbc19
PM		 908 pci_space = ranges[0];
909 pci_addr = ((unsigned long)ranges[1] << 32) | ranges[2];
1da177e4
LT		 910
911 cpu_phys_addr = ranges[3];
f7abbc19
PM		 912 if (na >= 2)
913 cpu_phys_addr = (cpu_phys_addr << 32) | ranges[4];
1da177e4 914
f7abbc19
PM		 915 size = ((unsigned long)ranges[na+3] << 32) | ranges[na+4];
916 ranges += np;
1da177e4
LT		 917 if (size == 0)
918 continue;
f7abbc19
PM		 919
920 /* Now consume following elements while they are contiguous */
921 while (rlen >= np * sizeof(unsigned int)) {
922 unsigned long addr, phys;
923
924 if (ranges[0] != pci_space)
925 break;
926 addr = ((unsigned long)ranges[1] << 32) | ranges[2];
927 phys = ranges[3];
928 if (na >= 2)
929 phys = (phys << 32) | ranges[4];
930 if (addr != pci_addr + size ||
931 phys != cpu_phys_addr + size)
932 break;
933
934 size += ((unsigned long)ranges[na+3] << 32)
935 | ranges[na+4];
936 ranges += np;
937 rlen -= np * sizeof(unsigned int);
938 }
939
940 switch ((pci_space >> 24) & 0x3) {
1da177e4
LT		 941 case 1: /* I/O space */
942 hose->io_base_phys = cpu_phys_addr;
943 hose->pci_io_size = size;
944
945 res = &hose->io_resource;
946 res->flags = IORESOURCE_IO;
947 res->start = pci_addr;
948 DBG("phb%d: IO 0x%lx -> 0x%lx\n", hose->global_number,
949 res->start, res->start + size - 1);
950 break;
951 case 2: /* memory space */
952 memno = 0;
953 while (memno < 3 && hose->mem_resources[memno].flags)
954 ++memno;
955
956 if (memno == 0)
957 hose->pci_mem_offset = cpu_phys_addr - pci_addr;
958 if (memno < 3) {
959 res = &hose->mem_resources[memno];
960 res->flags = IORESOURCE_MEM;
961 res->start = cpu_phys_addr;
962 DBG("phb%d: MEM 0x%lx -> 0x%lx\n", hose->global_number,
963 res->start, res->start + size - 1);
964 }
965 break;
966 }
967 if (res != NULL) {
968 res->name = dev->full_name;
969 res->end = res->start + size - 1;
970 res->parent = NULL;
971 res->sibling = NULL;
972 res->child = NULL;
973 }
1da177e4
LT		 974 }
975}
976
977void __init pci_setup_phb_io(struct pci_controller *hose, int primary)
978{
979 unsigned long size = hose->pci_io_size;
980 unsigned long io_virt_offset;
981 struct resource *res;
982 struct device_node *isa_dn;
983
984 hose->io_base_virt = reserve_phb_iospace(size);
985 DBG("phb%d io_base_phys 0x%lx io_base_virt 0x%lx\n",
986 hose->global_number, hose->io_base_phys,
987 (unsigned long) hose->io_base_virt);
988
989 if (primary) {
990 pci_io_base = (unsigned long)hose->io_base_virt;
991 isa_dn = of_find_node_by_type(NULL, "isa");
992 if (isa_dn) {
993 isa_io_base = pci_io_base;
994 pci_process_ISA_OF_ranges(isa_dn, hose->io_base_phys,
995 hose->io_base_virt);
996 of_node_put(isa_dn);
997 /* Allow all IO */
998 io_page_mask = -1;
999 }
1000 }
1001
1002 io_virt_offset = (unsigned long)hose->io_base_virt - pci_io_base;
1003 res = &hose->io_resource;
1004 res->start += io_virt_offset;
1005 res->end += io_virt_offset;
1006}
1007
1008void __devinit pci_setup_phb_io_dynamic(struct pci_controller *hose,
1009 int primary)
1010{
1011 unsigned long size = hose->pci_io_size;
1012 unsigned long io_virt_offset;
1013 struct resource *res;
1014
1015 hose->io_base_virt = __ioremap(hose->io_base_phys, size,
dfbacdc1 1016 _PAGE_NO_CACHE | _PAGE_GUARDED);
1da177e4
LT		 1017 DBG("phb%d io_base_phys 0x%lx io_base_virt 0x%lx\n",
1018 hose->global_number, hose->io_base_phys,
1019 (unsigned long) hose->io_base_virt);
1020
1021 if (primary)
1022 pci_io_base = (unsigned long)hose->io_base_virt;
1023
1024 io_virt_offset = (unsigned long)hose->io_base_virt - pci_io_base;
1025 res = &hose->io_resource;
1026 res->start += io_virt_offset;
1027 res->end += io_virt_offset;
1028}
1029
1030
1031static int get_bus_io_range(struct pci_bus *bus, unsigned long *start_phys,
1032 unsigned long *start_virt, unsigned long *size)
1033{
1034 struct pci_controller *hose = pci_bus_to_host(bus);
1035 struct pci_bus_region region;
1036 struct resource *res;
1037
1038 if (bus->self) {
1039 res = bus->resource[0];
1040 pcibios_resource_to_bus(bus->self, &region, res);
1041 *start_phys = hose->io_base_phys + region.start;
1042 *start_virt = (unsigned long) hose->io_base_virt +
1043 region.start;
1044 if (region.end > region.start)
1045 *size = region.end - region.start + 1;
1046 else {
1047 printk("%s(): unexpected region 0x%lx->0x%lx\n",
1048 __FUNCTION__, region.start, region.end);
1049 return 1;
1050 }
1051
1052 } else {
1053 /* Root Bus */
1054 res = &hose->io_resource;
1055 *start_phys = hose->io_base_phys;
1056 *start_virt = (unsigned long) hose->io_base_virt;
1057 if (res->end > res->start)
1058 *size = res->end - res->start + 1;
1059 else {
1060 printk("%s(): unexpected region 0x%lx->0x%lx\n",
1061 __FUNCTION__, res->start, res->end);
1062 return 1;
1063 }
1064 }
1065
1066 return 0;
1067}
1068
1069int unmap_bus_range(struct pci_bus *bus)
1070{
1071 unsigned long start_phys;
1072 unsigned long start_virt;
1073 unsigned long size;
1074
1075 if (!bus) {
1076 printk(KERN_ERR "%s() expected bus\n", __FUNCTION__);
1077 return 1;
1078 }
1079
1080 if (get_bus_io_range(bus, &start_phys, &start_virt, &size))
1081 return 1;
1082 if (iounmap_explicit((void __iomem *) start_virt, size))
1083 return 1;
1084
1085 return 0;
1086}
1087EXPORT_SYMBOL(unmap_bus_range);
1088
1089int remap_bus_range(struct pci_bus *bus)
1090{
1091 unsigned long start_phys;
1092 unsigned long start_virt;
1093 unsigned long size;
1094
1095 if (!bus) {
1096 printk(KERN_ERR "%s() expected bus\n", __FUNCTION__);
1097 return 1;
1098 }
1099
1100
1101 if (get_bus_io_range(bus, &start_phys, &start_virt, &size))
1102 return 1;
1103 printk("mapping IO %lx -> %lx, size: %lx\n", start_phys, start_virt, size);
dfbacdc1
BH		 1104 if (__ioremap_explicit(start_phys, start_virt, size,
1105 _PAGE_NO_CACHE | _PAGE_GUARDED))
1da177e4
LT		 1106 return 1;
1107
1108 return 0;
1109}
1110EXPORT_SYMBOL(remap_bus_range);
1111
1112void phbs_remap_io(void)
1113{
1114 struct pci_controller *hose, *tmp;
1115
1116 list_for_each_entry_safe(hose, tmp, &hose_list, list_node)
1117 remap_bus_range(hose->bus);
1118}
1119
1120/*
1121 * ppc64 can have multifunction devices that do not respond to function 0.
1122 * In this case we must scan all functions.
4267292b
PM		 1123 * XXX this can go now, we use the OF device tree in all the
1124 * cases that caused problems. -- paulus
1da177e4
LT		 1125 */
1126int pcibios_scan_all_fns(struct pci_bus *bus, int devfn)
1127{
4267292b
PM		 1128 return 0;
1129}
1da177e4 1130
4267292b
PM		 1131static void __devinit fixup_resource(struct resource *res, struct pci_dev *dev)
1132{
1133 struct pci_controller *hose = pci_bus_to_host(dev->bus);
1134 unsigned long start, end, mask, offset;
1da177e4 1135
4267292b
PM		 1136 if (res->flags & IORESOURCE_IO) {
1137 offset = (unsigned long)hose->io_base_virt - pci_io_base;
1da177e4 1138
4267292b
PM		 1139 start = res->start += offset;
1140 end = res->end += offset;
1da177e4 1141
4267292b
PM		 1142 /* Need to allow IO access to pages that are in the
1143 ISA range */
1144 if (start < MAX_ISA_PORT) {
1145 if (end > MAX_ISA_PORT)
1146 end = MAX_ISA_PORT;
1147
1148 start >>= PAGE_SHIFT;
1149 end >>= PAGE_SHIFT;
1da177e4 1150
4267292b
PM		 1151 /* get the range of pages for the map */
1152 mask = ((1 << (end+1)) - 1) ^ ((1 << start) - 1);
1153 io_page_mask |= mask;
1154 }
1155 } else if (res->flags & IORESOURCE_MEM) {
1156 res->start += hose->pci_mem_offset;
1157 res->end += hose->pci_mem_offset;
1158 }
1159}
1da177e4
LT		 1160
1161void __devinit pcibios_fixup_device_resources(struct pci_dev *dev,
4267292b 1162 struct pci_bus *bus)
1da177e4
LT		 1163{
1164 /* Update device resources. */
1da177e4
LT		 1165 int i;
1166
4267292b
PM		 1167 for (i = 0; i < PCI_NUM_RESOURCES; i++)
1168 if (dev->resource[i].flags)
1169 fixup_resource(&dev->resource[i], dev);
1da177e4
LT		 1170}
1171EXPORT_SYMBOL(pcibios_fixup_device_resources);
1172
4267292b 1173static void __devinit do_bus_setup(struct pci_bus *bus)
1da177e4 1174{
4267292b 1175 struct pci_dev *dev;
1da177e4 1176
4267292b 1177 ppc_md.iommu_bus_setup(bus);
1da177e4 1178
4267292b
PM		 1179 list_for_each_entry(dev, &bus->devices, bus_list)
1180 ppc_md.iommu_dev_setup(dev);
1da177e4 1181
4267292b
PM		 1182 if (ppc_md.irq_bus_setup)
1183 ppc_md.irq_bus_setup(bus);
1184}
1da177e4 1185
4267292b
PM		 1186void __devinit pcibios_fixup_bus(struct pci_bus *bus)
1187{
1188 struct pci_dev *dev = bus->self;
1189
1190 if (dev && pci_probe_only &&
1191 (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
1da177e4
LT		 1192 /* This is a subordinate bridge */
1193
1194 pci_read_bridge_bases(bus);
1195 pcibios_fixup_device_resources(dev, bus);
1196 }
1197
4267292b 1198 do_bus_setup(bus);
dad32bbf 1199
1da177e4
LT		 1200 if (!pci_probe_only)
1201 return;
1202
4267292b 1203 list_for_each_entry(dev, &bus->devices, bus_list)
1da177e4
LT		 1204 if ((dev->class >> 8) != PCI_CLASS_BRIDGE_PCI)
1205 pcibios_fixup_device_resources(dev, bus);
1da177e4
LT		 1206}
1207EXPORT_SYMBOL(pcibios_fixup_bus);
1208
1209/*
1210 * Reads the interrupt pin to determine if interrupt is use by card.
1211 * If the interrupt is used, then gets the interrupt line from the
1212 * openfirmware and sets it in the pci_dev and pci_config line.
1213 */
1214int pci_read_irq_line(struct pci_dev *pci_dev)
1215{
1216 u8 intpin;
1217 struct device_node *node;
1218
1219 pci_read_config_byte(pci_dev, PCI_INTERRUPT_PIN, &intpin);
1220 if (intpin == 0)
1221 return 0;
1222
1223 node = pci_device_to_OF_node(pci_dev);
1224 if (node == NULL)
1225 return -1;
1226
1227 if (node->n_intrs == 0)
1228 return -1;
1229
1230 pci_dev->irq = node->intrs[0].line;
1231
1232 pci_write_config_byte(pci_dev, PCI_INTERRUPT_LINE, pci_dev->irq);
1233
1234 return 0;
1235}
1236EXPORT_SYMBOL(pci_read_irq_line);
1237
2311b1f2
ME		 1238void pci_resource_to_user(const struct pci_dev *dev, int bar,
1239 const struct resource *rsrc,
1240 u64 *start, u64 *end)
1241{
1242 struct pci_controller *hose = pci_bus_to_host(dev->bus);
1243 unsigned long offset = 0;
1244
1245 if (hose == NULL)
1246 return;
1247
1248 if (rsrc->flags & IORESOURCE_IO)
1249 offset = pci_io_base - (unsigned long)hose->io_base_virt +
1250 hose->io_base_phys;
1251
1252 *start = rsrc->start + offset;
1253 *end = rsrc->end + offset;
1254}
1255
1da177e4 1256#endif /* CONFIG_PPC_MULTIPLATFORM */
b2ad7b5e
PM		 1257
1258
1259#define IOBASE_BRIDGE_NUMBER 0
1260#define IOBASE_MEMORY 1
1261#define IOBASE_IO 2
1262#define IOBASE_ISA_IO 3
1263#define IOBASE_ISA_MEM 4
1264
1265long sys_pciconfig_iobase(long which, unsigned long in_bus,
1266 unsigned long in_devfn)
1267{
1268 struct pci_controller* hose;
1269 struct list_head *ln;
1270 struct pci_bus *bus = NULL;
1271 struct device_node *hose_node;
1272
1273 /* Argh ! Please forgive me for that hack, but that's the
1274 * simplest way to get existing XFree to not lockup on some
1275 * G5 machines... So when something asks for bus 0 io base
1276 * (bus 0 is HT root), we return the AGP one instead.
1277 */
1278#ifdef CONFIG_PPC_PMAC
1279 if (systemcfg->platform == PLATFORM_POWERMAC &&
1280 machine_is_compatible("MacRISC4"))
1281 if (in_bus == 0)
1282 in_bus = 0xf0;
1283#endif /* CONFIG_PPC_PMAC */
1284
1285 /* That syscall isn't quite compatible with PCI domains, but it's
1286 * used on pre-domains setup. We return the first match
1287 */
1288
1289 for (ln = pci_root_buses.next; ln != &pci_root_buses; ln = ln->next) {
1290 bus = pci_bus_b(ln);
1291 if (in_bus >= bus->number && in_bus < (bus->number + bus->subordinate))
1292 break;
1293 bus = NULL;
1294 }
1295 if (bus == NULL || bus->sysdata == NULL)
1296 return -ENODEV;
1297
1298 hose_node = (struct device_node *)bus->sysdata;
1299 hose = PCI_DN(hose_node)->phb;
1300
1301 switch (which) {
1302 case IOBASE_BRIDGE_NUMBER:
1303 return (long)hose->first_busno;
1304 case IOBASE_MEMORY:
1305 return (long)hose->pci_mem_offset;
1306 case IOBASE_IO:
1307 return (long)hose->io_base_phys;
1308 case IOBASE_ISA_IO:
1309 return (long)isa_io_base;
1310 case IOBASE_ISA_MEM:
1311 return -EINVAL;
1312 }
1313
1314 return -EOPNOTSUPP;
1315}
Linux 6.x block layer and io_uring tree(s)