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1da177e4 LT |
1 | /* |
2 | * Port for PPC64 David Engebretsen, IBM Corp. | |
3 | * Contains common pci routines for ppc64 platform, pSeries and iSeries brands. | |
4 | * | |
5 | * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM | |
6 | * Rework, based on alpha PCI code. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License | |
10 | * as published by the Free Software Foundation; either version | |
11 | * 2 of the License, or (at your option) any later version. | |
12 | */ | |
13 | ||
14 | #undef DEBUG | |
15 | ||
16 | #include <linux/config.h> | |
17 | #include <linux/kernel.h> | |
18 | #include <linux/pci.h> | |
19 | #include <linux/string.h> | |
20 | #include <linux/init.h> | |
21 | #include <linux/bootmem.h> | |
22 | #include <linux/mm.h> | |
23 | #include <linux/list.h> | |
b2ad7b5e | 24 | #include <linux/syscalls.h> |
1da177e4 LT |
25 | |
26 | #include <asm/processor.h> | |
27 | #include <asm/io.h> | |
28 | #include <asm/prom.h> | |
29 | #include <asm/pci-bridge.h> | |
30 | #include <asm/byteorder.h> | |
31 | #include <asm/irq.h> | |
32 | #include <asm/machdep.h> | |
33 | #include <asm/udbg.h> | |
d387899f | 34 | #include <asm/ppc-pci.h> |
1da177e4 LT |
35 | |
36 | #ifdef DEBUG | |
37 | #define DBG(fmt...) udbg_printf(fmt) | |
38 | #else | |
39 | #define DBG(fmt...) | |
40 | #endif | |
41 | ||
42 | unsigned long pci_probe_only = 1; | |
43 | unsigned long pci_assign_all_buses = 0; | |
44 | ||
45 | /* | |
46 | * legal IO pages under MAX_ISA_PORT. This is to ensure we don't touch | |
47 | * devices we don't have access to. | |
48 | */ | |
49 | unsigned long io_page_mask; | |
50 | ||
51 | EXPORT_SYMBOL(io_page_mask); | |
52 | ||
4267292b PM |
53 | #ifdef CONFIG_PPC_MULTIPLATFORM |
54 | static void fixup_resource(struct resource *res, struct pci_dev *dev); | |
55 | static void do_bus_setup(struct pci_bus *bus); | |
56 | #endif | |
1da177e4 LT |
57 | |
58 | unsigned int pcibios_assign_all_busses(void) | |
59 | { | |
60 | return pci_assign_all_buses; | |
61 | } | |
62 | ||
63 | /* pci_io_base -- the base address from which io bars are offsets. | |
64 | * This is the lowest I/O base address (so bar values are always positive), | |
65 | * and it *must* be the start of ISA space if an ISA bus exists because | |
66 | * ISA drivers use hard coded offsets. If no ISA bus exists a dummy | |
67 | * page is mapped and isa_io_limit prevents access to it. | |
68 | */ | |
69 | unsigned long isa_io_base; /* NULL if no ISA bus */ | |
70 | EXPORT_SYMBOL(isa_io_base); | |
71 | unsigned long pci_io_base; | |
72 | EXPORT_SYMBOL(pci_io_base); | |
73 | ||
74 | void iSeries_pcibios_init(void); | |
75 | ||
76 | LIST_HEAD(hose_list); | |
77 | ||
78 | struct dma_mapping_ops pci_dma_ops; | |
79 | EXPORT_SYMBOL(pci_dma_ops); | |
80 | ||
81 | int global_phb_number; /* Global phb counter */ | |
82 | ||
83 | /* Cached ISA bridge dev. */ | |
84 | struct pci_dev *ppc64_isabridge_dev = NULL; | |
85 | ||
86 | static void fixup_broken_pcnet32(struct pci_dev* dev) | |
87 | { | |
88 | if ((dev->class>>8 == PCI_CLASS_NETWORK_ETHERNET)) { | |
89 | dev->vendor = PCI_VENDOR_ID_AMD; | |
90 | pci_write_config_word(dev, PCI_VENDOR_ID, PCI_VENDOR_ID_AMD); | |
1da177e4 LT |
91 | } |
92 | } | |
93 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TRIDENT, PCI_ANY_ID, fixup_broken_pcnet32); | |
94 | ||
95 | void pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region, | |
96 | struct resource *res) | |
97 | { | |
98 | unsigned long offset = 0; | |
99 | struct pci_controller *hose = pci_bus_to_host(dev->bus); | |
100 | ||
101 | if (!hose) | |
102 | return; | |
103 | ||
104 | if (res->flags & IORESOURCE_IO) | |
105 | offset = (unsigned long)hose->io_base_virt - pci_io_base; | |
106 | ||
107 | if (res->flags & IORESOURCE_MEM) | |
108 | offset = hose->pci_mem_offset; | |
109 | ||
110 | region->start = res->start - offset; | |
111 | region->end = res->end - offset; | |
112 | } | |
113 | ||
43c34735 DB |
114 | void pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res, |
115 | struct pci_bus_region *region) | |
116 | { | |
117 | unsigned long offset = 0; | |
118 | struct pci_controller *hose = pci_bus_to_host(dev->bus); | |
119 | ||
120 | if (!hose) | |
121 | return; | |
122 | ||
123 | if (res->flags & IORESOURCE_IO) | |
124 | offset = (unsigned long)hose->io_base_virt - pci_io_base; | |
125 | ||
126 | if (res->flags & IORESOURCE_MEM) | |
127 | offset = hose->pci_mem_offset; | |
128 | ||
129 | res->start = region->start + offset; | |
130 | res->end = region->end + offset; | |
131 | } | |
132 | ||
1da177e4 LT |
133 | #ifdef CONFIG_HOTPLUG |
134 | EXPORT_SYMBOL(pcibios_resource_to_bus); | |
43c34735 | 135 | EXPORT_SYMBOL(pcibios_bus_to_resource); |
1da177e4 LT |
136 | #endif |
137 | ||
138 | /* | |
139 | * We need to avoid collisions with `mirrored' VGA ports | |
140 | * and other strange ISA hardware, so we always want the | |
141 | * addresses to be allocated in the 0x000-0x0ff region | |
142 | * modulo 0x400. | |
143 | * | |
144 | * Why? Because some silly external IO cards only decode | |
145 | * the low 10 bits of the IO address. The 0x00-0xff region | |
146 | * is reserved for motherboard devices that decode all 16 | |
147 | * bits, so it's ok to allocate at, say, 0x2800-0x28ff, | |
148 | * but we want to try to avoid allocating at 0x2900-0x2bff | |
149 | * which might have be mirrored at 0x0100-0x03ff.. | |
150 | */ | |
151 | void pcibios_align_resource(void *data, struct resource *res, | |
152 | unsigned long size, unsigned long align) | |
153 | { | |
154 | struct pci_dev *dev = data; | |
155 | struct pci_controller *hose = pci_bus_to_host(dev->bus); | |
156 | unsigned long start = res->start; | |
157 | unsigned long alignto; | |
158 | ||
159 | if (res->flags & IORESOURCE_IO) { | |
160 | unsigned long offset = (unsigned long)hose->io_base_virt - | |
161 | pci_io_base; | |
162 | /* Make sure we start at our min on all hoses */ | |
163 | if (start - offset < PCIBIOS_MIN_IO) | |
164 | start = PCIBIOS_MIN_IO + offset; | |
165 | ||
166 | /* | |
167 | * Put everything into 0x00-0xff region modulo 0x400 | |
168 | */ | |
169 | if (start & 0x300) | |
170 | start = (start + 0x3ff) & ~0x3ff; | |
171 | ||
172 | } else if (res->flags & IORESOURCE_MEM) { | |
173 | /* Make sure we start at our min on all hoses */ | |
174 | if (start - hose->pci_mem_offset < PCIBIOS_MIN_MEM) | |
175 | start = PCIBIOS_MIN_MEM + hose->pci_mem_offset; | |
176 | ||
177 | /* Align to multiple of size of minimum base. */ | |
178 | alignto = max(0x1000UL, align); | |
179 | start = ALIGN(start, alignto); | |
180 | } | |
181 | ||
182 | res->start = start; | |
183 | } | |
184 | ||
185 | static DEFINE_SPINLOCK(hose_spinlock); | |
186 | ||
187 | /* | |
188 | * pci_controller(phb) initialized common variables. | |
189 | */ | |
190 | void __devinit pci_setup_pci_controller(struct pci_controller *hose) | |
191 | { | |
192 | memset(hose, 0, sizeof(struct pci_controller)); | |
193 | ||
194 | spin_lock(&hose_spinlock); | |
195 | hose->global_number = global_phb_number++; | |
196 | list_add_tail(&hose->list_node, &hose_list); | |
197 | spin_unlock(&hose_spinlock); | |
198 | } | |
199 | ||
200 | static void __init pcibios_claim_one_bus(struct pci_bus *b) | |
201 | { | |
202 | struct pci_dev *dev; | |
203 | struct pci_bus *child_bus; | |
204 | ||
205 | list_for_each_entry(dev, &b->devices, bus_list) { | |
206 | int i; | |
207 | ||
208 | for (i = 0; i < PCI_NUM_RESOURCES; i++) { | |
209 | struct resource *r = &dev->resource[i]; | |
210 | ||
211 | if (r->parent || !r->start || !r->flags) | |
212 | continue; | |
213 | pci_claim_resource(dev, i); | |
214 | } | |
215 | } | |
216 | ||
217 | list_for_each_entry(child_bus, &b->children, node) | |
218 | pcibios_claim_one_bus(child_bus); | |
219 | } | |
220 | ||
221 | #ifndef CONFIG_PPC_ISERIES | |
222 | static void __init pcibios_claim_of_setup(void) | |
223 | { | |
224 | struct pci_bus *b; | |
225 | ||
226 | list_for_each_entry(b, &pci_root_buses, node) | |
227 | pcibios_claim_one_bus(b); | |
228 | } | |
229 | #endif | |
230 | ||
4267292b PM |
231 | #ifdef CONFIG_PPC_MULTIPLATFORM |
232 | static u32 get_int_prop(struct device_node *np, const char *name, u32 def) | |
233 | { | |
234 | u32 *prop; | |
235 | int len; | |
236 | ||
237 | prop = (u32 *) get_property(np, name, &len); | |
238 | if (prop && len >= 4) | |
239 | return *prop; | |
240 | return def; | |
241 | } | |
242 | ||
243 | static unsigned int pci_parse_of_flags(u32 addr0) | |
244 | { | |
245 | unsigned int flags = 0; | |
246 | ||
247 | if (addr0 & 0x02000000) { | |
d79e743e PM |
248 | flags = IORESOURCE_MEM | PCI_BASE_ADDRESS_SPACE_MEMORY; |
249 | flags |= (addr0 >> 22) & PCI_BASE_ADDRESS_MEM_TYPE_64; | |
250 | flags |= (addr0 >> 28) & PCI_BASE_ADDRESS_MEM_TYPE_1M; | |
4267292b | 251 | if (addr0 & 0x40000000) |
d79e743e PM |
252 | flags |= IORESOURCE_PREFETCH |
253 | | PCI_BASE_ADDRESS_MEM_PREFETCH; | |
4267292b | 254 | } else if (addr0 & 0x01000000) |
d79e743e | 255 | flags = IORESOURCE_IO | PCI_BASE_ADDRESS_SPACE_IO; |
4267292b PM |
256 | return flags; |
257 | } | |
258 | ||
259 | #define GET_64BIT(prop, i) ((((u64) (prop)[(i)]) << 32) | (prop)[(i)+1]) | |
260 | ||
261 | static void pci_parse_of_addrs(struct device_node *node, struct pci_dev *dev) | |
262 | { | |
263 | u64 base, size; | |
264 | unsigned int flags; | |
265 | struct resource *res; | |
266 | u32 *addrs, i; | |
267 | int proplen; | |
268 | ||
269 | addrs = (u32 *) get_property(node, "assigned-addresses", &proplen); | |
270 | if (!addrs) | |
271 | return; | |
272 | for (; proplen >= 20; proplen -= 20, addrs += 5) { | |
273 | flags = pci_parse_of_flags(addrs[0]); | |
274 | if (!flags) | |
275 | continue; | |
276 | base = GET_64BIT(addrs, 1); | |
277 | size = GET_64BIT(addrs, 3); | |
278 | if (!size) | |
279 | continue; | |
280 | i = addrs[0] & 0xff; | |
281 | if (PCI_BASE_ADDRESS_0 <= i && i <= PCI_BASE_ADDRESS_5) { | |
282 | res = &dev->resource[(i - PCI_BASE_ADDRESS_0) >> 2]; | |
283 | } else if (i == dev->rom_base_reg) { | |
284 | res = &dev->resource[PCI_ROM_RESOURCE]; | |
285 | flags |= IORESOURCE_READONLY | IORESOURCE_CACHEABLE; | |
286 | } else { | |
287 | printk(KERN_ERR "PCI: bad cfg reg num 0x%x\n", i); | |
288 | continue; | |
289 | } | |
290 | res->start = base; | |
291 | res->end = base + size - 1; | |
292 | res->flags = flags; | |
293 | res->name = pci_name(dev); | |
294 | fixup_resource(res, dev); | |
295 | } | |
296 | } | |
297 | ||
ead83717 JR |
298 | struct pci_dev *of_create_pci_dev(struct device_node *node, |
299 | struct pci_bus *bus, int devfn) | |
4267292b PM |
300 | { |
301 | struct pci_dev *dev; | |
302 | const char *type; | |
303 | ||
304 | dev = kmalloc(sizeof(struct pci_dev), GFP_KERNEL); | |
305 | if (!dev) | |
306 | return NULL; | |
307 | type = get_property(node, "device_type", NULL); | |
308 | if (type == NULL) | |
309 | type = ""; | |
310 | ||
311 | memset(dev, 0, sizeof(struct pci_dev)); | |
312 | dev->bus = bus; | |
313 | dev->sysdata = node; | |
314 | dev->dev.parent = bus->bridge; | |
315 | dev->dev.bus = &pci_bus_type; | |
316 | dev->devfn = devfn; | |
317 | dev->multifunction = 0; /* maybe a lie? */ | |
318 | ||
319 | dev->vendor = get_int_prop(node, "vendor-id", 0xffff); | |
320 | dev->device = get_int_prop(node, "device-id", 0xffff); | |
321 | dev->subsystem_vendor = get_int_prop(node, "subsystem-vendor-id", 0); | |
322 | dev->subsystem_device = get_int_prop(node, "subsystem-id", 0); | |
323 | ||
324 | dev->cfg_size = 256; /*pci_cfg_space_size(dev);*/ | |
325 | ||
326 | sprintf(pci_name(dev), "%04x:%02x:%02x.%d", pci_domain_nr(bus), | |
327 | dev->bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn)); | |
328 | dev->class = get_int_prop(node, "class-code", 0); | |
329 | ||
330 | dev->current_state = 4; /* unknown power state */ | |
331 | ||
332 | if (!strcmp(type, "pci")) { | |
333 | /* a PCI-PCI bridge */ | |
334 | dev->hdr_type = PCI_HEADER_TYPE_BRIDGE; | |
335 | dev->rom_base_reg = PCI_ROM_ADDRESS1; | |
336 | } else if (!strcmp(type, "cardbus")) { | |
337 | dev->hdr_type = PCI_HEADER_TYPE_CARDBUS; | |
338 | } else { | |
339 | dev->hdr_type = PCI_HEADER_TYPE_NORMAL; | |
340 | dev->rom_base_reg = PCI_ROM_ADDRESS; | |
341 | dev->irq = NO_IRQ; | |
342 | if (node->n_intrs > 0) { | |
343 | dev->irq = node->intrs[0].line; | |
344 | pci_write_config_byte(dev, PCI_INTERRUPT_LINE, | |
345 | dev->irq); | |
346 | } | |
347 | } | |
348 | ||
349 | pci_parse_of_addrs(node, dev); | |
350 | ||
351 | pci_device_add(dev, bus); | |
352 | ||
353 | /* XXX pci_scan_msi_device(dev); */ | |
354 | ||
355 | return dev; | |
356 | } | |
ead83717 | 357 | EXPORT_SYMBOL(of_create_pci_dev); |
4267292b | 358 | |
ead83717 | 359 | void __devinit of_scan_bus(struct device_node *node, |
4267292b PM |
360 | struct pci_bus *bus) |
361 | { | |
362 | struct device_node *child = NULL; | |
363 | u32 *reg; | |
364 | int reglen, devfn; | |
365 | struct pci_dev *dev; | |
366 | ||
367 | while ((child = of_get_next_child(node, child)) != NULL) { | |
368 | reg = (u32 *) get_property(child, "reg", ®len); | |
369 | if (reg == NULL || reglen < 20) | |
370 | continue; | |
371 | devfn = (reg[0] >> 8) & 0xff; | |
372 | /* create a new pci_dev for this device */ | |
373 | dev = of_create_pci_dev(child, bus, devfn); | |
374 | if (!dev) | |
375 | continue; | |
376 | if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE || | |
377 | dev->hdr_type == PCI_HEADER_TYPE_CARDBUS) | |
378 | of_scan_pci_bridge(child, dev); | |
379 | } | |
380 | ||
381 | do_bus_setup(bus); | |
382 | } | |
ead83717 | 383 | EXPORT_SYMBOL(of_scan_bus); |
4267292b | 384 | |
ead83717 JR |
385 | void __devinit of_scan_pci_bridge(struct device_node *node, |
386 | struct pci_dev *dev) | |
4267292b PM |
387 | { |
388 | struct pci_bus *bus; | |
389 | u32 *busrange, *ranges; | |
390 | int len, i, mode; | |
391 | struct resource *res; | |
392 | unsigned int flags; | |
393 | u64 size; | |
394 | ||
395 | /* parse bus-range property */ | |
396 | busrange = (u32 *) get_property(node, "bus-range", &len); | |
397 | if (busrange == NULL || len != 8) { | |
398 | printk(KERN_ERR "Can't get bus-range for PCI-PCI bridge %s\n", | |
399 | node->full_name); | |
400 | return; | |
401 | } | |
402 | ranges = (u32 *) get_property(node, "ranges", &len); | |
403 | if (ranges == NULL) { | |
404 | printk(KERN_ERR "Can't get ranges for PCI-PCI bridge %s\n", | |
405 | node->full_name); | |
406 | return; | |
407 | } | |
408 | ||
409 | bus = pci_add_new_bus(dev->bus, dev, busrange[0]); | |
410 | if (!bus) { | |
411 | printk(KERN_ERR "Failed to create pci bus for %s\n", | |
412 | node->full_name); | |
413 | return; | |
414 | } | |
415 | ||
416 | bus->primary = dev->bus->number; | |
417 | bus->subordinate = busrange[1]; | |
418 | bus->bridge_ctl = 0; | |
419 | bus->sysdata = node; | |
420 | ||
421 | /* parse ranges property */ | |
422 | /* PCI #address-cells == 3 and #size-cells == 2 always */ | |
423 | res = &dev->resource[PCI_BRIDGE_RESOURCES]; | |
424 | for (i = 0; i < PCI_NUM_RESOURCES - PCI_BRIDGE_RESOURCES; ++i) { | |
425 | res->flags = 0; | |
426 | bus->resource[i] = res; | |
427 | ++res; | |
428 | } | |
429 | i = 1; | |
430 | for (; len >= 32; len -= 32, ranges += 8) { | |
431 | flags = pci_parse_of_flags(ranges[0]); | |
432 | size = GET_64BIT(ranges, 6); | |
433 | if (flags == 0 || size == 0) | |
434 | continue; | |
435 | if (flags & IORESOURCE_IO) { | |
436 | res = bus->resource[0]; | |
437 | if (res->flags) { | |
438 | printk(KERN_ERR "PCI: ignoring extra I/O range" | |
439 | " for bridge %s\n", node->full_name); | |
440 | continue; | |
441 | } | |
442 | } else { | |
443 | if (i >= PCI_NUM_RESOURCES - PCI_BRIDGE_RESOURCES) { | |
444 | printk(KERN_ERR "PCI: too many memory ranges" | |
445 | " for bridge %s\n", node->full_name); | |
446 | continue; | |
447 | } | |
448 | res = bus->resource[i]; | |
449 | ++i; | |
450 | } | |
451 | res->start = GET_64BIT(ranges, 1); | |
452 | res->end = res->start + size - 1; | |
453 | res->flags = flags; | |
454 | fixup_resource(res, dev); | |
455 | } | |
456 | sprintf(bus->name, "PCI Bus %04x:%02x", pci_domain_nr(bus), | |
457 | bus->number); | |
458 | ||
459 | mode = PCI_PROBE_NORMAL; | |
460 | if (ppc_md.pci_probe_mode) | |
461 | mode = ppc_md.pci_probe_mode(bus); | |
462 | if (mode == PCI_PROBE_DEVTREE) | |
463 | of_scan_bus(node, bus); | |
464 | else if (mode == PCI_PROBE_NORMAL) | |
465 | pci_scan_child_bus(bus); | |
466 | } | |
ead83717 | 467 | EXPORT_SYMBOL(of_scan_pci_bridge); |
4267292b PM |
468 | #endif /* CONFIG_PPC_MULTIPLATFORM */ |
469 | ||
ead83717 | 470 | void __devinit scan_phb(struct pci_controller *hose) |
4267292b PM |
471 | { |
472 | struct pci_bus *bus; | |
473 | struct device_node *node = hose->arch_data; | |
474 | int i, mode; | |
475 | struct resource *res; | |
476 | ||
477 | bus = pci_create_bus(NULL, hose->first_busno, hose->ops, node); | |
478 | if (bus == NULL) { | |
479 | printk(KERN_ERR "Failed to create bus for PCI domain %04x\n", | |
480 | hose->global_number); | |
481 | return; | |
482 | } | |
483 | bus->secondary = hose->first_busno; | |
484 | hose->bus = bus; | |
485 | ||
486 | bus->resource[0] = res = &hose->io_resource; | |
487 | if (res->flags && request_resource(&ioport_resource, res)) | |
488 | printk(KERN_ERR "Failed to request PCI IO region " | |
489 | "on PCI domain %04x\n", hose->global_number); | |
490 | ||
491 | for (i = 0; i < 3; ++i) { | |
492 | res = &hose->mem_resources[i]; | |
493 | bus->resource[i+1] = res; | |
494 | if (res->flags && request_resource(&iomem_resource, res)) | |
495 | printk(KERN_ERR "Failed to request PCI memory region " | |
496 | "on PCI domain %04x\n", hose->global_number); | |
497 | } | |
498 | ||
499 | mode = PCI_PROBE_NORMAL; | |
500 | #ifdef CONFIG_PPC_MULTIPLATFORM | |
501 | if (ppc_md.pci_probe_mode) | |
502 | mode = ppc_md.pci_probe_mode(bus); | |
503 | if (mode == PCI_PROBE_DEVTREE) { | |
504 | bus->subordinate = hose->last_busno; | |
505 | of_scan_bus(node, bus); | |
506 | } | |
507 | #endif /* CONFIG_PPC_MULTIPLATFORM */ | |
508 | if (mode == PCI_PROBE_NORMAL) | |
509 | hose->last_busno = bus->subordinate = pci_scan_child_bus(bus); | |
510 | pci_bus_add_devices(bus); | |
511 | } | |
512 | ||
1da177e4 LT |
513 | static int __init pcibios_init(void) |
514 | { | |
515 | struct pci_controller *hose, *tmp; | |
1da177e4 LT |
516 | |
517 | /* For now, override phys_mem_access_prot. If we need it, | |
518 | * later, we may move that initialization to each ppc_md | |
519 | */ | |
520 | ppc_md.phys_mem_access_prot = pci_phys_mem_access_prot; | |
521 | ||
522 | #ifdef CONFIG_PPC_ISERIES | |
523 | iSeries_pcibios_init(); | |
524 | #endif | |
525 | ||
526 | printk("PCI: Probing PCI hardware\n"); | |
527 | ||
528 | /* Scan all of the recorded PCI controllers. */ | |
4267292b PM |
529 | list_for_each_entry_safe(hose, tmp, &hose_list, list_node) |
530 | scan_phb(hose); | |
1da177e4 LT |
531 | |
532 | #ifndef CONFIG_PPC_ISERIES | |
533 | if (pci_probe_only) | |
534 | pcibios_claim_of_setup(); | |
535 | else | |
536 | /* FIXME: `else' will be removed when | |
537 | pci_assign_unassigned_resources() is able to work | |
538 | correctly with [partially] allocated PCI tree. */ | |
539 | pci_assign_unassigned_resources(); | |
540 | #endif /* !CONFIG_PPC_ISERIES */ | |
541 | ||
542 | /* Call machine dependent final fixup */ | |
543 | if (ppc_md.pcibios_fixup) | |
544 | ppc_md.pcibios_fixup(); | |
545 | ||
546 | /* Cache the location of the ISA bridge (if we have one) */ | |
547 | ppc64_isabridge_dev = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL); | |
548 | if (ppc64_isabridge_dev != NULL) | |
549 | printk("ISA bridge at %s\n", pci_name(ppc64_isabridge_dev)); | |
550 | ||
551 | printk("PCI: Probing PCI hardware done\n"); | |
552 | ||
553 | return 0; | |
554 | } | |
555 | ||
556 | subsys_initcall(pcibios_init); | |
557 | ||
558 | char __init *pcibios_setup(char *str) | |
559 | { | |
560 | return str; | |
561 | } | |
562 | ||
563 | int pcibios_enable_device(struct pci_dev *dev, int mask) | |
564 | { | |
565 | u16 cmd, oldcmd; | |
566 | int i; | |
567 | ||
568 | pci_read_config_word(dev, PCI_COMMAND, &cmd); | |
569 | oldcmd = cmd; | |
570 | ||
571 | for (i = 0; i < PCI_NUM_RESOURCES; i++) { | |
572 | struct resource *res = &dev->resource[i]; | |
573 | ||
574 | /* Only set up the requested stuff */ | |
575 | if (!(mask & (1<<i))) | |
576 | continue; | |
577 | ||
578 | if (res->flags & IORESOURCE_IO) | |
579 | cmd |= PCI_COMMAND_IO; | |
580 | if (res->flags & IORESOURCE_MEM) | |
581 | cmd |= PCI_COMMAND_MEMORY; | |
582 | } | |
583 | ||
584 | if (cmd != oldcmd) { | |
585 | printk(KERN_DEBUG "PCI: Enabling device: (%s), cmd %x\n", | |
586 | pci_name(dev), cmd); | |
587 | /* Enable the appropriate bits in the PCI command register. */ | |
588 | pci_write_config_word(dev, PCI_COMMAND, cmd); | |
589 | } | |
590 | return 0; | |
591 | } | |
592 | ||
593 | /* | |
594 | * Return the domain number for this bus. | |
595 | */ | |
596 | int pci_domain_nr(struct pci_bus *bus) | |
597 | { | |
598 | #ifdef CONFIG_PPC_ISERIES | |
599 | return 0; | |
600 | #else | |
601 | struct pci_controller *hose = pci_bus_to_host(bus); | |
602 | ||
603 | return hose->global_number; | |
604 | #endif | |
605 | } | |
606 | ||
607 | EXPORT_SYMBOL(pci_domain_nr); | |
608 | ||
609 | /* Decide whether to display the domain number in /proc */ | |
610 | int pci_proc_domain(struct pci_bus *bus) | |
611 | { | |
612 | #ifdef CONFIG_PPC_ISERIES | |
613 | return 0; | |
614 | #else | |
615 | struct pci_controller *hose = pci_bus_to_host(bus); | |
616 | return hose->buid; | |
617 | #endif | |
618 | } | |
619 | ||
620 | /* | |
621 | * Platform support for /proc/bus/pci/X/Y mmap()s, | |
622 | * modelled on the sparc64 implementation by Dave Miller. | |
623 | * -- paulus. | |
624 | */ | |
625 | ||
626 | /* | |
627 | * Adjust vm_pgoff of VMA such that it is the physical page offset | |
628 | * corresponding to the 32-bit pci bus offset for DEV requested by the user. | |
629 | * | |
630 | * Basically, the user finds the base address for his device which he wishes | |
631 | * to mmap. They read the 32-bit value from the config space base register, | |
632 | * add whatever PAGE_SIZE multiple offset they wish, and feed this into the | |
633 | * offset parameter of mmap on /proc/bus/pci/XXX for that device. | |
634 | * | |
635 | * Returns negative error code on failure, zero on success. | |
636 | */ | |
637 | static struct resource *__pci_mmap_make_offset(struct pci_dev *dev, | |
638 | unsigned long *offset, | |
639 | enum pci_mmap_state mmap_state) | |
640 | { | |
641 | struct pci_controller *hose = pci_bus_to_host(dev->bus); | |
642 | unsigned long io_offset = 0; | |
643 | int i, res_bit; | |
644 | ||
645 | if (hose == 0) | |
646 | return NULL; /* should never happen */ | |
647 | ||
648 | /* If memory, add on the PCI bridge address offset */ | |
649 | if (mmap_state == pci_mmap_mem) { | |
650 | *offset += hose->pci_mem_offset; | |
651 | res_bit = IORESOURCE_MEM; | |
652 | } else { | |
2311b1f2 | 653 | io_offset = (unsigned long)hose->io_base_virt - pci_io_base; |
1da177e4 LT |
654 | *offset += io_offset; |
655 | res_bit = IORESOURCE_IO; | |
656 | } | |
657 | ||
658 | /* | |
659 | * Check that the offset requested corresponds to one of the | |
660 | * resources of the device. | |
661 | */ | |
662 | for (i = 0; i <= PCI_ROM_RESOURCE; i++) { | |
663 | struct resource *rp = &dev->resource[i]; | |
664 | int flags = rp->flags; | |
665 | ||
666 | /* treat ROM as memory (should be already) */ | |
667 | if (i == PCI_ROM_RESOURCE) | |
668 | flags |= IORESOURCE_MEM; | |
669 | ||
670 | /* Active and same type? */ | |
671 | if ((flags & res_bit) == 0) | |
672 | continue; | |
673 | ||
674 | /* In the range of this resource? */ | |
675 | if (*offset < (rp->start & PAGE_MASK) || *offset > rp->end) | |
676 | continue; | |
677 | ||
678 | /* found it! construct the final physical address */ | |
679 | if (mmap_state == pci_mmap_io) | |
2311b1f2 | 680 | *offset += hose->io_base_phys - io_offset; |
1da177e4 LT |
681 | return rp; |
682 | } | |
683 | ||
684 | return NULL; | |
685 | } | |
686 | ||
687 | /* | |
688 | * Set vm_page_prot of VMA, as appropriate for this architecture, for a pci | |
689 | * device mapping. | |
690 | */ | |
691 | static pgprot_t __pci_mmap_set_pgprot(struct pci_dev *dev, struct resource *rp, | |
692 | pgprot_t protection, | |
693 | enum pci_mmap_state mmap_state, | |
694 | int write_combine) | |
695 | { | |
696 | unsigned long prot = pgprot_val(protection); | |
697 | ||
698 | /* Write combine is always 0 on non-memory space mappings. On | |
699 | * memory space, if the user didn't pass 1, we check for a | |
700 | * "prefetchable" resource. This is a bit hackish, but we use | |
701 | * this to workaround the inability of /sysfs to provide a write | |
702 | * combine bit | |
703 | */ | |
704 | if (mmap_state != pci_mmap_mem) | |
705 | write_combine = 0; | |
706 | else if (write_combine == 0) { | |
707 | if (rp->flags & IORESOURCE_PREFETCH) | |
708 | write_combine = 1; | |
709 | } | |
710 | ||
711 | /* XXX would be nice to have a way to ask for write-through */ | |
712 | prot |= _PAGE_NO_CACHE; | |
713 | if (write_combine) | |
714 | prot &= ~_PAGE_GUARDED; | |
715 | else | |
716 | prot |= _PAGE_GUARDED; | |
717 | ||
718 | printk("PCI map for %s:%lx, prot: %lx\n", pci_name(dev), rp->start, | |
719 | prot); | |
720 | ||
721 | return __pgprot(prot); | |
722 | } | |
723 | ||
724 | /* | |
725 | * This one is used by /dev/mem and fbdev who have no clue about the | |
726 | * PCI device, it tries to find the PCI device first and calls the | |
727 | * above routine | |
728 | */ | |
729 | pgprot_t pci_phys_mem_access_prot(struct file *file, | |
8b150478 | 730 | unsigned long pfn, |
1da177e4 LT |
731 | unsigned long size, |
732 | pgprot_t protection) | |
733 | { | |
734 | struct pci_dev *pdev = NULL; | |
735 | struct resource *found = NULL; | |
736 | unsigned long prot = pgprot_val(protection); | |
8b150478 | 737 | unsigned long offset = pfn << PAGE_SHIFT; |
1da177e4 LT |
738 | int i; |
739 | ||
8b150478 | 740 | if (page_is_ram(pfn)) |
1f8d419e | 741 | return __pgprot(prot); |
1da177e4 LT |
742 | |
743 | prot |= _PAGE_NO_CACHE | _PAGE_GUARDED; | |
744 | ||
745 | for_each_pci_dev(pdev) { | |
746 | for (i = 0; i <= PCI_ROM_RESOURCE; i++) { | |
747 | struct resource *rp = &pdev->resource[i]; | |
748 | int flags = rp->flags; | |
749 | ||
750 | /* Active and same type? */ | |
751 | if ((flags & IORESOURCE_MEM) == 0) | |
752 | continue; | |
753 | /* In the range of this resource? */ | |
754 | if (offset < (rp->start & PAGE_MASK) || | |
755 | offset > rp->end) | |
756 | continue; | |
757 | found = rp; | |
758 | break; | |
759 | } | |
760 | if (found) | |
761 | break; | |
762 | } | |
763 | if (found) { | |
764 | if (found->flags & IORESOURCE_PREFETCH) | |
765 | prot &= ~_PAGE_GUARDED; | |
766 | pci_dev_put(pdev); | |
767 | } | |
768 | ||
769 | DBG("non-PCI map for %lx, prot: %lx\n", offset, prot); | |
770 | ||
771 | return __pgprot(prot); | |
772 | } | |
773 | ||
774 | ||
775 | /* | |
776 | * Perform the actual remap of the pages for a PCI device mapping, as | |
777 | * appropriate for this architecture. The region in the process to map | |
778 | * is described by vm_start and vm_end members of VMA, the base physical | |
779 | * address is found in vm_pgoff. | |
780 | * The pci device structure is provided so that architectures may make mapping | |
781 | * decisions on a per-device or per-bus basis. | |
782 | * | |
783 | * Returns a negative error code on failure, zero on success. | |
784 | */ | |
785 | int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma, | |
786 | enum pci_mmap_state mmap_state, | |
787 | int write_combine) | |
788 | { | |
789 | unsigned long offset = vma->vm_pgoff << PAGE_SHIFT; | |
790 | struct resource *rp; | |
791 | int ret; | |
792 | ||
793 | rp = __pci_mmap_make_offset(dev, &offset, mmap_state); | |
794 | if (rp == NULL) | |
795 | return -EINVAL; | |
796 | ||
797 | vma->vm_pgoff = offset >> PAGE_SHIFT; | |
798 | vma->vm_flags |= VM_SHM | VM_LOCKED | VM_IO; | |
799 | vma->vm_page_prot = __pci_mmap_set_pgprot(dev, rp, | |
800 | vma->vm_page_prot, | |
801 | mmap_state, write_combine); | |
802 | ||
803 | ret = remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff, | |
804 | vma->vm_end - vma->vm_start, vma->vm_page_prot); | |
805 | ||
806 | return ret; | |
807 | } | |
808 | ||
809 | #ifdef CONFIG_PPC_MULTIPLATFORM | |
ff381d22 | 810 | static ssize_t pci_show_devspec(struct device *dev, struct device_attribute *attr, char *buf) |
1da177e4 LT |
811 | { |
812 | struct pci_dev *pdev; | |
813 | struct device_node *np; | |
814 | ||
815 | pdev = to_pci_dev (dev); | |
816 | np = pci_device_to_OF_node(pdev); | |
817 | if (np == NULL || np->full_name == NULL) | |
818 | return 0; | |
819 | return sprintf(buf, "%s", np->full_name); | |
820 | } | |
821 | static DEVICE_ATTR(devspec, S_IRUGO, pci_show_devspec, NULL); | |
822 | #endif /* CONFIG_PPC_MULTIPLATFORM */ | |
823 | ||
824 | void pcibios_add_platform_entries(struct pci_dev *pdev) | |
825 | { | |
826 | #ifdef CONFIG_PPC_MULTIPLATFORM | |
827 | device_create_file(&pdev->dev, &dev_attr_devspec); | |
828 | #endif /* CONFIG_PPC_MULTIPLATFORM */ | |
829 | } | |
830 | ||
831 | #ifdef CONFIG_PPC_MULTIPLATFORM | |
832 | ||
833 | #define ISA_SPACE_MASK 0x1 | |
834 | #define ISA_SPACE_IO 0x1 | |
835 | ||
836 | static void __devinit pci_process_ISA_OF_ranges(struct device_node *isa_node, | |
837 | unsigned long phb_io_base_phys, | |
838 | void __iomem * phb_io_base_virt) | |
839 | { | |
840 | struct isa_range *range; | |
841 | unsigned long pci_addr; | |
842 | unsigned int isa_addr; | |
843 | unsigned int size; | |
844 | int rlen = 0; | |
845 | ||
846 | range = (struct isa_range *) get_property(isa_node, "ranges", &rlen); | |
847 | if (range == NULL || (rlen < sizeof(struct isa_range))) { | |
848 | printk(KERN_ERR "no ISA ranges or unexpected isa range size," | |
849 | "mapping 64k\n"); | |
dfbacdc1 BH |
850 | __ioremap_explicit(phb_io_base_phys, |
851 | (unsigned long)phb_io_base_virt, | |
852 | 0x10000, _PAGE_NO_CACHE | _PAGE_GUARDED); | |
1da177e4 LT |
853 | return; |
854 | } | |
855 | ||
856 | /* From "ISA Binding to 1275" | |
857 | * The ranges property is laid out as an array of elements, | |
858 | * each of which comprises: | |
859 | * cells 0 - 1: an ISA address | |
860 | * cells 2 - 4: a PCI address | |
861 | * (size depending on dev->n_addr_cells) | |
862 | * cell 5: the size of the range | |
863 | */ | |
864 | if ((range->isa_addr.a_hi && ISA_SPACE_MASK) == ISA_SPACE_IO) { | |
865 | isa_addr = range->isa_addr.a_lo; | |
866 | pci_addr = (unsigned long) range->pci_addr.a_mid << 32 | | |
867 | range->pci_addr.a_lo; | |
868 | ||
869 | /* Assume these are both zero */ | |
870 | if ((pci_addr != 0) || (isa_addr != 0)) { | |
871 | printk(KERN_ERR "unexpected isa to pci mapping: %s\n", | |
872 | __FUNCTION__); | |
873 | return; | |
874 | } | |
875 | ||
876 | size = PAGE_ALIGN(range->size); | |
877 | ||
878 | __ioremap_explicit(phb_io_base_phys, | |
879 | (unsigned long) phb_io_base_virt, | |
dfbacdc1 | 880 | size, _PAGE_NO_CACHE | _PAGE_GUARDED); |
1da177e4 LT |
881 | } |
882 | } | |
883 | ||
884 | void __devinit pci_process_bridge_OF_ranges(struct pci_controller *hose, | |
f7abbc19 | 885 | struct device_node *dev, int prim) |
1da177e4 | 886 | { |
f7abbc19 | 887 | unsigned int *ranges, pci_space; |
1da177e4 LT |
888 | unsigned long size; |
889 | int rlen = 0; | |
890 | int memno = 0; | |
891 | struct resource *res; | |
892 | int np, na = prom_n_addr_cells(dev); | |
893 | unsigned long pci_addr, cpu_phys_addr; | |
894 | ||
895 | np = na + 5; | |
896 | ||
897 | /* From "PCI Binding to 1275" | |
898 | * The ranges property is laid out as an array of elements, | |
899 | * each of which comprises: | |
900 | * cells 0 - 2: a PCI address | |
901 | * cells 3 or 3+4: a CPU physical address | |
902 | * (size depending on dev->n_addr_cells) | |
903 | * cells 4+5 or 5+6: the size of the range | |
904 | */ | |
905 | rlen = 0; | |
906 | hose->io_base_phys = 0; | |
907 | ranges = (unsigned int *) get_property(dev, "ranges", &rlen); | |
908 | while ((rlen -= np * sizeof(unsigned int)) >= 0) { | |
909 | res = NULL; | |
f7abbc19 PM |
910 | pci_space = ranges[0]; |
911 | pci_addr = ((unsigned long)ranges[1] << 32) | ranges[2]; | |
1da177e4 LT |
912 | |
913 | cpu_phys_addr = ranges[3]; | |
f7abbc19 PM |
914 | if (na >= 2) |
915 | cpu_phys_addr = (cpu_phys_addr << 32) | ranges[4]; | |
1da177e4 | 916 | |
f7abbc19 PM |
917 | size = ((unsigned long)ranges[na+3] << 32) | ranges[na+4]; |
918 | ranges += np; | |
1da177e4 LT |
919 | if (size == 0) |
920 | continue; | |
f7abbc19 PM |
921 | |
922 | /* Now consume following elements while they are contiguous */ | |
923 | while (rlen >= np * sizeof(unsigned int)) { | |
924 | unsigned long addr, phys; | |
925 | ||
926 | if (ranges[0] != pci_space) | |
927 | break; | |
928 | addr = ((unsigned long)ranges[1] << 32) | ranges[2]; | |
929 | phys = ranges[3]; | |
930 | if (na >= 2) | |
931 | phys = (phys << 32) | ranges[4]; | |
932 | if (addr != pci_addr + size || | |
933 | phys != cpu_phys_addr + size) | |
934 | break; | |
935 | ||
936 | size += ((unsigned long)ranges[na+3] << 32) | |
937 | | ranges[na+4]; | |
938 | ranges += np; | |
939 | rlen -= np * sizeof(unsigned int); | |
940 | } | |
941 | ||
942 | switch ((pci_space >> 24) & 0x3) { | |
1da177e4 LT |
943 | case 1: /* I/O space */ |
944 | hose->io_base_phys = cpu_phys_addr; | |
945 | hose->pci_io_size = size; | |
946 | ||
947 | res = &hose->io_resource; | |
948 | res->flags = IORESOURCE_IO; | |
949 | res->start = pci_addr; | |
950 | DBG("phb%d: IO 0x%lx -> 0x%lx\n", hose->global_number, | |
951 | res->start, res->start + size - 1); | |
952 | break; | |
953 | case 2: /* memory space */ | |
954 | memno = 0; | |
955 | while (memno < 3 && hose->mem_resources[memno].flags) | |
956 | ++memno; | |
957 | ||
958 | if (memno == 0) | |
959 | hose->pci_mem_offset = cpu_phys_addr - pci_addr; | |
960 | if (memno < 3) { | |
961 | res = &hose->mem_resources[memno]; | |
962 | res->flags = IORESOURCE_MEM; | |
963 | res->start = cpu_phys_addr; | |
964 | DBG("phb%d: MEM 0x%lx -> 0x%lx\n", hose->global_number, | |
965 | res->start, res->start + size - 1); | |
966 | } | |
967 | break; | |
968 | } | |
969 | if (res != NULL) { | |
970 | res->name = dev->full_name; | |
971 | res->end = res->start + size - 1; | |
972 | res->parent = NULL; | |
973 | res->sibling = NULL; | |
974 | res->child = NULL; | |
975 | } | |
1da177e4 LT |
976 | } |
977 | } | |
978 | ||
979 | void __init pci_setup_phb_io(struct pci_controller *hose, int primary) | |
980 | { | |
981 | unsigned long size = hose->pci_io_size; | |
982 | unsigned long io_virt_offset; | |
983 | struct resource *res; | |
984 | struct device_node *isa_dn; | |
985 | ||
986 | hose->io_base_virt = reserve_phb_iospace(size); | |
987 | DBG("phb%d io_base_phys 0x%lx io_base_virt 0x%lx\n", | |
988 | hose->global_number, hose->io_base_phys, | |
989 | (unsigned long) hose->io_base_virt); | |
990 | ||
991 | if (primary) { | |
992 | pci_io_base = (unsigned long)hose->io_base_virt; | |
993 | isa_dn = of_find_node_by_type(NULL, "isa"); | |
994 | if (isa_dn) { | |
995 | isa_io_base = pci_io_base; | |
996 | pci_process_ISA_OF_ranges(isa_dn, hose->io_base_phys, | |
997 | hose->io_base_virt); | |
998 | of_node_put(isa_dn); | |
999 | /* Allow all IO */ | |
1000 | io_page_mask = -1; | |
1001 | } | |
1002 | } | |
1003 | ||
1004 | io_virt_offset = (unsigned long)hose->io_base_virt - pci_io_base; | |
1005 | res = &hose->io_resource; | |
1006 | res->start += io_virt_offset; | |
1007 | res->end += io_virt_offset; | |
1008 | } | |
1009 | ||
1010 | void __devinit pci_setup_phb_io_dynamic(struct pci_controller *hose, | |
1011 | int primary) | |
1012 | { | |
1013 | unsigned long size = hose->pci_io_size; | |
1014 | unsigned long io_virt_offset; | |
1015 | struct resource *res; | |
1016 | ||
1017 | hose->io_base_virt = __ioremap(hose->io_base_phys, size, | |
dfbacdc1 | 1018 | _PAGE_NO_CACHE | _PAGE_GUARDED); |
1da177e4 LT |
1019 | DBG("phb%d io_base_phys 0x%lx io_base_virt 0x%lx\n", |
1020 | hose->global_number, hose->io_base_phys, | |
1021 | (unsigned long) hose->io_base_virt); | |
1022 | ||
1023 | if (primary) | |
1024 | pci_io_base = (unsigned long)hose->io_base_virt; | |
1025 | ||
1026 | io_virt_offset = (unsigned long)hose->io_base_virt - pci_io_base; | |
1027 | res = &hose->io_resource; | |
1028 | res->start += io_virt_offset; | |
1029 | res->end += io_virt_offset; | |
1030 | } | |
1031 | ||
1032 | ||
1033 | static int get_bus_io_range(struct pci_bus *bus, unsigned long *start_phys, | |
1034 | unsigned long *start_virt, unsigned long *size) | |
1035 | { | |
1036 | struct pci_controller *hose = pci_bus_to_host(bus); | |
1037 | struct pci_bus_region region; | |
1038 | struct resource *res; | |
1039 | ||
1040 | if (bus->self) { | |
1041 | res = bus->resource[0]; | |
1042 | pcibios_resource_to_bus(bus->self, ®ion, res); | |
1043 | *start_phys = hose->io_base_phys + region.start; | |
1044 | *start_virt = (unsigned long) hose->io_base_virt + | |
1045 | region.start; | |
1046 | if (region.end > region.start) | |
1047 | *size = region.end - region.start + 1; | |
1048 | else { | |
1049 | printk("%s(): unexpected region 0x%lx->0x%lx\n", | |
1050 | __FUNCTION__, region.start, region.end); | |
1051 | return 1; | |
1052 | } | |
1053 | ||
1054 | } else { | |
1055 | /* Root Bus */ | |
1056 | res = &hose->io_resource; | |
1057 | *start_phys = hose->io_base_phys; | |
1058 | *start_virt = (unsigned long) hose->io_base_virt; | |
1059 | if (res->end > res->start) | |
1060 | *size = res->end - res->start + 1; | |
1061 | else { | |
1062 | printk("%s(): unexpected region 0x%lx->0x%lx\n", | |
1063 | __FUNCTION__, res->start, res->end); | |
1064 | return 1; | |
1065 | } | |
1066 | } | |
1067 | ||
1068 | return 0; | |
1069 | } | |
1070 | ||
1071 | int unmap_bus_range(struct pci_bus *bus) | |
1072 | { | |
1073 | unsigned long start_phys; | |
1074 | unsigned long start_virt; | |
1075 | unsigned long size; | |
1076 | ||
1077 | if (!bus) { | |
1078 | printk(KERN_ERR "%s() expected bus\n", __FUNCTION__); | |
1079 | return 1; | |
1080 | } | |
1081 | ||
1082 | if (get_bus_io_range(bus, &start_phys, &start_virt, &size)) | |
1083 | return 1; | |
1084 | if (iounmap_explicit((void __iomem *) start_virt, size)) | |
1085 | return 1; | |
1086 | ||
1087 | return 0; | |
1088 | } | |
1089 | EXPORT_SYMBOL(unmap_bus_range); | |
1090 | ||
1091 | int remap_bus_range(struct pci_bus *bus) | |
1092 | { | |
1093 | unsigned long start_phys; | |
1094 | unsigned long start_virt; | |
1095 | unsigned long size; | |
1096 | ||
1097 | if (!bus) { | |
1098 | printk(KERN_ERR "%s() expected bus\n", __FUNCTION__); | |
1099 | return 1; | |
1100 | } | |
1101 | ||
1102 | ||
1103 | if (get_bus_io_range(bus, &start_phys, &start_virt, &size)) | |
1104 | return 1; | |
1105 | printk("mapping IO %lx -> %lx, size: %lx\n", start_phys, start_virt, size); | |
dfbacdc1 BH |
1106 | if (__ioremap_explicit(start_phys, start_virt, size, |
1107 | _PAGE_NO_CACHE | _PAGE_GUARDED)) | |
1da177e4 LT |
1108 | return 1; |
1109 | ||
1110 | return 0; | |
1111 | } | |
1112 | EXPORT_SYMBOL(remap_bus_range); | |
1113 | ||
1114 | void phbs_remap_io(void) | |
1115 | { | |
1116 | struct pci_controller *hose, *tmp; | |
1117 | ||
1118 | list_for_each_entry_safe(hose, tmp, &hose_list, list_node) | |
1119 | remap_bus_range(hose->bus); | |
1120 | } | |
1121 | ||
1122 | /* | |
1123 | * ppc64 can have multifunction devices that do not respond to function 0. | |
1124 | * In this case we must scan all functions. | |
4267292b PM |
1125 | * XXX this can go now, we use the OF device tree in all the |
1126 | * cases that caused problems. -- paulus | |
1da177e4 LT |
1127 | */ |
1128 | int pcibios_scan_all_fns(struct pci_bus *bus, int devfn) | |
1129 | { | |
4267292b PM |
1130 | return 0; |
1131 | } | |
1da177e4 | 1132 | |
4267292b PM |
1133 | static void __devinit fixup_resource(struct resource *res, struct pci_dev *dev) |
1134 | { | |
1135 | struct pci_controller *hose = pci_bus_to_host(dev->bus); | |
1136 | unsigned long start, end, mask, offset; | |
1da177e4 | 1137 | |
4267292b PM |
1138 | if (res->flags & IORESOURCE_IO) { |
1139 | offset = (unsigned long)hose->io_base_virt - pci_io_base; | |
1da177e4 | 1140 | |
4267292b PM |
1141 | start = res->start += offset; |
1142 | end = res->end += offset; | |
1da177e4 | 1143 | |
4267292b PM |
1144 | /* Need to allow IO access to pages that are in the |
1145 | ISA range */ | |
1146 | if (start < MAX_ISA_PORT) { | |
1147 | if (end > MAX_ISA_PORT) | |
1148 | end = MAX_ISA_PORT; | |
1149 | ||
1150 | start >>= PAGE_SHIFT; | |
1151 | end >>= PAGE_SHIFT; | |
1da177e4 | 1152 | |
4267292b PM |
1153 | /* get the range of pages for the map */ |
1154 | mask = ((1 << (end+1)) - 1) ^ ((1 << start) - 1); | |
1155 | io_page_mask |= mask; | |
1156 | } | |
1157 | } else if (res->flags & IORESOURCE_MEM) { | |
1158 | res->start += hose->pci_mem_offset; | |
1159 | res->end += hose->pci_mem_offset; | |
1160 | } | |
1161 | } | |
1da177e4 LT |
1162 | |
1163 | void __devinit pcibios_fixup_device_resources(struct pci_dev *dev, | |
4267292b | 1164 | struct pci_bus *bus) |
1da177e4 LT |
1165 | { |
1166 | /* Update device resources. */ | |
1da177e4 LT |
1167 | int i; |
1168 | ||
4267292b PM |
1169 | for (i = 0; i < PCI_NUM_RESOURCES; i++) |
1170 | if (dev->resource[i].flags) | |
1171 | fixup_resource(&dev->resource[i], dev); | |
1da177e4 LT |
1172 | } |
1173 | EXPORT_SYMBOL(pcibios_fixup_device_resources); | |
1174 | ||
4267292b | 1175 | static void __devinit do_bus_setup(struct pci_bus *bus) |
1da177e4 | 1176 | { |
4267292b | 1177 | struct pci_dev *dev; |
1da177e4 | 1178 | |
4267292b | 1179 | ppc_md.iommu_bus_setup(bus); |
1da177e4 | 1180 | |
4267292b PM |
1181 | list_for_each_entry(dev, &bus->devices, bus_list) |
1182 | ppc_md.iommu_dev_setup(dev); | |
1da177e4 | 1183 | |
4267292b PM |
1184 | if (ppc_md.irq_bus_setup) |
1185 | ppc_md.irq_bus_setup(bus); | |
1186 | } | |
1da177e4 | 1187 | |
4267292b PM |
1188 | void __devinit pcibios_fixup_bus(struct pci_bus *bus) |
1189 | { | |
1190 | struct pci_dev *dev = bus->self; | |
1191 | ||
1192 | if (dev && pci_probe_only && | |
1193 | (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) { | |
1da177e4 LT |
1194 | /* This is a subordinate bridge */ |
1195 | ||
1196 | pci_read_bridge_bases(bus); | |
1197 | pcibios_fixup_device_resources(dev, bus); | |
1198 | } | |
1199 | ||
4267292b | 1200 | do_bus_setup(bus); |
dad32bbf | 1201 | |
1da177e4 LT |
1202 | if (!pci_probe_only) |
1203 | return; | |
1204 | ||
4267292b | 1205 | list_for_each_entry(dev, &bus->devices, bus_list) |
1da177e4 LT |
1206 | if ((dev->class >> 8) != PCI_CLASS_BRIDGE_PCI) |
1207 | pcibios_fixup_device_resources(dev, bus); | |
1da177e4 LT |
1208 | } |
1209 | EXPORT_SYMBOL(pcibios_fixup_bus); | |
1210 | ||
1211 | /* | |
1212 | * Reads the interrupt pin to determine if interrupt is use by card. | |
1213 | * If the interrupt is used, then gets the interrupt line from the | |
1214 | * openfirmware and sets it in the pci_dev and pci_config line. | |
1215 | */ | |
1216 | int pci_read_irq_line(struct pci_dev *pci_dev) | |
1217 | { | |
1218 | u8 intpin; | |
1219 | struct device_node *node; | |
1220 | ||
1221 | pci_read_config_byte(pci_dev, PCI_INTERRUPT_PIN, &intpin); | |
1222 | if (intpin == 0) | |
1223 | return 0; | |
1224 | ||
1225 | node = pci_device_to_OF_node(pci_dev); | |
1226 | if (node == NULL) | |
1227 | return -1; | |
1228 | ||
1229 | if (node->n_intrs == 0) | |
1230 | return -1; | |
1231 | ||
1232 | pci_dev->irq = node->intrs[0].line; | |
1233 | ||
1234 | pci_write_config_byte(pci_dev, PCI_INTERRUPT_LINE, pci_dev->irq); | |
1235 | ||
1236 | return 0; | |
1237 | } | |
1238 | EXPORT_SYMBOL(pci_read_irq_line); | |
1239 | ||
2311b1f2 ME |
1240 | void pci_resource_to_user(const struct pci_dev *dev, int bar, |
1241 | const struct resource *rsrc, | |
1242 | u64 *start, u64 *end) | |
1243 | { | |
1244 | struct pci_controller *hose = pci_bus_to_host(dev->bus); | |
1245 | unsigned long offset = 0; | |
1246 | ||
1247 | if (hose == NULL) | |
1248 | return; | |
1249 | ||
1250 | if (rsrc->flags & IORESOURCE_IO) | |
1251 | offset = pci_io_base - (unsigned long)hose->io_base_virt + | |
1252 | hose->io_base_phys; | |
1253 | ||
1254 | *start = rsrc->start + offset; | |
1255 | *end = rsrc->end + offset; | |
1256 | } | |
1257 | ||
1da177e4 | 1258 | #endif /* CONFIG_PPC_MULTIPLATFORM */ |
b2ad7b5e PM |
1259 | |
1260 | ||
1261 | #define IOBASE_BRIDGE_NUMBER 0 | |
1262 | #define IOBASE_MEMORY 1 | |
1263 | #define IOBASE_IO 2 | |
1264 | #define IOBASE_ISA_IO 3 | |
1265 | #define IOBASE_ISA_MEM 4 | |
1266 | ||
1267 | long sys_pciconfig_iobase(long which, unsigned long in_bus, | |
1268 | unsigned long in_devfn) | |
1269 | { | |
1270 | struct pci_controller* hose; | |
1271 | struct list_head *ln; | |
1272 | struct pci_bus *bus = NULL; | |
1273 | struct device_node *hose_node; | |
1274 | ||
1275 | /* Argh ! Please forgive me for that hack, but that's the | |
1276 | * simplest way to get existing XFree to not lockup on some | |
1277 | * G5 machines... So when something asks for bus 0 io base | |
1278 | * (bus 0 is HT root), we return the AGP one instead. | |
1279 | */ | |
799d6046 | 1280 | if (machine_is_compatible("MacRISC4")) |
b2ad7b5e PM |
1281 | if (in_bus == 0) |
1282 | in_bus = 0xf0; | |
b2ad7b5e PM |
1283 | |
1284 | /* That syscall isn't quite compatible with PCI domains, but it's | |
1285 | * used on pre-domains setup. We return the first match | |
1286 | */ | |
1287 | ||
1288 | for (ln = pci_root_buses.next; ln != &pci_root_buses; ln = ln->next) { | |
1289 | bus = pci_bus_b(ln); | |
1290 | if (in_bus >= bus->number && in_bus < (bus->number + bus->subordinate)) | |
1291 | break; | |
1292 | bus = NULL; | |
1293 | } | |
1294 | if (bus == NULL || bus->sysdata == NULL) | |
1295 | return -ENODEV; | |
1296 | ||
1297 | hose_node = (struct device_node *)bus->sysdata; | |
1298 | hose = PCI_DN(hose_node)->phb; | |
1299 | ||
1300 | switch (which) { | |
1301 | case IOBASE_BRIDGE_NUMBER: | |
1302 | return (long)hose->first_busno; | |
1303 | case IOBASE_MEMORY: | |
1304 | return (long)hose->pci_mem_offset; | |
1305 | case IOBASE_IO: | |
1306 | return (long)hose->io_base_phys; | |
1307 | case IOBASE_ISA_IO: | |
1308 | return (long)isa_io_base; | |
1309 | case IOBASE_ISA_MEM: | |
1310 | return -EINVAL; | |
1311 | } | |
1312 | ||
1313 | return -EOPNOTSUPP; | |
1314 | } |