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1da177e4 LT |
1 | /* |
2 | * arch/ppc64/kernel/pSeries_iommu.c | |
3 | * | |
4 | * Copyright (C) 2001 Mike Corrigan & Dave Engebretsen, IBM Corporation | |
5 | * | |
6 | * Rewrite, cleanup: | |
7 | * | |
8 | * Copyright (C) 2004 Olof Johansson <olof@austin.ibm.com>, IBM Corporation | |
9 | * | |
10 | * Dynamic DMA mapping support, pSeries-specific parts, both SMP and LPAR. | |
11 | * | |
12 | * | |
13 | * This program is free software; you can redistribute it and/or modify | |
14 | * it under the terms of the GNU General Public License as published by | |
15 | * the Free Software Foundation; either version 2 of the License, or | |
16 | * (at your option) any later version. | |
17 | * | |
18 | * This program is distributed in the hope that it will be useful, | |
19 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
20 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
21 | * GNU General Public License for more details. | |
22 | * | |
23 | * You should have received a copy of the GNU General Public License | |
24 | * along with this program; if not, write to the Free Software | |
25 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
26 | */ | |
27 | ||
28 | #include <linux/config.h> | |
29 | #include <linux/init.h> | |
30 | #include <linux/types.h> | |
31 | #include <linux/slab.h> | |
32 | #include <linux/mm.h> | |
33 | #include <linux/spinlock.h> | |
34 | #include <linux/string.h> | |
35 | #include <linux/pci.h> | |
36 | #include <linux/dma-mapping.h> | |
37 | #include <asm/io.h> | |
38 | #include <asm/prom.h> | |
39 | #include <asm/rtas.h> | |
40 | #include <asm/ppcdebug.h> | |
41 | #include <asm/iommu.h> | |
42 | #include <asm/pci-bridge.h> | |
43 | #include <asm/machdep.h> | |
44 | #include <asm/abs_addr.h> | |
45 | #include <asm/plpar_wrappers.h> | |
46 | #include <asm/pSeries_reconfig.h> | |
47 | #include <asm/systemcfg.h> | |
48 | #include "pci.h" | |
49 | ||
50 | #define DBG(fmt...) | |
51 | ||
52 | extern int is_python(struct device_node *); | |
53 | ||
54 | static void tce_build_pSeries(struct iommu_table *tbl, long index, | |
55 | long npages, unsigned long uaddr, | |
56 | enum dma_data_direction direction) | |
57 | { | |
58 | union tce_entry t; | |
59 | union tce_entry *tp; | |
60 | ||
61 | t.te_word = 0; | |
62 | t.te_rdwr = 1; // Read allowed | |
63 | ||
64 | if (direction != DMA_TO_DEVICE) | |
65 | t.te_pciwr = 1; | |
66 | ||
67 | tp = ((union tce_entry *)tbl->it_base) + index; | |
68 | ||
69 | while (npages--) { | |
70 | /* can't move this out since we might cross LMB boundary */ | |
71 | t.te_rpn = (virt_to_abs(uaddr)) >> PAGE_SHIFT; | |
72 | ||
73 | tp->te_word = t.te_word; | |
74 | ||
75 | uaddr += PAGE_SIZE; | |
76 | tp++; | |
77 | } | |
78 | } | |
79 | ||
80 | ||
81 | static void tce_free_pSeries(struct iommu_table *tbl, long index, long npages) | |
82 | { | |
83 | union tce_entry t; | |
84 | union tce_entry *tp; | |
85 | ||
86 | t.te_word = 0; | |
87 | tp = ((union tce_entry *)tbl->it_base) + index; | |
88 | ||
89 | while (npages--) { | |
90 | tp->te_word = t.te_word; | |
91 | ||
92 | tp++; | |
93 | } | |
94 | } | |
95 | ||
96 | ||
97 | static void tce_build_pSeriesLP(struct iommu_table *tbl, long tcenum, | |
98 | long npages, unsigned long uaddr, | |
99 | enum dma_data_direction direction) | |
100 | { | |
101 | u64 rc; | |
102 | union tce_entry tce; | |
103 | ||
104 | tce.te_word = 0; | |
105 | tce.te_rpn = (virt_to_abs(uaddr)) >> PAGE_SHIFT; | |
106 | tce.te_rdwr = 1; | |
107 | if (direction != DMA_TO_DEVICE) | |
108 | tce.te_pciwr = 1; | |
109 | ||
110 | while (npages--) { | |
111 | rc = plpar_tce_put((u64)tbl->it_index, | |
112 | (u64)tcenum << 12, | |
113 | tce.te_word ); | |
114 | ||
115 | if (rc && printk_ratelimit()) { | |
116 | printk("tce_build_pSeriesLP: plpar_tce_put failed. rc=%ld\n", rc); | |
117 | printk("\tindex = 0x%lx\n", (u64)tbl->it_index); | |
118 | printk("\ttcenum = 0x%lx\n", (u64)tcenum); | |
119 | printk("\ttce val = 0x%lx\n", tce.te_word ); | |
120 | show_stack(current, (unsigned long *)__get_SP()); | |
121 | } | |
122 | ||
123 | tcenum++; | |
124 | tce.te_rpn++; | |
125 | } | |
126 | } | |
127 | ||
128 | static DEFINE_PER_CPU(void *, tce_page) = NULL; | |
129 | ||
130 | static void tce_buildmulti_pSeriesLP(struct iommu_table *tbl, long tcenum, | |
131 | long npages, unsigned long uaddr, | |
132 | enum dma_data_direction direction) | |
133 | { | |
134 | u64 rc; | |
135 | union tce_entry tce, *tcep; | |
136 | long l, limit; | |
137 | ||
138 | if (npages == 1) | |
139 | return tce_build_pSeriesLP(tbl, tcenum, npages, uaddr, | |
140 | direction); | |
141 | ||
142 | tcep = __get_cpu_var(tce_page); | |
143 | ||
144 | /* This is safe to do since interrupts are off when we're called | |
145 | * from iommu_alloc{,_sg}() | |
146 | */ | |
147 | if (!tcep) { | |
148 | tcep = (void *)__get_free_page(GFP_ATOMIC); | |
149 | /* If allocation fails, fall back to the loop implementation */ | |
150 | if (!tcep) | |
151 | return tce_build_pSeriesLP(tbl, tcenum, npages, | |
152 | uaddr, direction); | |
153 | __get_cpu_var(tce_page) = tcep; | |
154 | } | |
155 | ||
156 | tce.te_word = 0; | |
157 | tce.te_rpn = (virt_to_abs(uaddr)) >> PAGE_SHIFT; | |
158 | tce.te_rdwr = 1; | |
159 | if (direction != DMA_TO_DEVICE) | |
160 | tce.te_pciwr = 1; | |
161 | ||
162 | /* We can map max one pageful of TCEs at a time */ | |
163 | do { | |
164 | /* | |
165 | * Set up the page with TCE data, looping through and setting | |
166 | * the values. | |
167 | */ | |
168 | limit = min_t(long, npages, PAGE_SIZE/sizeof(union tce_entry)); | |
169 | ||
170 | for (l = 0; l < limit; l++) { | |
171 | tcep[l] = tce; | |
172 | tce.te_rpn++; | |
173 | } | |
174 | ||
175 | rc = plpar_tce_put_indirect((u64)tbl->it_index, | |
176 | (u64)tcenum << 12, | |
177 | (u64)virt_to_abs(tcep), | |
178 | limit); | |
179 | ||
180 | npages -= limit; | |
181 | tcenum += limit; | |
182 | } while (npages > 0 && !rc); | |
183 | ||
184 | if (rc && printk_ratelimit()) { | |
185 | printk("tce_buildmulti_pSeriesLP: plpar_tce_put failed. rc=%ld\n", rc); | |
186 | printk("\tindex = 0x%lx\n", (u64)tbl->it_index); | |
187 | printk("\tnpages = 0x%lx\n", (u64)npages); | |
188 | printk("\ttce[0] val = 0x%lx\n", tcep[0].te_word); | |
189 | show_stack(current, (unsigned long *)__get_SP()); | |
190 | } | |
191 | } | |
192 | ||
193 | static void tce_free_pSeriesLP(struct iommu_table *tbl, long tcenum, long npages) | |
194 | { | |
195 | u64 rc; | |
196 | union tce_entry tce; | |
197 | ||
198 | tce.te_word = 0; | |
199 | ||
200 | while (npages--) { | |
201 | rc = plpar_tce_put((u64)tbl->it_index, | |
202 | (u64)tcenum << 12, | |
203 | tce.te_word); | |
204 | ||
205 | if (rc && printk_ratelimit()) { | |
206 | printk("tce_free_pSeriesLP: plpar_tce_put failed. rc=%ld\n", rc); | |
207 | printk("\tindex = 0x%lx\n", (u64)tbl->it_index); | |
208 | printk("\ttcenum = 0x%lx\n", (u64)tcenum); | |
209 | printk("\ttce val = 0x%lx\n", tce.te_word ); | |
210 | show_stack(current, (unsigned long *)__get_SP()); | |
211 | } | |
212 | ||
213 | tcenum++; | |
214 | } | |
215 | } | |
216 | ||
217 | ||
218 | static void tce_freemulti_pSeriesLP(struct iommu_table *tbl, long tcenum, long npages) | |
219 | { | |
220 | u64 rc; | |
221 | union tce_entry tce; | |
222 | ||
223 | tce.te_word = 0; | |
224 | ||
225 | rc = plpar_tce_stuff((u64)tbl->it_index, | |
226 | (u64)tcenum << 12, | |
227 | tce.te_word, | |
228 | npages); | |
229 | ||
230 | if (rc && printk_ratelimit()) { | |
231 | printk("tce_freemulti_pSeriesLP: plpar_tce_stuff failed\n"); | |
232 | printk("\trc = %ld\n", rc); | |
233 | printk("\tindex = 0x%lx\n", (u64)tbl->it_index); | |
234 | printk("\tnpages = 0x%lx\n", (u64)npages); | |
235 | printk("\ttce val = 0x%lx\n", tce.te_word ); | |
236 | show_stack(current, (unsigned long *)__get_SP()); | |
237 | } | |
238 | } | |
239 | ||
240 | static void iommu_table_setparms(struct pci_controller *phb, | |
241 | struct device_node *dn, | |
242 | struct iommu_table *tbl) | |
243 | { | |
244 | struct device_node *node; | |
245 | unsigned long *basep; | |
246 | unsigned int *sizep; | |
247 | ||
248 | node = (struct device_node *)phb->arch_data; | |
249 | ||
250 | basep = (unsigned long *)get_property(node, "linux,tce-base", NULL); | |
251 | sizep = (unsigned int *)get_property(node, "linux,tce-size", NULL); | |
252 | if (basep == NULL || sizep == NULL) { | |
253 | printk(KERN_ERR "PCI_DMA: iommu_table_setparms: %s has " | |
254 | "missing tce entries !\n", dn->full_name); | |
255 | return; | |
256 | } | |
257 | ||
258 | tbl->it_base = (unsigned long)__va(*basep); | |
259 | memset((void *)tbl->it_base, 0, *sizep); | |
260 | ||
261 | tbl->it_busno = phb->bus->number; | |
262 | ||
263 | /* Units of tce entries */ | |
264 | tbl->it_offset = phb->dma_window_base_cur >> PAGE_SHIFT; | |
265 | ||
266 | /* Test if we are going over 2GB of DMA space */ | |
267 | if (phb->dma_window_base_cur + phb->dma_window_size > (1L << 31)) | |
268 | panic("PCI_DMA: Unexpected number of IOAs under this PHB.\n"); | |
269 | ||
270 | phb->dma_window_base_cur += phb->dma_window_size; | |
271 | ||
272 | /* Set the tce table size - measured in entries */ | |
273 | tbl->it_size = phb->dma_window_size >> PAGE_SHIFT; | |
274 | ||
275 | tbl->it_index = 0; | |
276 | tbl->it_blocksize = 16; | |
277 | tbl->it_type = TCE_PCI; | |
278 | } | |
279 | ||
280 | /* | |
281 | * iommu_table_setparms_lpar | |
282 | * | |
283 | * Function: On pSeries LPAR systems, return TCE table info, given a pci bus. | |
284 | * | |
285 | * ToDo: properly interpret the ibm,dma-window property. The definition is: | |
286 | * logical-bus-number (1 word) | |
287 | * phys-address (#address-cells words) | |
288 | * size (#cell-size words) | |
289 | * | |
290 | * Currently we hard code these sizes (more or less). | |
291 | */ | |
292 | static void iommu_table_setparms_lpar(struct pci_controller *phb, | |
293 | struct device_node *dn, | |
294 | struct iommu_table *tbl, | |
295 | unsigned int *dma_window) | |
296 | { | |
297 | tbl->it_busno = dn->bussubno; | |
298 | ||
299 | /* TODO: Parse field size properties properly. */ | |
300 | tbl->it_size = (((unsigned long)dma_window[4] << 32) | | |
301 | (unsigned long)dma_window[5]) >> PAGE_SHIFT; | |
302 | tbl->it_offset = (((unsigned long)dma_window[2] << 32) | | |
303 | (unsigned long)dma_window[3]) >> PAGE_SHIFT; | |
304 | tbl->it_base = 0; | |
305 | tbl->it_index = dma_window[0]; | |
306 | tbl->it_blocksize = 16; | |
307 | tbl->it_type = TCE_PCI; | |
308 | } | |
309 | ||
310 | static void iommu_bus_setup_pSeries(struct pci_bus *bus) | |
311 | { | |
312 | struct device_node *dn, *pdn; | |
313 | struct iommu_table *tbl; | |
314 | ||
315 | DBG("iommu_bus_setup_pSeries, bus %p, bus->self %p\n", bus, bus->self); | |
316 | ||
317 | /* For each (root) bus, we carve up the available DMA space in 256MB | |
318 | * pieces. Since each piece is used by one (sub) bus/device, that would | |
319 | * give a maximum of 7 devices per PHB. In most cases, this is plenty. | |
320 | * | |
321 | * The exception is on Python PHBs (pre-POWER4). Here we don't have EADS | |
322 | * bridges below the PHB to allocate the sectioned tables to, so instead | |
323 | * we allocate a 1GB table at the PHB level. | |
324 | */ | |
325 | ||
326 | dn = pci_bus_to_OF_node(bus); | |
327 | ||
328 | if (!bus->self) { | |
329 | /* Root bus */ | |
330 | if (is_python(dn)) { | |
331 | unsigned int *iohole; | |
332 | ||
333 | DBG("Python root bus %s\n", bus->name); | |
334 | ||
335 | iohole = (unsigned int *)get_property(dn, "io-hole", 0); | |
336 | ||
337 | if (iohole) { | |
338 | /* On first bus we need to leave room for the | |
339 | * ISA address space. Just skip the first 256MB | |
340 | * alltogether. This leaves 768MB for the window. | |
341 | */ | |
342 | DBG("PHB has io-hole, reserving 256MB\n"); | |
343 | dn->phb->dma_window_size = 3 << 28; | |
344 | dn->phb->dma_window_base_cur = 1 << 28; | |
345 | } else { | |
346 | /* 1GB window by default */ | |
347 | dn->phb->dma_window_size = 1 << 30; | |
348 | dn->phb->dma_window_base_cur = 0; | |
349 | } | |
350 | ||
351 | tbl = kmalloc(sizeof(struct iommu_table), GFP_KERNEL); | |
352 | ||
353 | iommu_table_setparms(dn->phb, dn, tbl); | |
354 | dn->iommu_table = iommu_init_table(tbl); | |
355 | } else { | |
356 | /* Do a 128MB table at root. This is used for the IDE | |
357 | * controller on some SMP-mode POWER4 machines. It | |
358 | * doesn't hurt to allocate it on other machines | |
359 | * -- it'll just be unused since new tables are | |
360 | * allocated on the EADS level. | |
361 | * | |
362 | * Allocate at offset 128MB to avoid having to deal | |
363 | * with ISA holes; 128MB table for IDE is plenty. | |
364 | */ | |
365 | dn->phb->dma_window_size = 1 << 27; | |
366 | dn->phb->dma_window_base_cur = 1 << 27; | |
367 | ||
368 | tbl = kmalloc(sizeof(struct iommu_table), GFP_KERNEL); | |
369 | ||
370 | iommu_table_setparms(dn->phb, dn, tbl); | |
371 | dn->iommu_table = iommu_init_table(tbl); | |
372 | ||
373 | /* All child buses have 256MB tables */ | |
374 | dn->phb->dma_window_size = 1 << 28; | |
375 | } | |
376 | } else { | |
377 | pdn = pci_bus_to_OF_node(bus->parent); | |
378 | ||
379 | if (!bus->parent->self && !is_python(pdn)) { | |
380 | struct iommu_table *tbl; | |
381 | /* First child and not python means this is the EADS | |
382 | * level. Allocate new table for this slot with 256MB | |
383 | * window. | |
384 | */ | |
385 | ||
386 | tbl = kmalloc(sizeof(struct iommu_table), GFP_KERNEL); | |
387 | ||
388 | iommu_table_setparms(dn->phb, dn, tbl); | |
389 | ||
390 | dn->iommu_table = iommu_init_table(tbl); | |
391 | } else { | |
392 | /* Lower than first child or under python, use parent table */ | |
393 | dn->iommu_table = pdn->iommu_table; | |
394 | } | |
395 | } | |
396 | } | |
397 | ||
398 | ||
399 | static void iommu_bus_setup_pSeriesLP(struct pci_bus *bus) | |
400 | { | |
401 | struct iommu_table *tbl; | |
402 | struct device_node *dn, *pdn; | |
403 | unsigned int *dma_window = NULL; | |
404 | ||
405 | DBG("iommu_bus_setup_pSeriesLP, bus %p, bus->self %p\n", bus, bus->self); | |
406 | ||
407 | dn = pci_bus_to_OF_node(bus); | |
408 | ||
409 | /* Find nearest ibm,dma-window, walking up the device tree */ | |
410 | for (pdn = dn; pdn != NULL; pdn = pdn->parent) { | |
411 | dma_window = (unsigned int *)get_property(pdn, "ibm,dma-window", NULL); | |
412 | if (dma_window != NULL) | |
413 | break; | |
414 | } | |
415 | ||
416 | if (dma_window == NULL) { | |
417 | DBG("iommu_bus_setup_pSeriesLP: bus %s seems to have no ibm,dma-window property\n", dn->full_name); | |
418 | return; | |
419 | } | |
420 | ||
421 | if (!pdn->iommu_table) { | |
422 | /* Bussubno hasn't been copied yet. | |
423 | * Do it now because iommu_table_setparms_lpar needs it. | |
424 | */ | |
425 | pdn->bussubno = bus->number; | |
426 | ||
427 | tbl = (struct iommu_table *)kmalloc(sizeof(struct iommu_table), | |
428 | GFP_KERNEL); | |
429 | ||
430 | iommu_table_setparms_lpar(pdn->phb, pdn, tbl, dma_window); | |
431 | ||
432 | pdn->iommu_table = iommu_init_table(tbl); | |
433 | } | |
434 | ||
435 | if (pdn != dn) | |
436 | dn->iommu_table = pdn->iommu_table; | |
437 | } | |
438 | ||
439 | ||
440 | static void iommu_dev_setup_pSeries(struct pci_dev *dev) | |
441 | { | |
442 | struct device_node *dn, *mydn; | |
443 | ||
444 | DBG("iommu_dev_setup_pSeries, dev %p (%s)\n", dev, dev->pretty_name); | |
445 | /* Now copy the iommu_table ptr from the bus device down to the | |
446 | * pci device_node. This means get_iommu_table() won't need to search | |
447 | * up the device tree to find it. | |
448 | */ | |
449 | mydn = dn = pci_device_to_OF_node(dev); | |
450 | ||
451 | while (dn && dn->iommu_table == NULL) | |
452 | dn = dn->parent; | |
453 | ||
454 | if (dn) { | |
455 | mydn->iommu_table = dn->iommu_table; | |
456 | } else { | |
457 | DBG("iommu_dev_setup_pSeries, dev %p (%s) has no iommu table\n", dev, dev->pretty_name); | |
458 | } | |
459 | } | |
460 | ||
461 | static int iommu_reconfig_notifier(struct notifier_block *nb, unsigned long action, void *node) | |
462 | { | |
463 | int err = NOTIFY_OK; | |
464 | struct device_node *np = node; | |
465 | ||
466 | switch (action) { | |
467 | case PSERIES_RECONFIG_REMOVE: | |
468 | if (np->iommu_table && | |
469 | get_property(np, "ibm,dma-window", NULL)) | |
470 | iommu_free_table(np); | |
471 | break; | |
472 | default: | |
473 | err = NOTIFY_DONE; | |
474 | break; | |
475 | } | |
476 | return err; | |
477 | } | |
478 | ||
479 | static struct notifier_block iommu_reconfig_nb = { | |
480 | .notifier_call = iommu_reconfig_notifier, | |
481 | }; | |
482 | ||
483 | static void iommu_dev_setup_pSeriesLP(struct pci_dev *dev) | |
484 | { | |
485 | struct device_node *pdn, *dn; | |
486 | struct iommu_table *tbl; | |
487 | int *dma_window = NULL; | |
488 | ||
489 | DBG("iommu_dev_setup_pSeriesLP, dev %p (%s)\n", dev, dev->pretty_name); | |
490 | ||
491 | /* dev setup for LPAR is a little tricky, since the device tree might | |
492 | * contain the dma-window properties per-device and not neccesarily | |
493 | * for the bus. So we need to search upwards in the tree until we | |
494 | * either hit a dma-window property, OR find a parent with a table | |
495 | * already allocated. | |
496 | */ | |
497 | dn = pci_device_to_OF_node(dev); | |
498 | ||
499 | for (pdn = dn; pdn && !pdn->iommu_table; pdn = pdn->parent) { | |
500 | dma_window = (unsigned int *)get_property(pdn, "ibm,dma-window", NULL); | |
501 | if (dma_window) | |
502 | break; | |
503 | } | |
504 | ||
505 | /* Check for parent == NULL so we don't try to setup the empty EADS | |
506 | * slots on POWER4 machines. | |
507 | */ | |
508 | if (dma_window == NULL || pdn->parent == NULL) { | |
509 | /* Fall back to regular (non-LPAR) dev setup */ | |
510 | DBG("No dma window for device, falling back to regular setup\n"); | |
511 | iommu_dev_setup_pSeries(dev); | |
512 | return; | |
513 | } else { | |
514 | DBG("Found DMA window, allocating table\n"); | |
515 | } | |
516 | ||
517 | if (!pdn->iommu_table) { | |
518 | /* iommu_table_setparms_lpar needs bussubno. */ | |
519 | pdn->bussubno = pdn->phb->bus->number; | |
520 | ||
521 | tbl = (struct iommu_table *)kmalloc(sizeof(struct iommu_table), | |
522 | GFP_KERNEL); | |
523 | ||
524 | iommu_table_setparms_lpar(pdn->phb, pdn, tbl, dma_window); | |
525 | ||
526 | pdn->iommu_table = iommu_init_table(tbl); | |
527 | } | |
528 | ||
529 | if (pdn != dn) | |
530 | dn->iommu_table = pdn->iommu_table; | |
531 | } | |
532 | ||
533 | static void iommu_bus_setup_null(struct pci_bus *b) { } | |
534 | static void iommu_dev_setup_null(struct pci_dev *d) { } | |
535 | ||
536 | /* These are called very early. */ | |
537 | void iommu_init_early_pSeries(void) | |
538 | { | |
539 | if (of_chosen && get_property(of_chosen, "linux,iommu-off", NULL)) { | |
540 | /* Direct I/O, IOMMU off */ | |
541 | ppc_md.iommu_dev_setup = iommu_dev_setup_null; | |
542 | ppc_md.iommu_bus_setup = iommu_bus_setup_null; | |
543 | pci_direct_iommu_init(); | |
544 | ||
545 | return; | |
546 | } | |
547 | ||
548 | if (systemcfg->platform & PLATFORM_LPAR) { | |
549 | if (cur_cpu_spec->firmware_features & FW_FEATURE_MULTITCE) { | |
550 | ppc_md.tce_build = tce_buildmulti_pSeriesLP; | |
551 | ppc_md.tce_free = tce_freemulti_pSeriesLP; | |
552 | } else { | |
553 | ppc_md.tce_build = tce_build_pSeriesLP; | |
554 | ppc_md.tce_free = tce_free_pSeriesLP; | |
555 | } | |
556 | ppc_md.iommu_bus_setup = iommu_bus_setup_pSeriesLP; | |
557 | ppc_md.iommu_dev_setup = iommu_dev_setup_pSeriesLP; | |
558 | } else { | |
559 | ppc_md.tce_build = tce_build_pSeries; | |
560 | ppc_md.tce_free = tce_free_pSeries; | |
561 | ppc_md.iommu_bus_setup = iommu_bus_setup_pSeries; | |
562 | ppc_md.iommu_dev_setup = iommu_dev_setup_pSeries; | |
563 | } | |
564 | ||
565 | ||
566 | pSeries_reconfig_notifier_register(&iommu_reconfig_nb); | |
567 | ||
568 | pci_iommu_init(); | |
569 | } | |
570 |