Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * eeh.c | |
3 | * Copyright (C) 2001 Dave Engebretsen & Todd Inglett IBM Corporation | |
69376502 | 4 | * |
1da177e4 LT |
5 | * This program is free software; you can redistribute it and/or modify |
6 | * it under the terms of the GNU General Public License as published by | |
7 | * the Free Software Foundation; either version 2 of the License, or | |
8 | * (at your option) any later version. | |
69376502 | 9 | * |
1da177e4 LT |
10 | * This program is distributed in the hope that it will be useful, |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
69376502 | 14 | * |
1da177e4 LT |
15 | * You should have received a copy of the GNU General Public License |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | */ | |
19 | ||
1da177e4 LT |
20 | #include <linux/init.h> |
21 | #include <linux/list.h> | |
1da177e4 LT |
22 | #include <linux/notifier.h> |
23 | #include <linux/pci.h> | |
24 | #include <linux/proc_fs.h> | |
25 | #include <linux/rbtree.h> | |
26 | #include <linux/seq_file.h> | |
27 | #include <linux/spinlock.h> | |
69376502 | 28 | #include <asm/atomic.h> |
1da177e4 LT |
29 | #include <asm/eeh.h> |
30 | #include <asm/io.h> | |
31 | #include <asm/machdep.h> | |
32 | #include <asm/rtas.h> | |
33 | #include <asm/atomic.h> | |
34 | #include <asm/systemcfg.h> | |
d387899f | 35 | #include <asm/ppc-pci.h> |
1da177e4 LT |
36 | |
37 | #undef DEBUG | |
38 | ||
39 | /** Overview: | |
40 | * EEH, or "Extended Error Handling" is a PCI bridge technology for | |
41 | * dealing with PCI bus errors that can't be dealt with within the | |
42 | * usual PCI framework, except by check-stopping the CPU. Systems | |
43 | * that are designed for high-availability/reliability cannot afford | |
44 | * to crash due to a "mere" PCI error, thus the need for EEH. | |
45 | * An EEH-capable bridge operates by converting a detected error | |
46 | * into a "slot freeze", taking the PCI adapter off-line, making | |
47 | * the slot behave, from the OS'es point of view, as if the slot | |
48 | * were "empty": all reads return 0xff's and all writes are silently | |
49 | * ignored. EEH slot isolation events can be triggered by parity | |
50 | * errors on the address or data busses (e.g. during posted writes), | |
69376502 LV |
51 | * which in turn might be caused by low voltage on the bus, dust, |
52 | * vibration, humidity, radioactivity or plain-old failed hardware. | |
1da177e4 LT |
53 | * |
54 | * Note, however, that one of the leading causes of EEH slot | |
55 | * freeze events are buggy device drivers, buggy device microcode, | |
56 | * or buggy device hardware. This is because any attempt by the | |
57 | * device to bus-master data to a memory address that is not | |
58 | * assigned to the device will trigger a slot freeze. (The idea | |
59 | * is to prevent devices-gone-wild from corrupting system memory). | |
60 | * Buggy hardware/drivers will have a miserable time co-existing | |
61 | * with EEH. | |
62 | * | |
63 | * Ideally, a PCI device driver, when suspecting that an isolation | |
64 | * event has occured (e.g. by reading 0xff's), will then ask EEH | |
65 | * whether this is the case, and then take appropriate steps to | |
66 | * reset the PCI slot, the PCI device, and then resume operations. | |
67 | * However, until that day, the checking is done here, with the | |
68 | * eeh_check_failure() routine embedded in the MMIO macros. If | |
69 | * the slot is found to be isolated, an "EEH Event" is synthesized | |
70 | * and sent out for processing. | |
71 | */ | |
72 | ||
1da177e4 LT |
73 | /* EEH event workqueue setup. */ |
74 | static DEFINE_SPINLOCK(eeh_eventlist_lock); | |
75 | LIST_HEAD(eeh_eventlist); | |
76 | static void eeh_event_handler(void *); | |
77 | DECLARE_WORK(eeh_event_wq, eeh_event_handler, NULL); | |
78 | ||
79 | static struct notifier_block *eeh_notifier_chain; | |
80 | ||
81 | /* | |
82 | * If a device driver keeps reading an MMIO register in an interrupt | |
83 | * handler after a slot isolation event has occurred, we assume it | |
84 | * is broken and panic. This sets the threshold for how many read | |
85 | * attempts we allow before panicking. | |
86 | */ | |
87 | #define EEH_MAX_FAILS 1000 | |
88 | static atomic_t eeh_fail_count; | |
89 | ||
90 | /* RTAS tokens */ | |
91 | static int ibm_set_eeh_option; | |
92 | static int ibm_set_slot_reset; | |
93 | static int ibm_read_slot_reset_state; | |
94 | static int ibm_read_slot_reset_state2; | |
95 | static int ibm_slot_error_detail; | |
96 | ||
97 | static int eeh_subsystem_enabled; | |
98 | ||
99 | /* Buffer for reporting slot-error-detail rtas calls */ | |
100 | static unsigned char slot_errbuf[RTAS_ERROR_LOG_MAX]; | |
101 | static DEFINE_SPINLOCK(slot_errbuf_lock); | |
102 | static int eeh_error_buf_size; | |
103 | ||
104 | /* System monitoring statistics */ | |
177bc936 LV |
105 | static DEFINE_PER_CPU(unsigned long, no_device); |
106 | static DEFINE_PER_CPU(unsigned long, no_dn); | |
107 | static DEFINE_PER_CPU(unsigned long, no_cfg_addr); | |
108 | static DEFINE_PER_CPU(unsigned long, ignored_check); | |
1da177e4 LT |
109 | static DEFINE_PER_CPU(unsigned long, total_mmio_ffs); |
110 | static DEFINE_PER_CPU(unsigned long, false_positives); | |
111 | static DEFINE_PER_CPU(unsigned long, ignored_failures); | |
112 | static DEFINE_PER_CPU(unsigned long, slot_resets); | |
113 | ||
114 | /** | |
115 | * The pci address cache subsystem. This subsystem places | |
116 | * PCI device address resources into a red-black tree, sorted | |
117 | * according to the address range, so that given only an i/o | |
118 | * address, the corresponding PCI device can be **quickly** | |
119 | * found. It is safe to perform an address lookup in an interrupt | |
120 | * context; this ability is an important feature. | |
121 | * | |
122 | * Currently, the only customer of this code is the EEH subsystem; | |
123 | * thus, this code has been somewhat tailored to suit EEH better. | |
124 | * In particular, the cache does *not* hold the addresses of devices | |
125 | * for which EEH is not enabled. | |
126 | * | |
127 | * (Implementation Note: The RB tree seems to be better/faster | |
128 | * than any hash algo I could think of for this problem, even | |
129 | * with the penalty of slow pointer chases for d-cache misses). | |
130 | */ | |
131 | struct pci_io_addr_range | |
132 | { | |
133 | struct rb_node rb_node; | |
134 | unsigned long addr_lo; | |
135 | unsigned long addr_hi; | |
136 | struct pci_dev *pcidev; | |
137 | unsigned int flags; | |
138 | }; | |
139 | ||
140 | static struct pci_io_addr_cache | |
141 | { | |
142 | struct rb_root rb_root; | |
143 | spinlock_t piar_lock; | |
144 | } pci_io_addr_cache_root; | |
145 | ||
146 | static inline struct pci_dev *__pci_get_device_by_addr(unsigned long addr) | |
147 | { | |
148 | struct rb_node *n = pci_io_addr_cache_root.rb_root.rb_node; | |
149 | ||
150 | while (n) { | |
151 | struct pci_io_addr_range *piar; | |
152 | piar = rb_entry(n, struct pci_io_addr_range, rb_node); | |
153 | ||
154 | if (addr < piar->addr_lo) { | |
155 | n = n->rb_left; | |
156 | } else { | |
157 | if (addr > piar->addr_hi) { | |
158 | n = n->rb_right; | |
159 | } else { | |
160 | pci_dev_get(piar->pcidev); | |
161 | return piar->pcidev; | |
162 | } | |
163 | } | |
164 | } | |
165 | ||
166 | return NULL; | |
167 | } | |
168 | ||
169 | /** | |
170 | * pci_get_device_by_addr - Get device, given only address | |
171 | * @addr: mmio (PIO) phys address or i/o port number | |
172 | * | |
173 | * Given an mmio phys address, or a port number, find a pci device | |
174 | * that implements this address. Be sure to pci_dev_put the device | |
175 | * when finished. I/O port numbers are assumed to be offset | |
176 | * from zero (that is, they do *not* have pci_io_addr added in). | |
177 | * It is safe to call this function within an interrupt. | |
178 | */ | |
179 | static struct pci_dev *pci_get_device_by_addr(unsigned long addr) | |
180 | { | |
181 | struct pci_dev *dev; | |
182 | unsigned long flags; | |
183 | ||
184 | spin_lock_irqsave(&pci_io_addr_cache_root.piar_lock, flags); | |
185 | dev = __pci_get_device_by_addr(addr); | |
186 | spin_unlock_irqrestore(&pci_io_addr_cache_root.piar_lock, flags); | |
187 | return dev; | |
188 | } | |
189 | ||
190 | #ifdef DEBUG | |
191 | /* | |
192 | * Handy-dandy debug print routine, does nothing more | |
193 | * than print out the contents of our addr cache. | |
194 | */ | |
195 | static void pci_addr_cache_print(struct pci_io_addr_cache *cache) | |
196 | { | |
197 | struct rb_node *n; | |
198 | int cnt = 0; | |
199 | ||
200 | n = rb_first(&cache->rb_root); | |
201 | while (n) { | |
202 | struct pci_io_addr_range *piar; | |
203 | piar = rb_entry(n, struct pci_io_addr_range, rb_node); | |
982245f0 | 204 | printk(KERN_DEBUG "PCI: %s addr range %d [%lx-%lx]: %s\n", |
1da177e4 | 205 | (piar->flags & IORESOURCE_IO) ? "i/o" : "mem", cnt, |
982245f0 | 206 | piar->addr_lo, piar->addr_hi, pci_name(piar->pcidev)); |
1da177e4 LT |
207 | cnt++; |
208 | n = rb_next(n); | |
209 | } | |
210 | } | |
211 | #endif | |
212 | ||
213 | /* Insert address range into the rb tree. */ | |
214 | static struct pci_io_addr_range * | |
215 | pci_addr_cache_insert(struct pci_dev *dev, unsigned long alo, | |
216 | unsigned long ahi, unsigned int flags) | |
217 | { | |
218 | struct rb_node **p = &pci_io_addr_cache_root.rb_root.rb_node; | |
219 | struct rb_node *parent = NULL; | |
220 | struct pci_io_addr_range *piar; | |
221 | ||
222 | /* Walk tree, find a place to insert into tree */ | |
223 | while (*p) { | |
224 | parent = *p; | |
225 | piar = rb_entry(parent, struct pci_io_addr_range, rb_node); | |
56b0fca3 | 226 | if (ahi < piar->addr_lo) { |
1da177e4 | 227 | p = &parent->rb_left; |
56b0fca3 | 228 | } else if (alo > piar->addr_hi) { |
1da177e4 LT |
229 | p = &parent->rb_right; |
230 | } else { | |
231 | if (dev != piar->pcidev || | |
232 | alo != piar->addr_lo || ahi != piar->addr_hi) { | |
233 | printk(KERN_WARNING "PIAR: overlapping address range\n"); | |
234 | } | |
235 | return piar; | |
236 | } | |
237 | } | |
238 | piar = (struct pci_io_addr_range *)kmalloc(sizeof(struct pci_io_addr_range), GFP_ATOMIC); | |
239 | if (!piar) | |
240 | return NULL; | |
241 | ||
242 | piar->addr_lo = alo; | |
243 | piar->addr_hi = ahi; | |
244 | piar->pcidev = dev; | |
245 | piar->flags = flags; | |
246 | ||
56b0fca3 LV |
247 | #ifdef DEBUG |
248 | printk(KERN_DEBUG "PIAR: insert range=[%lx:%lx] dev=%s\n", | |
249 | alo, ahi, pci_name (dev)); | |
250 | #endif | |
251 | ||
1da177e4 LT |
252 | rb_link_node(&piar->rb_node, parent, p); |
253 | rb_insert_color(&piar->rb_node, &pci_io_addr_cache_root.rb_root); | |
254 | ||
255 | return piar; | |
256 | } | |
257 | ||
258 | static void __pci_addr_cache_insert_device(struct pci_dev *dev) | |
259 | { | |
260 | struct device_node *dn; | |
1635317f | 261 | struct pci_dn *pdn; |
1da177e4 LT |
262 | int i; |
263 | int inserted = 0; | |
264 | ||
265 | dn = pci_device_to_OF_node(dev); | |
266 | if (!dn) { | |
69376502 | 267 | printk(KERN_WARNING "PCI: no pci dn found for dev=%s\n", pci_name(dev)); |
1da177e4 LT |
268 | return; |
269 | } | |
270 | ||
271 | /* Skip any devices for which EEH is not enabled. */ | |
69376502 | 272 | pdn = PCI_DN(dn); |
1635317f PM |
273 | if (!(pdn->eeh_mode & EEH_MODE_SUPPORTED) || |
274 | pdn->eeh_mode & EEH_MODE_NOCHECK) { | |
1da177e4 | 275 | #ifdef DEBUG |
69376502 LV |
276 | printk(KERN_INFO "PCI: skip building address cache for=%s - %s\n", |
277 | pci_name(dev), pdn->node->full_name); | |
1da177e4 LT |
278 | #endif |
279 | return; | |
280 | } | |
281 | ||
282 | /* The cache holds a reference to the device... */ | |
283 | pci_dev_get(dev); | |
284 | ||
285 | /* Walk resources on this device, poke them into the tree */ | |
286 | for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { | |
287 | unsigned long start = pci_resource_start(dev,i); | |
288 | unsigned long end = pci_resource_end(dev,i); | |
289 | unsigned int flags = pci_resource_flags(dev,i); | |
290 | ||
291 | /* We are interested only bus addresses, not dma or other stuff */ | |
292 | if (0 == (flags & (IORESOURCE_IO | IORESOURCE_MEM))) | |
293 | continue; | |
294 | if (start == 0 || ~start == 0 || end == 0 || ~end == 0) | |
295 | continue; | |
296 | pci_addr_cache_insert(dev, start, end, flags); | |
297 | inserted = 1; | |
298 | } | |
299 | ||
300 | /* If there was nothing to add, the cache has no reference... */ | |
301 | if (!inserted) | |
302 | pci_dev_put(dev); | |
303 | } | |
304 | ||
305 | /** | |
306 | * pci_addr_cache_insert_device - Add a device to the address cache | |
307 | * @dev: PCI device whose I/O addresses we are interested in. | |
308 | * | |
309 | * In order to support the fast lookup of devices based on addresses, | |
310 | * we maintain a cache of devices that can be quickly searched. | |
311 | * This routine adds a device to that cache. | |
312 | */ | |
56b0fca3 | 313 | static void pci_addr_cache_insert_device(struct pci_dev *dev) |
1da177e4 LT |
314 | { |
315 | unsigned long flags; | |
316 | ||
317 | spin_lock_irqsave(&pci_io_addr_cache_root.piar_lock, flags); | |
318 | __pci_addr_cache_insert_device(dev); | |
319 | spin_unlock_irqrestore(&pci_io_addr_cache_root.piar_lock, flags); | |
320 | } | |
321 | ||
322 | static inline void __pci_addr_cache_remove_device(struct pci_dev *dev) | |
323 | { | |
324 | struct rb_node *n; | |
325 | int removed = 0; | |
326 | ||
327 | restart: | |
328 | n = rb_first(&pci_io_addr_cache_root.rb_root); | |
329 | while (n) { | |
330 | struct pci_io_addr_range *piar; | |
331 | piar = rb_entry(n, struct pci_io_addr_range, rb_node); | |
332 | ||
333 | if (piar->pcidev == dev) { | |
334 | rb_erase(n, &pci_io_addr_cache_root.rb_root); | |
335 | removed = 1; | |
336 | kfree(piar); | |
337 | goto restart; | |
338 | } | |
339 | n = rb_next(n); | |
340 | } | |
341 | ||
342 | /* The cache no longer holds its reference to this device... */ | |
343 | if (removed) | |
344 | pci_dev_put(dev); | |
345 | } | |
346 | ||
347 | /** | |
348 | * pci_addr_cache_remove_device - remove pci device from addr cache | |
349 | * @dev: device to remove | |
350 | * | |
351 | * Remove a device from the addr-cache tree. | |
352 | * This is potentially expensive, since it will walk | |
353 | * the tree multiple times (once per resource). | |
354 | * But so what; device removal doesn't need to be that fast. | |
355 | */ | |
56b0fca3 | 356 | static void pci_addr_cache_remove_device(struct pci_dev *dev) |
1da177e4 LT |
357 | { |
358 | unsigned long flags; | |
359 | ||
360 | spin_lock_irqsave(&pci_io_addr_cache_root.piar_lock, flags); | |
361 | __pci_addr_cache_remove_device(dev); | |
362 | spin_unlock_irqrestore(&pci_io_addr_cache_root.piar_lock, flags); | |
363 | } | |
364 | ||
365 | /** | |
366 | * pci_addr_cache_build - Build a cache of I/O addresses | |
367 | * | |
368 | * Build a cache of pci i/o addresses. This cache will be used to | |
369 | * find the pci device that corresponds to a given address. | |
370 | * This routine scans all pci busses to build the cache. | |
371 | * Must be run late in boot process, after the pci controllers | |
372 | * have been scaned for devices (after all device resources are known). | |
373 | */ | |
374 | void __init pci_addr_cache_build(void) | |
375 | { | |
376 | struct pci_dev *dev = NULL; | |
377 | ||
56b0fca3 LV |
378 | if (!eeh_subsystem_enabled) |
379 | return; | |
380 | ||
1da177e4 LT |
381 | spin_lock_init(&pci_io_addr_cache_root.piar_lock); |
382 | ||
383 | while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) { | |
384 | /* Ignore PCI bridges ( XXX why ??) */ | |
385 | if ((dev->class >> 16) == PCI_BASE_CLASS_BRIDGE) { | |
386 | continue; | |
387 | } | |
388 | pci_addr_cache_insert_device(dev); | |
389 | } | |
390 | ||
391 | #ifdef DEBUG | |
392 | /* Verify tree built up above, echo back the list of addrs. */ | |
393 | pci_addr_cache_print(&pci_io_addr_cache_root); | |
394 | #endif | |
395 | } | |
396 | ||
397 | /* --------------------------------------------------------------- */ | |
398 | /* Above lies the PCI Address Cache. Below lies the EEH event infrastructure */ | |
399 | ||
df7242b1 LV |
400 | void eeh_slot_error_detail (struct pci_dn *pdn, int severity) |
401 | { | |
402 | unsigned long flags; | |
403 | int rc; | |
404 | ||
405 | /* Log the error with the rtas logger */ | |
406 | spin_lock_irqsave(&slot_errbuf_lock, flags); | |
407 | memset(slot_errbuf, 0, eeh_error_buf_size); | |
408 | ||
409 | rc = rtas_call(ibm_slot_error_detail, | |
410 | 8, 1, NULL, pdn->eeh_config_addr, | |
411 | BUID_HI(pdn->phb->buid), | |
412 | BUID_LO(pdn->phb->buid), NULL, 0, | |
413 | virt_to_phys(slot_errbuf), | |
414 | eeh_error_buf_size, | |
415 | severity); | |
416 | ||
417 | if (rc == 0) | |
418 | log_error(slot_errbuf, ERR_TYPE_RTAS_LOG, 0); | |
419 | spin_unlock_irqrestore(&slot_errbuf_lock, flags); | |
420 | } | |
421 | ||
1da177e4 LT |
422 | /** |
423 | * eeh_register_notifier - Register to find out about EEH events. | |
424 | * @nb: notifier block to callback on events | |
425 | */ | |
426 | int eeh_register_notifier(struct notifier_block *nb) | |
427 | { | |
428 | return notifier_chain_register(&eeh_notifier_chain, nb); | |
429 | } | |
430 | ||
431 | /** | |
432 | * eeh_unregister_notifier - Unregister to an EEH event notifier. | |
433 | * @nb: notifier block to callback on events | |
434 | */ | |
435 | int eeh_unregister_notifier(struct notifier_block *nb) | |
436 | { | |
437 | return notifier_chain_unregister(&eeh_notifier_chain, nb); | |
438 | } | |
439 | ||
440 | /** | |
441 | * read_slot_reset_state - Read the reset state of a device node's slot | |
442 | * @dn: device node to read | |
443 | * @rets: array to return results in | |
444 | */ | |
69376502 | 445 | static int read_slot_reset_state(struct pci_dn *pdn, int rets[]) |
1da177e4 LT |
446 | { |
447 | int token, outputs; | |
448 | ||
449 | if (ibm_read_slot_reset_state2 != RTAS_UNKNOWN_SERVICE) { | |
450 | token = ibm_read_slot_reset_state2; | |
451 | outputs = 4; | |
452 | } else { | |
453 | token = ibm_read_slot_reset_state; | |
69376502 | 454 | rets[2] = 0; /* fake PE Unavailable info */ |
1da177e4 LT |
455 | outputs = 3; |
456 | } | |
457 | ||
1635317f PM |
458 | return rtas_call(token, 3, outputs, rets, pdn->eeh_config_addr, |
459 | BUID_HI(pdn->phb->buid), BUID_LO(pdn->phb->buid)); | |
1da177e4 LT |
460 | } |
461 | ||
462 | /** | |
463 | * eeh_panic - call panic() for an eeh event that cannot be handled. | |
464 | * The philosophy of this routine is that it is better to panic and | |
465 | * halt the OS than it is to risk possible data corruption by | |
466 | * oblivious device drivers that don't know better. | |
467 | * | |
468 | * @dev pci device that had an eeh event | |
469 | * @reset_state current reset state of the device slot | |
470 | */ | |
471 | static void eeh_panic(struct pci_dev *dev, int reset_state) | |
472 | { | |
473 | /* | |
474 | * XXX We should create a separate sysctl for this. | |
475 | * | |
476 | * Since the panic_on_oops sysctl is used to halt the system | |
477 | * in light of potential corruption, we can use it here. | |
478 | */ | |
df7242b1 LV |
479 | if (panic_on_oops) { |
480 | struct device_node *dn = pci_device_to_OF_node(dev); | |
481 | eeh_slot_error_detail (PCI_DN(dn), 2 /* Permanent Error */); | |
982245f0 AB |
482 | panic("EEH: MMIO failure (%d) on device:%s\n", reset_state, |
483 | pci_name(dev)); | |
df7242b1 | 484 | } |
1da177e4 LT |
485 | else { |
486 | __get_cpu_var(ignored_failures)++; | |
982245f0 AB |
487 | printk(KERN_INFO "EEH: Ignored MMIO failure (%d) on device:%s\n", |
488 | reset_state, pci_name(dev)); | |
1da177e4 LT |
489 | } |
490 | } | |
491 | ||
492 | /** | |
493 | * eeh_event_handler - dispatch EEH events. The detection of a frozen | |
494 | * slot can occur inside an interrupt, where it can be hard to do | |
495 | * anything about it. The goal of this routine is to pull these | |
496 | * detection events out of the context of the interrupt handler, and | |
497 | * re-dispatch them for processing at a later time in a normal context. | |
498 | * | |
499 | * @dummy - unused | |
500 | */ | |
501 | static void eeh_event_handler(void *dummy) | |
502 | { | |
503 | unsigned long flags; | |
504 | struct eeh_event *event; | |
505 | ||
506 | while (1) { | |
507 | spin_lock_irqsave(&eeh_eventlist_lock, flags); | |
508 | event = NULL; | |
509 | if (!list_empty(&eeh_eventlist)) { | |
510 | event = list_entry(eeh_eventlist.next, struct eeh_event, list); | |
511 | list_del(&event->list); | |
512 | } | |
513 | spin_unlock_irqrestore(&eeh_eventlist_lock, flags); | |
514 | if (event == NULL) | |
515 | break; | |
516 | ||
517 | printk(KERN_INFO "EEH: MMIO failure (%d), notifiying device " | |
982245f0 AB |
518 | "%s\n", event->reset_state, |
519 | pci_name(event->dev)); | |
1da177e4 LT |
520 | |
521 | atomic_set(&eeh_fail_count, 0); | |
522 | notifier_call_chain (&eeh_notifier_chain, | |
523 | EEH_NOTIFY_FREEZE, event); | |
524 | ||
1da177e4 LT |
525 | pci_dev_put(event->dev); |
526 | kfree(event); | |
527 | } | |
528 | } | |
529 | ||
530 | /** | |
531 | * eeh_token_to_phys - convert EEH address token to phys address | |
69376502 | 532 | * @token i/o token, should be address in the form 0xA.... |
1da177e4 LT |
533 | */ |
534 | static inline unsigned long eeh_token_to_phys(unsigned long token) | |
535 | { | |
536 | pte_t *ptep; | |
537 | unsigned long pa; | |
538 | ||
20cee16c | 539 | ptep = find_linux_pte(init_mm.pgd, token); |
1da177e4 LT |
540 | if (!ptep) |
541 | return token; | |
542 | pa = pte_pfn(*ptep) << PAGE_SHIFT; | |
543 | ||
544 | return pa | (token & (PAGE_SIZE-1)); | |
545 | } | |
546 | ||
547 | /** | |
548 | * eeh_dn_check_failure - check if all 1's data is due to EEH slot freeze | |
549 | * @dn device node | |
550 | * @dev pci device, if known | |
551 | * | |
552 | * Check for an EEH failure for the given device node. Call this | |
553 | * routine if the result of a read was all 0xff's and you want to | |
554 | * find out if this is due to an EEH slot freeze. This routine | |
555 | * will query firmware for the EEH status. | |
556 | * | |
557 | * Returns 0 if there has not been an EEH error; otherwise returns | |
69376502 | 558 | * a non-zero value and queues up a slot isolation event notification. |
1da177e4 LT |
559 | * |
560 | * It is safe to call this routine in an interrupt context. | |
561 | */ | |
562 | int eeh_dn_check_failure(struct device_node *dn, struct pci_dev *dev) | |
563 | { | |
564 | int ret; | |
565 | int rets[3]; | |
566 | unsigned long flags; | |
df7242b1 | 567 | int reset_state; |
1da177e4 | 568 | struct eeh_event *event; |
1635317f | 569 | struct pci_dn *pdn; |
1da177e4 LT |
570 | |
571 | __get_cpu_var(total_mmio_ffs)++; | |
572 | ||
573 | if (!eeh_subsystem_enabled) | |
574 | return 0; | |
575 | ||
177bc936 LV |
576 | if (!dn) { |
577 | __get_cpu_var(no_dn)++; | |
1da177e4 | 578 | return 0; |
177bc936 | 579 | } |
69376502 | 580 | pdn = PCI_DN(dn); |
1da177e4 LT |
581 | |
582 | /* Access to IO BARs might get this far and still not want checking. */ | |
1635317f PM |
583 | if (!pdn->eeh_capable || !(pdn->eeh_mode & EEH_MODE_SUPPORTED) || |
584 | pdn->eeh_mode & EEH_MODE_NOCHECK) { | |
177bc936 LV |
585 | __get_cpu_var(ignored_check)++; |
586 | #ifdef DEBUG | |
587 | printk ("EEH:ignored check for %s %s\n", pci_name (dev), dn->full_name); | |
588 | #endif | |
1da177e4 LT |
589 | return 0; |
590 | } | |
591 | ||
1635317f | 592 | if (!pdn->eeh_config_addr) { |
177bc936 | 593 | __get_cpu_var(no_cfg_addr)++; |
1da177e4 LT |
594 | return 0; |
595 | } | |
596 | ||
597 | /* | |
598 | * If we already have a pending isolation event for this | |
599 | * slot, we know it's bad already, we don't need to check... | |
600 | */ | |
1635317f | 601 | if (pdn->eeh_mode & EEH_MODE_ISOLATED) { |
1da177e4 LT |
602 | atomic_inc(&eeh_fail_count); |
603 | if (atomic_read(&eeh_fail_count) >= EEH_MAX_FAILS) { | |
604 | /* re-read the slot reset state */ | |
69376502 | 605 | if (read_slot_reset_state(pdn, rets) != 0) |
1da177e4 LT |
606 | rets[0] = -1; /* reset state unknown */ |
607 | eeh_panic(dev, rets[0]); | |
608 | } | |
609 | return 0; | |
610 | } | |
611 | ||
612 | /* | |
613 | * Now test for an EEH failure. This is VERY expensive. | |
614 | * Note that the eeh_config_addr may be a parent device | |
615 | * in the case of a device behind a bridge, or it may be | |
616 | * function zero of a multi-function device. | |
617 | * In any case they must share a common PHB. | |
618 | */ | |
69376502 | 619 | ret = read_slot_reset_state(pdn, rets); |
1da177e4 LT |
620 | if (!(ret == 0 && rets[1] == 1 && (rets[0] == 2 || rets[0] == 4))) { |
621 | __get_cpu_var(false_positives)++; | |
622 | return 0; | |
623 | } | |
624 | ||
625 | /* prevent repeated reports of this failure */ | |
1635317f | 626 | pdn->eeh_mode |= EEH_MODE_ISOLATED; |
177bc936 | 627 | __get_cpu_var(slot_resets)++; |
1da177e4 LT |
628 | |
629 | reset_state = rets[0]; | |
630 | ||
df7242b1 | 631 | eeh_slot_error_detail (pdn, 1 /* Temporary Error */); |
1da177e4 LT |
632 | |
633 | printk(KERN_INFO "EEH: MMIO failure (%d) on device: %s %s\n", | |
634 | rets[0], dn->name, dn->full_name); | |
635 | event = kmalloc(sizeof(*event), GFP_ATOMIC); | |
636 | if (event == NULL) { | |
637 | eeh_panic(dev, reset_state); | |
638 | return 1; | |
639 | } | |
640 | ||
641 | event->dev = dev; | |
642 | event->dn = dn; | |
643 | event->reset_state = reset_state; | |
644 | ||
645 | /* We may or may not be called in an interrupt context */ | |
646 | spin_lock_irqsave(&eeh_eventlist_lock, flags); | |
647 | list_add(&event->list, &eeh_eventlist); | |
648 | spin_unlock_irqrestore(&eeh_eventlist_lock, flags); | |
649 | ||
650 | /* Most EEH events are due to device driver bugs. Having | |
651 | * a stack trace will help the device-driver authors figure | |
652 | * out what happened. So print that out. */ | |
653 | dump_stack(); | |
654 | schedule_work(&eeh_event_wq); | |
655 | ||
656 | return 0; | |
657 | } | |
658 | ||
659 | EXPORT_SYMBOL(eeh_dn_check_failure); | |
660 | ||
661 | /** | |
662 | * eeh_check_failure - check if all 1's data is due to EEH slot freeze | |
663 | * @token i/o token, should be address in the form 0xA.... | |
664 | * @val value, should be all 1's (XXX why do we need this arg??) | |
665 | * | |
1da177e4 LT |
666 | * Check for an EEH failure at the given token address. Call this |
667 | * routine if the result of a read was all 0xff's and you want to | |
668 | * find out if this is due to an EEH slot freeze event. This routine | |
669 | * will query firmware for the EEH status. | |
670 | * | |
671 | * Note this routine is safe to call in an interrupt context. | |
672 | */ | |
673 | unsigned long eeh_check_failure(const volatile void __iomem *token, unsigned long val) | |
674 | { | |
675 | unsigned long addr; | |
676 | struct pci_dev *dev; | |
677 | struct device_node *dn; | |
678 | ||
679 | /* Finding the phys addr + pci device; this is pretty quick. */ | |
680 | addr = eeh_token_to_phys((unsigned long __force) token); | |
681 | dev = pci_get_device_by_addr(addr); | |
177bc936 LV |
682 | if (!dev) { |
683 | __get_cpu_var(no_device)++; | |
1da177e4 | 684 | return val; |
177bc936 | 685 | } |
1da177e4 LT |
686 | |
687 | dn = pci_device_to_OF_node(dev); | |
688 | eeh_dn_check_failure (dn, dev); | |
689 | ||
690 | pci_dev_put(dev); | |
691 | return val; | |
692 | } | |
693 | ||
694 | EXPORT_SYMBOL(eeh_check_failure); | |
695 | ||
696 | struct eeh_early_enable_info { | |
697 | unsigned int buid_hi; | |
698 | unsigned int buid_lo; | |
699 | }; | |
700 | ||
701 | /* Enable eeh for the given device node. */ | |
702 | static void *early_enable_eeh(struct device_node *dn, void *data) | |
703 | { | |
704 | struct eeh_early_enable_info *info = data; | |
705 | int ret; | |
706 | char *status = get_property(dn, "status", NULL); | |
707 | u32 *class_code = (u32 *)get_property(dn, "class-code", NULL); | |
708 | u32 *vendor_id = (u32 *)get_property(dn, "vendor-id", NULL); | |
709 | u32 *device_id = (u32 *)get_property(dn, "device-id", NULL); | |
710 | u32 *regs; | |
711 | int enable; | |
69376502 | 712 | struct pci_dn *pdn = PCI_DN(dn); |
1da177e4 | 713 | |
1635317f | 714 | pdn->eeh_mode = 0; |
1da177e4 LT |
715 | |
716 | if (status && strcmp(status, "ok") != 0) | |
717 | return NULL; /* ignore devices with bad status */ | |
718 | ||
719 | /* Ignore bad nodes. */ | |
720 | if (!class_code || !vendor_id || !device_id) | |
721 | return NULL; | |
722 | ||
723 | /* There is nothing to check on PCI to ISA bridges */ | |
724 | if (dn->type && !strcmp(dn->type, "isa")) { | |
1635317f | 725 | pdn->eeh_mode |= EEH_MODE_NOCHECK; |
1da177e4 LT |
726 | return NULL; |
727 | } | |
728 | ||
729 | /* | |
730 | * Now decide if we are going to "Disable" EEH checking | |
731 | * for this device. We still run with the EEH hardware active, | |
732 | * but we won't be checking for ff's. This means a driver | |
733 | * could return bad data (very bad!), an interrupt handler could | |
734 | * hang waiting on status bits that won't change, etc. | |
735 | * But there are a few cases like display devices that make sense. | |
736 | */ | |
737 | enable = 1; /* i.e. we will do checking */ | |
738 | if ((*class_code >> 16) == PCI_BASE_CLASS_DISPLAY) | |
739 | enable = 0; | |
740 | ||
741 | if (!enable) | |
1635317f | 742 | pdn->eeh_mode |= EEH_MODE_NOCHECK; |
1da177e4 LT |
743 | |
744 | /* Ok... see if this device supports EEH. Some do, some don't, | |
745 | * and the only way to find out is to check each and every one. */ | |
746 | regs = (u32 *)get_property(dn, "reg", NULL); | |
747 | if (regs) { | |
748 | /* First register entry is addr (00BBSS00) */ | |
749 | /* Try to enable eeh */ | |
750 | ret = rtas_call(ibm_set_eeh_option, 4, 1, NULL, | |
751 | regs[0], info->buid_hi, info->buid_lo, | |
752 | EEH_ENABLE); | |
753 | if (ret == 0) { | |
754 | eeh_subsystem_enabled = 1; | |
1635317f PM |
755 | pdn->eeh_mode |= EEH_MODE_SUPPORTED; |
756 | pdn->eeh_config_addr = regs[0]; | |
1da177e4 LT |
757 | #ifdef DEBUG |
758 | printk(KERN_DEBUG "EEH: %s: eeh enabled\n", dn->full_name); | |
759 | #endif | |
760 | } else { | |
761 | ||
762 | /* This device doesn't support EEH, but it may have an | |
763 | * EEH parent, in which case we mark it as supported. */ | |
69376502 | 764 | if (dn->parent && PCI_DN(dn->parent) |
1635317f | 765 | && (PCI_DN(dn->parent)->eeh_mode & EEH_MODE_SUPPORTED)) { |
1da177e4 | 766 | /* Parent supports EEH. */ |
1635317f PM |
767 | pdn->eeh_mode |= EEH_MODE_SUPPORTED; |
768 | pdn->eeh_config_addr = PCI_DN(dn->parent)->eeh_config_addr; | |
1da177e4 LT |
769 | return NULL; |
770 | } | |
771 | } | |
772 | } else { | |
773 | printk(KERN_WARNING "EEH: %s: unable to get reg property.\n", | |
774 | dn->full_name); | |
775 | } | |
776 | ||
69376502 | 777 | return NULL; |
1da177e4 LT |
778 | } |
779 | ||
780 | /* | |
781 | * Initialize EEH by trying to enable it for all of the adapters in the system. | |
782 | * As a side effect we can determine here if eeh is supported at all. | |
783 | * Note that we leave EEH on so failed config cycles won't cause a machine | |
784 | * check. If a user turns off EEH for a particular adapter they are really | |
785 | * telling Linux to ignore errors. Some hardware (e.g. POWER5) won't | |
786 | * grant access to a slot if EEH isn't enabled, and so we always enable | |
787 | * EEH for all slots/all devices. | |
788 | * | |
789 | * The eeh-force-off option disables EEH checking globally, for all slots. | |
790 | * Even if force-off is set, the EEH hardware is still enabled, so that | |
791 | * newer systems can boot. | |
792 | */ | |
793 | void __init eeh_init(void) | |
794 | { | |
795 | struct device_node *phb, *np; | |
796 | struct eeh_early_enable_info info; | |
797 | ||
df7242b1 LV |
798 | spin_lock_init(&slot_errbuf_lock); |
799 | ||
1da177e4 LT |
800 | np = of_find_node_by_path("/rtas"); |
801 | if (np == NULL) | |
802 | return; | |
803 | ||
804 | ibm_set_eeh_option = rtas_token("ibm,set-eeh-option"); | |
805 | ibm_set_slot_reset = rtas_token("ibm,set-slot-reset"); | |
806 | ibm_read_slot_reset_state2 = rtas_token("ibm,read-slot-reset-state2"); | |
807 | ibm_read_slot_reset_state = rtas_token("ibm,read-slot-reset-state"); | |
808 | ibm_slot_error_detail = rtas_token("ibm,slot-error-detail"); | |
809 | ||
810 | if (ibm_set_eeh_option == RTAS_UNKNOWN_SERVICE) | |
811 | return; | |
812 | ||
813 | eeh_error_buf_size = rtas_token("rtas-error-log-max"); | |
814 | if (eeh_error_buf_size == RTAS_UNKNOWN_SERVICE) { | |
815 | eeh_error_buf_size = 1024; | |
816 | } | |
817 | if (eeh_error_buf_size > RTAS_ERROR_LOG_MAX) { | |
818 | printk(KERN_WARNING "EEH: rtas-error-log-max is bigger than allocated " | |
819 | "buffer ! (%d vs %d)", eeh_error_buf_size, RTAS_ERROR_LOG_MAX); | |
820 | eeh_error_buf_size = RTAS_ERROR_LOG_MAX; | |
821 | } | |
822 | ||
823 | /* Enable EEH for all adapters. Note that eeh requires buid's */ | |
824 | for (phb = of_find_node_by_name(NULL, "pci"); phb; | |
825 | phb = of_find_node_by_name(phb, "pci")) { | |
826 | unsigned long buid; | |
827 | ||
828 | buid = get_phb_buid(phb); | |
69376502 | 829 | if (buid == 0 || PCI_DN(phb) == NULL) |
1da177e4 LT |
830 | continue; |
831 | ||
832 | info.buid_lo = BUID_LO(buid); | |
833 | info.buid_hi = BUID_HI(buid); | |
834 | traverse_pci_devices(phb, early_enable_eeh, &info); | |
835 | } | |
836 | ||
837 | if (eeh_subsystem_enabled) | |
838 | printk(KERN_INFO "EEH: PCI Enhanced I/O Error Handling Enabled\n"); | |
839 | else | |
840 | printk(KERN_WARNING "EEH: No capable adapters found\n"); | |
841 | } | |
842 | ||
843 | /** | |
844 | * eeh_add_device_early - enable EEH for the indicated device_node | |
845 | * @dn: device node for which to set up EEH | |
846 | * | |
847 | * This routine must be used to perform EEH initialization for PCI | |
848 | * devices that were added after system boot (e.g. hotplug, dlpar). | |
849 | * This routine must be called before any i/o is performed to the | |
850 | * adapter (inluding any config-space i/o). | |
851 | * Whether this actually enables EEH or not for this device depends | |
852 | * on the CEC architecture, type of the device, on earlier boot | |
853 | * command-line arguments & etc. | |
854 | */ | |
855 | void eeh_add_device_early(struct device_node *dn) | |
856 | { | |
857 | struct pci_controller *phb; | |
858 | struct eeh_early_enable_info info; | |
859 | ||
69376502 | 860 | if (!dn || !PCI_DN(dn)) |
1da177e4 | 861 | return; |
1635317f | 862 | phb = PCI_DN(dn)->phb; |
1da177e4 | 863 | if (NULL == phb || 0 == phb->buid) { |
69376502 LV |
864 | printk(KERN_WARNING "EEH: Expected buid but found none for %s\n", |
865 | dn->full_name); | |
866 | dump_stack(); | |
1da177e4 LT |
867 | return; |
868 | } | |
869 | ||
870 | info.buid_hi = BUID_HI(phb->buid); | |
871 | info.buid_lo = BUID_LO(phb->buid); | |
872 | early_enable_eeh(dn, &info); | |
873 | } | |
56b0fca3 | 874 | EXPORT_SYMBOL_GPL(eeh_add_device_early); |
1da177e4 LT |
875 | |
876 | /** | |
877 | * eeh_add_device_late - perform EEH initialization for the indicated pci device | |
878 | * @dev: pci device for which to set up EEH | |
879 | * | |
880 | * This routine must be used to complete EEH initialization for PCI | |
881 | * devices that were added after system boot (e.g. hotplug, dlpar). | |
882 | */ | |
883 | void eeh_add_device_late(struct pci_dev *dev) | |
884 | { | |
56b0fca3 LV |
885 | struct device_node *dn; |
886 | ||
1da177e4 LT |
887 | if (!dev || !eeh_subsystem_enabled) |
888 | return; | |
889 | ||
890 | #ifdef DEBUG | |
982245f0 | 891 | printk(KERN_DEBUG "EEH: adding device %s\n", pci_name(dev)); |
1da177e4 LT |
892 | #endif |
893 | ||
56b0fca3 LV |
894 | pci_dev_get (dev); |
895 | dn = pci_device_to_OF_node(dev); | |
896 | PCI_DN(dn)->pcidev = dev; | |
897 | ||
1da177e4 LT |
898 | pci_addr_cache_insert_device (dev); |
899 | } | |
56b0fca3 | 900 | EXPORT_SYMBOL_GPL(eeh_add_device_late); |
1da177e4 LT |
901 | |
902 | /** | |
903 | * eeh_remove_device - undo EEH setup for the indicated pci device | |
904 | * @dev: pci device to be removed | |
905 | * | |
906 | * This routine should be when a device is removed from a running | |
907 | * system (e.g. by hotplug or dlpar). | |
908 | */ | |
909 | void eeh_remove_device(struct pci_dev *dev) | |
910 | { | |
56b0fca3 | 911 | struct device_node *dn; |
1da177e4 LT |
912 | if (!dev || !eeh_subsystem_enabled) |
913 | return; | |
914 | ||
915 | /* Unregister the device with the EEH/PCI address search system */ | |
916 | #ifdef DEBUG | |
982245f0 | 917 | printk(KERN_DEBUG "EEH: remove device %s\n", pci_name(dev)); |
1da177e4 LT |
918 | #endif |
919 | pci_addr_cache_remove_device(dev); | |
56b0fca3 LV |
920 | |
921 | dn = pci_device_to_OF_node(dev); | |
922 | PCI_DN(dn)->pcidev = NULL; | |
923 | pci_dev_put (dev); | |
1da177e4 | 924 | } |
56b0fca3 | 925 | EXPORT_SYMBOL_GPL(eeh_remove_device); |
1da177e4 LT |
926 | |
927 | static int proc_eeh_show(struct seq_file *m, void *v) | |
928 | { | |
929 | unsigned int cpu; | |
930 | unsigned long ffs = 0, positives = 0, failures = 0; | |
931 | unsigned long resets = 0; | |
177bc936 | 932 | unsigned long no_dev = 0, no_dn = 0, no_cfg = 0, no_check = 0; |
1da177e4 LT |
933 | |
934 | for_each_cpu(cpu) { | |
935 | ffs += per_cpu(total_mmio_ffs, cpu); | |
936 | positives += per_cpu(false_positives, cpu); | |
937 | failures += per_cpu(ignored_failures, cpu); | |
938 | resets += per_cpu(slot_resets, cpu); | |
177bc936 LV |
939 | no_dev += per_cpu(no_device, cpu); |
940 | no_dn += per_cpu(no_dn, cpu); | |
941 | no_cfg += per_cpu(no_cfg_addr, cpu); | |
942 | no_check += per_cpu(ignored_check, cpu); | |
1da177e4 LT |
943 | } |
944 | ||
945 | if (0 == eeh_subsystem_enabled) { | |
946 | seq_printf(m, "EEH Subsystem is globally disabled\n"); | |
947 | seq_printf(m, "eeh_total_mmio_ffs=%ld\n", ffs); | |
948 | } else { | |
949 | seq_printf(m, "EEH Subsystem is enabled\n"); | |
177bc936 LV |
950 | seq_printf(m, |
951 | "no device=%ld\n" | |
952 | "no device node=%ld\n" | |
953 | "no config address=%ld\n" | |
954 | "check not wanted=%ld\n" | |
955 | "eeh_total_mmio_ffs=%ld\n" | |
956 | "eeh_false_positives=%ld\n" | |
957 | "eeh_ignored_failures=%ld\n" | |
958 | "eeh_slot_resets=%ld\n", | |
959 | no_dev, no_dn, no_cfg, no_check, | |
960 | ffs, positives, failures, resets); | |
1da177e4 LT |
961 | } |
962 | ||
963 | return 0; | |
964 | } | |
965 | ||
966 | static int proc_eeh_open(struct inode *inode, struct file *file) | |
967 | { | |
968 | return single_open(file, proc_eeh_show, NULL); | |
969 | } | |
970 | ||
971 | static struct file_operations proc_eeh_operations = { | |
972 | .open = proc_eeh_open, | |
973 | .read = seq_read, | |
974 | .llseek = seq_lseek, | |
975 | .release = single_release, | |
976 | }; | |
977 | ||
978 | static int __init eeh_init_proc(void) | |
979 | { | |
980 | struct proc_dir_entry *e; | |
981 | ||
982 | if (systemcfg->platform & PLATFORM_PSERIES) { | |
983 | e = create_proc_entry("ppc64/eeh", 0, NULL); | |
984 | if (e) | |
985 | e->proc_fops = &proc_eeh_operations; | |
986 | } | |
987 | ||
988 | return 0; | |
989 | } | |
990 | __initcall(eeh_init_proc); |