[linux-block.git] / arch / ppc64 / kernel / cpu_setup_power4.S

/*
 * This file contains low level CPU setup functions.
 *    Copyright (C) 2003 Benjamin Herrenschmidt (benh@kernel.crashing.org)
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version
 * 2 of the License, or (at your option) any later version.
 *
 */

#include <linux/config.h>
#include <asm/processor.h>
#include <asm/page.h>
#include <asm/cputable.h>
#include <asm/ppc_asm.h>
#include <asm/asm-offsets.h>
#include <asm/cache.h>

_GLOBAL(__970_cpu_preinit)
	/*
	 * Do nothing if not running in HV mode
	 */
	mfmsr	r0
	rldicl.	r0,r0,4,63
	beqlr

	/*
	 * Deal only with PPC970 and PPC970FX.
	 */
	mfspr	r0,SPRN_PVR
	srwi	r0,r0,16
	cmpwi	r0,0x39
	beq	1f
	cmpwi	r0,0x3c
	beq	1f
	cmpwi	r0,0x44
	bnelr
1:

	/* Make sure HID4:rm_ci is off before MMU is turned off, that large
	 * pages are enabled with HID4:61 and clear HID5:DCBZ_size and
	 * HID5:DCBZ32_ill
	 */
	li	r0,0
	mfspr	r3,SPRN_HID4
	rldimi	r3,r0,40,23	/* clear bit 23 (rm_ci) */
	rldimi	r3,r0,2,61	/* clear bit 61 (lg_pg_en) */
	sync
	mtspr	SPRN_HID4,r3
	isync
	sync
	mfspr	r3,SPRN_HID5
	rldimi	r3,r0,6,56	/* clear bits 56 & 57 (DCBZ*) */
	sync
	mtspr	SPRN_HID5,r3
	isync
	sync

	/* Setup some basic HID1 features */
	mfspr	r0,SPRN_HID1
	li	r3,0x1200		/* enable i-fetch cacheability */
	sldi	r3,r3,44		/* and prefetch */
	or	r0,r0,r3
	mtspr	SPRN_HID1,r0
	mtspr	SPRN_HID1,r0
	isync

	/* Clear HIOR */
	li	r0,0
	sync
	mtspr	SPRN_HIOR,0		/* Clear interrupt prefix */
	isync
	blr

_GLOBAL(__setup_cpu_power4)
	blr

_GLOBAL(__setup_cpu_be)
        /* Set large page sizes LP=0: 16MB, LP=1: 64KB */
        addi    r3, 0,  0
        ori     r3, r3, HID6_LB
        sldi    r3, r3, 32
        nor     r3, r3, r3
        mfspr   r4, SPRN_HID6
        and     r4, r4, r3
        addi    r3, 0, 0x02000
        sldi    r3, r3, 32
        or      r4, r4, r3
        mtspr   SPRN_HID6, r4
	blr

_GLOBAL(__setup_cpu_ppc970)
	mfspr	r0,SPRN_HID0
	li	r11,5			/* clear DOZE and SLEEP */
	rldimi	r0,r11,52,8		/* set NAP and DPM */
	mtspr	SPRN_HID0,r0
	mfspr	r0,SPRN_HID0
	mfspr	r0,SPRN_HID0
	mfspr	r0,SPRN_HID0
	mfspr	r0,SPRN_HID0
	mfspr	r0,SPRN_HID0
	mfspr	r0,SPRN_HID0
	sync
	isync
	blr

/* Definitions for the table use to save CPU states */
#define CS_HID0		0
#define CS_HID1		8
#define	CS_HID4		16
#define CS_HID5		24
#define CS_SIZE		32

	.data
	.balign	L1_CACHE_BYTES,0
cpu_state_storage:	
	.space	CS_SIZE
	.balign	L1_CACHE_BYTES,0
	.text
	
/* Called in normal context to backup CPU 0 state. This
 * does not include cache settings. This function is also
 * called for machine sleep. This does not include the MMU
 * setup, BATs, etc... but rather the "special" registers
 * like HID0, HID1, HID4, etc...
 */
_GLOBAL(__save_cpu_setup)
	/* Some CR fields are volatile, we back it up all */
	mfcr	r7

	/* Get storage ptr */
	LOADADDR(r5,cpu_state_storage)

	/* We only deal with 970 for now */
	mfspr	r0,SPRN_PVR
	srwi	r0,r0,16
	cmpwi	r0,0x39
	beq	1f
	cmpwi	r0,0x3c
	beq	1f
	cmpwi	r0,0x44
	bne	2f

1:	/* Save HID0,1,4 and 5 */
	mfspr	r3,SPRN_HID0
	std	r3,CS_HID0(r5)
	mfspr	r3,SPRN_HID1
	std	r3,CS_HID1(r5)
	mfspr	r3,SPRN_HID4
	std	r3,CS_HID4(r5)
	mfspr	r3,SPRN_HID5
	std	r3,CS_HID5(r5)
	
2:
	mtcr	r7
	blr

/* Called with no MMU context (typically MSR:IR/DR off) to
 * restore CPU state as backed up by the previous
 * function. This does not include cache setting
 */
_GLOBAL(__restore_cpu_setup)
	/* Get storage ptr (FIXME when using anton reloc as we
	 * are running with translation disabled here
	 */
	LOADADDR(r5,cpu_state_storage)

	/* We only deal with 970 for now */
	mfspr	r0,SPRN_PVR
	srwi	r0,r0,16
	cmpwi	r0,0x39
	beq	1f
	cmpwi	r0,0x3c
	beq	1f
	cmpwi	r0,0x44
	bnelr

1:	/* Before accessing memory, we make sure rm_ci is clear */
	li	r0,0
	mfspr	r3,SPRN_HID4
	rldimi	r3,r0,40,23	/* clear bit 23 (rm_ci) */
	sync
	mtspr	SPRN_HID4,r3
	isync
	sync

	/* Clear interrupt prefix */
	li	r0,0
	sync
	mtspr	SPRN_HIOR,0
	isync

	/* Restore HID0 */
	ld	r3,CS_HID0(r5)
	sync
	isync
	mtspr	SPRN_HID0,r3
	mfspr	r3,SPRN_HID0
	mfspr	r3,SPRN_HID0
	mfspr	r3,SPRN_HID0
	mfspr	r3,SPRN_HID0
	mfspr	r3,SPRN_HID0
	mfspr	r3,SPRN_HID0
	sync
	isync

	/* Restore HID1 */
	ld	r3,CS_HID1(r5)
	sync
	isync
	mtspr	SPRN_HID1,r3
	mtspr	SPRN_HID1,r3
	sync
	isync
	
	/* Restore HID4 */
	ld	r3,CS_HID4(r5)
	sync
	isync
	mtspr	SPRN_HID4,r3
	sync
	isync

	/* Restore HID5 */
	ld	r3,CS_HID5(r5)
	sync
	isync
	mtspr	SPRN_HID5,r3
	sync
	isync
	blr
Commit	Line	Data
1da177e4 LT	1	/*
	2	* This file contains low level CPU setup functions.
	3	* Copyright (C) 2003 Benjamin Herrenschmidt (benh@kernel.crashing.org)
	4	*
	5	* This program is free software; you can redistribute it and/or
	6	* modify it under the terms of the GNU General Public License
	7	* as published by the Free Software Foundation; either version
	8	* 2 of the License, or (at your option) any later version.
	9	*
	10	*/
	11
	12	#include <linux/config.h>
	13	#include <asm/processor.h>
	14	#include <asm/page.h>
1da177e4 LT	15	#include <asm/cputable.h>
1da177e4 LT	16	#include <asm/ppc_asm.h>
0013a854	17	#include <asm/asm-offsets.h>
1da177e4 LT	18	#include <asm/cache.h>
	19
	20	_GLOBAL(__970_cpu_preinit)
	21	/*
	22	* Do nothing if not running in HV mode
	23	*/
	24	mfmsr r0
	25	rldicl. r0,r0,4,63
	26	beqlr
	27
	28	/*
	29	* Deal only with PPC970 and PPC970FX.
	30	*/
	31	mfspr r0,SPRN_PVR
	32	srwi r0,r0,16
f264cc28 OJ	33	cmpwi r0,0x39
	34	beq 1f
	35	cmpwi r0,0x3c
	36	beq 1f
	37	cmpwi r0,0x44
1da177e4	38	bnelr
f264cc28	39	1:
1da177e4 LT	40
	41	/* Make sure HID4:rm_ci is off before MMU is turned off, that large
	42	* pages are enabled with HID4:61 and clear HID5:DCBZ_size and
	43	* HID5:DCBZ32_ill
	44	*/
	45	li r0,0
	46	mfspr r3,SPRN_HID4
	47	rldimi r3,r0,40,23 /* clear bit 23 (rm_ci) */
	48	rldimi r3,r0,2,61 /* clear bit 61 (lg_pg_en) */
	49	sync
	50	mtspr SPRN_HID4,r3
	51	isync
	52	sync
	53	mfspr r3,SPRN_HID5
	54	rldimi r3,r0,6,56 /* clear bits 56 & 57 (DCBZ) /
	55	sync
	56	mtspr SPRN_HID5,r3
	57	isync
	58	sync
	59
	60	/* Setup some basic HID1 features */
	61	mfspr r0,SPRN_HID1
	62	li r3,0x1200 /* enable i-fetch cacheability */
	63	sldi r3,r3,44 /* and prefetch */
	64	or r0,r0,r3
	65	mtspr SPRN_HID1,r0
	66	mtspr SPRN_HID1,r0
	67	isync
	68
	69	/* Clear HIOR */
	70	li r0,0
	71	sync
	72	mtspr SPRN_HIOR,0 /* Clear interrupt prefix */
	73	isync
	74	blr
	75
	76	_GLOBAL(__setup_cpu_power4)
	77	blr
fef1c772 AB	78
	79	_GLOBAL(__setup_cpu_be)
	80	/* Set large page sizes LP=0: 16MB, LP=1: 64KB */
	81	addi r3, 0, 0
	82	ori r3, r3, HID6_LB
	83	sldi r3, r3, 32
	84	nor r3, r3, r3
	85	mfspr r4, SPRN_HID6
	86	and r4, r4, r3
	87	addi r3, 0, 0x02000
	88	sldi r3, r3, 32
	89	or r4, r4, r3
	90	mtspr SPRN_HID6, r4
	91	blr
	92
1da177e4 LT	93	_GLOBAL(__setup_cpu_ppc970)
	94	mfspr r0,SPRN_HID0
	95	li r11,5 /* clear DOZE and SLEEP */
	96	rldimi r0,r11,52,8 /* set NAP and DPM */
	97	mtspr SPRN_HID0,r0
	98	mfspr r0,SPRN_HID0
	99	mfspr r0,SPRN_HID0
	100	mfspr r0,SPRN_HID0
	101	mfspr r0,SPRN_HID0
	102	mfspr r0,SPRN_HID0
	103	mfspr r0,SPRN_HID0
	104	sync
	105	isync
	106	blr
	107
	108	/* Definitions for the table use to save CPU states */
	109	#define CS_HID0 0
	110	#define CS_HID1 8
	111	#define CS_HID4 16
	112	#define CS_HID5 24
	113	#define CS_SIZE 32
	114
	115	.data
	116	.balign L1_CACHE_BYTES,0
	117	cpu_state_storage:
	118	.space CS_SIZE
	119	.balign L1_CACHE_BYTES,0
	120	.text
	121
	122	/* Called in normal context to backup CPU 0 state. This
	123	* does not include cache settings. This function is also
	124	* called for machine sleep. This does not include the MMU
	125	* setup, BATs, etc... but rather the "special" registers
	126	* like HID0, HID1, HID4, etc...
	127	*/
	128	_GLOBAL(__save_cpu_setup)
	129	/* Some CR fields are volatile, we back it up all */
	130	mfcr r7
	131
	132	/* Get storage ptr */
	133	LOADADDR(r5,cpu_state_storage)
	134
	135	/* We only deal with 970 for now */
	136	mfspr r0,SPRN_PVR
	137	srwi r0,r0,16
f264cc28 OJ	138	cmpwi r0,0x39
	139	beq 1f
	140	cmpwi r0,0x3c
	141	beq 1f
	142	cmpwi r0,0x44
	143	bne 2f
	144
	145	1: /* Save HID0,1,4 and 5 */
1da177e4 LT	146	mfspr r3,SPRN_HID0
	147	std r3,CS_HID0(r5)
	148	mfspr r3,SPRN_HID1
	149	std r3,CS_HID1(r5)
	150	mfspr r3,SPRN_HID4
	151	std r3,CS_HID4(r5)
	152	mfspr r3,SPRN_HID5
	153	std r3,CS_HID5(r5)
	154
f264cc28	155	2:
1da177e4 LT	156	mtcr r7
	157	blr
	158
	159	/* Called with no MMU context (typically MSR:IR/DR off) to
	160	* restore CPU state as backed up by the previous
	161	* function. This does not include cache setting
	162	*/
	163	_GLOBAL(__restore_cpu_setup)
	164	/* Get storage ptr (FIXME when using anton reloc as we
	165	* are running with translation disabled here
	166	*/
	167	LOADADDR(r5,cpu_state_storage)
	168
	169	/* We only deal with 970 for now */
	170	mfspr r0,SPRN_PVR
	171	srwi r0,r0,16
f264cc28 OJ	172	cmpwi r0,0x39
	173	beq 1f
	174	cmpwi r0,0x3c
	175	beq 1f
	176	cmpwi r0,0x44
	177	bnelr
1da177e4	178
f264cc28	179	1: /* Before accessing memory, we make sure rm_ci is clear */
1da177e4 LT	180	li r0,0
	181	mfspr r3,SPRN_HID4
	182	rldimi r3,r0,40,23 /* clear bit 23 (rm_ci) */
	183	sync
	184	mtspr SPRN_HID4,r3
	185	isync
	186	sync
	187
	188	/* Clear interrupt prefix */
	189	li r0,0
	190	sync
	191	mtspr SPRN_HIOR,0
	192	isync
	193
	194	/* Restore HID0 */
	195	ld r3,CS_HID0(r5)
	196	sync
	197	isync
	198	mtspr SPRN_HID0,r3
	199	mfspr r3,SPRN_HID0
	200	mfspr r3,SPRN_HID0
	201	mfspr r3,SPRN_HID0
	202	mfspr r3,SPRN_HID0
	203	mfspr r3,SPRN_HID0
	204	mfspr r3,SPRN_HID0
	205	sync
	206	isync
	207
	208	/* Restore HID1 */
	209	ld r3,CS_HID1(r5)
	210	sync
	211	isync
	212	mtspr SPRN_HID1,r3
	213	mtspr SPRN_HID1,r3
	214	sync
	215	isync
	216
	217	/* Restore HID4 */
	218	ld r3,CS_HID4(r5)
	219	sync
	220	isync
	221	mtspr SPRN_HID4,r3
	222	sync
	223	isync
	224
	225	/* Restore HID5 */
	226	ld r3,CS_HID5(r5)
	227	sync
	228	isync
	229	mtspr SPRN_HID5,r3
	230	sync
	231	isync
1da177e4 LT	232	blr
1da177e4 LT	233