Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
1da177e4 LT |
2 | * Common routines for the Marvell/Galileo Discovery line of host bridges |
3 | * (gt64260, mv64360, mv64460, ...). | |
4 | * | |
5 | * Author: Mark A. Greer <mgreer@mvista.com> | |
6 | * | |
7 | * 2004 (c) MontaVista, Software, Inc. This file is licensed under | |
8 | * the terms of the GNU General Public License version 2. This program | |
9 | * is licensed "as is" without any warranty of any kind, whether express | |
10 | * or implied. | |
11 | */ | |
12 | #include <linux/kernel.h> | |
13 | #include <linux/init.h> | |
14 | #include <linux/pci.h> | |
15 | #include <linux/slab.h> | |
16 | #include <linux/module.h> | |
17 | #include <linux/string.h> | |
1da177e4 LT |
18 | #include <linux/spinlock.h> |
19 | #include <linux/mv643xx.h> | |
d052d1be | 20 | #include <linux/platform_device.h> |
1da177e4 LT |
21 | |
22 | #include <asm/byteorder.h> | |
23 | #include <asm/io.h> | |
24 | #include <asm/irq.h> | |
25 | #include <asm/uaccess.h> | |
26 | #include <asm/machdep.h> | |
27 | #include <asm/pci-bridge.h> | |
28 | #include <asm/delay.h> | |
29 | #include <asm/mv64x60.h> | |
30 | ||
31 | ||
d01c08c9 | 32 | u8 mv64x60_pci_exclude_bridge = 1; |
a9f6a0dd | 33 | DEFINE_SPINLOCK(mv64x60_lock); |
1da177e4 | 34 | |
d01c08c9 | 35 | static phys_addr_t mv64x60_bridge_pbase; |
a7625d6e | 36 | static void __iomem *mv64x60_bridge_vbase; |
1da177e4 | 37 | static u32 mv64x60_bridge_type = MV64x60_TYPE_INVALID; |
d01c08c9 MG |
38 | static u32 mv64x60_bridge_rev; |
39 | #if defined(CONFIG_SYSFS) && !defined(CONFIG_GT64260) | |
40 | static struct pci_controller sysfs_hose_a; | |
41 | #endif | |
1da177e4 LT |
42 | |
43 | static u32 gt64260_translate_size(u32 base, u32 size, u32 num_bits); | |
44 | static u32 gt64260_untranslate_size(u32 base, u32 size, u32 num_bits); | |
45 | static void gt64260_set_pci2mem_window(struct pci_controller *hose, u32 bus, | |
46 | u32 window, u32 base); | |
47 | static void gt64260_set_pci2regs_window(struct mv64x60_handle *bh, | |
48 | struct pci_controller *hose, u32 bus, u32 base); | |
49 | static u32 gt64260_is_enabled_32bit(struct mv64x60_handle *bh, u32 window); | |
50 | static void gt64260_enable_window_32bit(struct mv64x60_handle *bh, u32 window); | |
51 | static void gt64260_disable_window_32bit(struct mv64x60_handle *bh, u32 window); | |
52 | static void gt64260_enable_window_64bit(struct mv64x60_handle *bh, u32 window); | |
53 | static void gt64260_disable_window_64bit(struct mv64x60_handle *bh, u32 window); | |
54 | static void gt64260_disable_all_windows(struct mv64x60_handle *bh, | |
55 | struct mv64x60_setup_info *si); | |
56 | static void gt64260a_chip_specific_init(struct mv64x60_handle *bh, | |
57 | struct mv64x60_setup_info *si); | |
58 | static void gt64260b_chip_specific_init(struct mv64x60_handle *bh, | |
59 | struct mv64x60_setup_info *si); | |
60 | ||
61 | static u32 mv64360_translate_size(u32 base, u32 size, u32 num_bits); | |
62 | static u32 mv64360_untranslate_size(u32 base, u32 size, u32 num_bits); | |
63 | static void mv64360_set_pci2mem_window(struct pci_controller *hose, u32 bus, | |
64 | u32 window, u32 base); | |
65 | static void mv64360_set_pci2regs_window(struct mv64x60_handle *bh, | |
66 | struct pci_controller *hose, u32 bus, u32 base); | |
67 | static u32 mv64360_is_enabled_32bit(struct mv64x60_handle *bh, u32 window); | |
68 | static void mv64360_enable_window_32bit(struct mv64x60_handle *bh, u32 window); | |
69 | static void mv64360_disable_window_32bit(struct mv64x60_handle *bh, u32 window); | |
70 | static void mv64360_enable_window_64bit(struct mv64x60_handle *bh, u32 window); | |
71 | static void mv64360_disable_window_64bit(struct mv64x60_handle *bh, u32 window); | |
72 | static void mv64360_disable_all_windows(struct mv64x60_handle *bh, | |
73 | struct mv64x60_setup_info *si); | |
74 | static void mv64360_config_io2mem_windows(struct mv64x60_handle *bh, | |
75 | struct mv64x60_setup_info *si, | |
76 | u32 mem_windows[MV64x60_CPU2MEM_WINDOWS][2]); | |
77 | static void mv64360_set_mpsc2regs_window(struct mv64x60_handle *bh, u32 base); | |
78 | static void mv64360_chip_specific_init(struct mv64x60_handle *bh, | |
79 | struct mv64x60_setup_info *si); | |
80 | static void mv64460_chip_specific_init(struct mv64x60_handle *bh, | |
81 | struct mv64x60_setup_info *si); | |
82 | ||
83 | ||
84 | /* | |
85 | * Define tables that have the chip-specific info for each type of | |
86 | * Marvell bridge chip. | |
87 | */ | |
88 | static struct mv64x60_chip_info gt64260a_ci __initdata = { /* GT64260A */ | |
89 | .translate_size = gt64260_translate_size, | |
90 | .untranslate_size = gt64260_untranslate_size, | |
91 | .set_pci2mem_window = gt64260_set_pci2mem_window, | |
92 | .set_pci2regs_window = gt64260_set_pci2regs_window, | |
93 | .is_enabled_32bit = gt64260_is_enabled_32bit, | |
94 | .enable_window_32bit = gt64260_enable_window_32bit, | |
95 | .disable_window_32bit = gt64260_disable_window_32bit, | |
96 | .enable_window_64bit = gt64260_enable_window_64bit, | |
97 | .disable_window_64bit = gt64260_disable_window_64bit, | |
98 | .disable_all_windows = gt64260_disable_all_windows, | |
99 | .chip_specific_init = gt64260a_chip_specific_init, | |
100 | .window_tab_32bit = gt64260_32bit_windows, | |
101 | .window_tab_64bit = gt64260_64bit_windows, | |
102 | }; | |
103 | ||
104 | static struct mv64x60_chip_info gt64260b_ci __initdata = { /* GT64260B */ | |
105 | .translate_size = gt64260_translate_size, | |
106 | .untranslate_size = gt64260_untranslate_size, | |
107 | .set_pci2mem_window = gt64260_set_pci2mem_window, | |
108 | .set_pci2regs_window = gt64260_set_pci2regs_window, | |
109 | .is_enabled_32bit = gt64260_is_enabled_32bit, | |
110 | .enable_window_32bit = gt64260_enable_window_32bit, | |
111 | .disable_window_32bit = gt64260_disable_window_32bit, | |
112 | .enable_window_64bit = gt64260_enable_window_64bit, | |
113 | .disable_window_64bit = gt64260_disable_window_64bit, | |
114 | .disable_all_windows = gt64260_disable_all_windows, | |
115 | .chip_specific_init = gt64260b_chip_specific_init, | |
116 | .window_tab_32bit = gt64260_32bit_windows, | |
117 | .window_tab_64bit = gt64260_64bit_windows, | |
118 | }; | |
119 | ||
120 | static struct mv64x60_chip_info mv64360_ci __initdata = { /* MV64360 */ | |
121 | .translate_size = mv64360_translate_size, | |
122 | .untranslate_size = mv64360_untranslate_size, | |
123 | .set_pci2mem_window = mv64360_set_pci2mem_window, | |
124 | .set_pci2regs_window = mv64360_set_pci2regs_window, | |
125 | .is_enabled_32bit = mv64360_is_enabled_32bit, | |
126 | .enable_window_32bit = mv64360_enable_window_32bit, | |
127 | .disable_window_32bit = mv64360_disable_window_32bit, | |
128 | .enable_window_64bit = mv64360_enable_window_64bit, | |
129 | .disable_window_64bit = mv64360_disable_window_64bit, | |
130 | .disable_all_windows = mv64360_disable_all_windows, | |
131 | .config_io2mem_windows = mv64360_config_io2mem_windows, | |
132 | .set_mpsc2regs_window = mv64360_set_mpsc2regs_window, | |
133 | .chip_specific_init = mv64360_chip_specific_init, | |
134 | .window_tab_32bit = mv64360_32bit_windows, | |
135 | .window_tab_64bit = mv64360_64bit_windows, | |
136 | }; | |
137 | ||
138 | static struct mv64x60_chip_info mv64460_ci __initdata = { /* MV64460 */ | |
139 | .translate_size = mv64360_translate_size, | |
140 | .untranslate_size = mv64360_untranslate_size, | |
141 | .set_pci2mem_window = mv64360_set_pci2mem_window, | |
142 | .set_pci2regs_window = mv64360_set_pci2regs_window, | |
143 | .is_enabled_32bit = mv64360_is_enabled_32bit, | |
144 | .enable_window_32bit = mv64360_enable_window_32bit, | |
145 | .disable_window_32bit = mv64360_disable_window_32bit, | |
146 | .enable_window_64bit = mv64360_enable_window_64bit, | |
147 | .disable_window_64bit = mv64360_disable_window_64bit, | |
148 | .disable_all_windows = mv64360_disable_all_windows, | |
149 | .config_io2mem_windows = mv64360_config_io2mem_windows, | |
150 | .set_mpsc2regs_window = mv64360_set_mpsc2regs_window, | |
151 | .chip_specific_init = mv64460_chip_specific_init, | |
152 | .window_tab_32bit = mv64360_32bit_windows, | |
153 | .window_tab_64bit = mv64360_64bit_windows, | |
154 | }; | |
155 | ||
156 | /* | |
157 | ***************************************************************************** | |
158 | * | |
159 | * Platform Device Definitions | |
160 | * | |
161 | ***************************************************************************** | |
162 | */ | |
163 | #ifdef CONFIG_SERIAL_MPSC | |
164 | static struct mpsc_shared_pdata mv64x60_mpsc_shared_pdata = { | |
165 | .mrr_val = 0x3ffffe38, | |
166 | .rcrr_val = 0, | |
167 | .tcrr_val = 0, | |
168 | .intr_cause_val = 0, | |
169 | .intr_mask_val = 0, | |
170 | }; | |
171 | ||
172 | static struct resource mv64x60_mpsc_shared_resources[] = { | |
173 | /* Do not change the order of the IORESOURCE_MEM resources */ | |
174 | [0] = { | |
175 | .name = "mpsc routing base", | |
176 | .start = MV64x60_MPSC_ROUTING_OFFSET, | |
177 | .end = MV64x60_MPSC_ROUTING_OFFSET + | |
178 | MPSC_ROUTING_REG_BLOCK_SIZE - 1, | |
179 | .flags = IORESOURCE_MEM, | |
180 | }, | |
181 | [1] = { | |
182 | .name = "sdma intr base", | |
183 | .start = MV64x60_SDMA_INTR_OFFSET, | |
184 | .end = MV64x60_SDMA_INTR_OFFSET + | |
185 | MPSC_SDMA_INTR_REG_BLOCK_SIZE - 1, | |
186 | .flags = IORESOURCE_MEM, | |
187 | }, | |
188 | }; | |
189 | ||
190 | static struct platform_device mpsc_shared_device = { /* Shared device */ | |
191 | .name = MPSC_SHARED_NAME, | |
192 | .id = 0, | |
193 | .num_resources = ARRAY_SIZE(mv64x60_mpsc_shared_resources), | |
194 | .resource = mv64x60_mpsc_shared_resources, | |
195 | .dev = { | |
196 | .platform_data = &mv64x60_mpsc_shared_pdata, | |
197 | }, | |
198 | }; | |
199 | ||
200 | static struct mpsc_pdata mv64x60_mpsc0_pdata = { | |
201 | .mirror_regs = 0, | |
202 | .cache_mgmt = 0, | |
203 | .max_idle = 0, | |
204 | .default_baud = 9600, | |
205 | .default_bits = 8, | |
206 | .default_parity = 'n', | |
207 | .default_flow = 'n', | |
208 | .chr_1_val = 0x00000000, | |
209 | .chr_2_val = 0x00000000, | |
210 | .chr_10_val = 0x00000003, | |
211 | .mpcr_val = 0, | |
212 | .bcr_val = 0, | |
213 | .brg_can_tune = 0, | |
214 | .brg_clk_src = 8, /* Default to TCLK */ | |
215 | .brg_clk_freq = 100000000, /* Default to 100 MHz */ | |
216 | }; | |
217 | ||
218 | static struct resource mv64x60_mpsc0_resources[] = { | |
219 | /* Do not change the order of the IORESOURCE_MEM resources */ | |
220 | [0] = { | |
221 | .name = "mpsc 0 base", | |
222 | .start = MV64x60_MPSC_0_OFFSET, | |
223 | .end = MV64x60_MPSC_0_OFFSET + MPSC_REG_BLOCK_SIZE - 1, | |
224 | .flags = IORESOURCE_MEM, | |
225 | }, | |
226 | [1] = { | |
227 | .name = "sdma 0 base", | |
228 | .start = MV64x60_SDMA_0_OFFSET, | |
229 | .end = MV64x60_SDMA_0_OFFSET + MPSC_SDMA_REG_BLOCK_SIZE - 1, | |
230 | .flags = IORESOURCE_MEM, | |
231 | }, | |
232 | [2] = { | |
233 | .name = "brg 0 base", | |
234 | .start = MV64x60_BRG_0_OFFSET, | |
235 | .end = MV64x60_BRG_0_OFFSET + MPSC_BRG_REG_BLOCK_SIZE - 1, | |
236 | .flags = IORESOURCE_MEM, | |
237 | }, | |
238 | [3] = { | |
239 | .name = "sdma 0 irq", | |
240 | .start = MV64x60_IRQ_SDMA_0, | |
241 | .end = MV64x60_IRQ_SDMA_0, | |
242 | .flags = IORESOURCE_IRQ, | |
243 | }, | |
244 | }; | |
245 | ||
246 | static struct platform_device mpsc0_device = { | |
247 | .name = MPSC_CTLR_NAME, | |
248 | .id = 0, | |
249 | .num_resources = ARRAY_SIZE(mv64x60_mpsc0_resources), | |
250 | .resource = mv64x60_mpsc0_resources, | |
251 | .dev = { | |
252 | .platform_data = &mv64x60_mpsc0_pdata, | |
253 | }, | |
254 | }; | |
255 | ||
256 | static struct mpsc_pdata mv64x60_mpsc1_pdata = { | |
257 | .mirror_regs = 0, | |
258 | .cache_mgmt = 0, | |
259 | .max_idle = 0, | |
260 | .default_baud = 9600, | |
261 | .default_bits = 8, | |
262 | .default_parity = 'n', | |
263 | .default_flow = 'n', | |
264 | .chr_1_val = 0x00000000, | |
265 | .chr_1_val = 0x00000000, | |
266 | .chr_2_val = 0x00000000, | |
267 | .chr_10_val = 0x00000003, | |
268 | .mpcr_val = 0, | |
269 | .bcr_val = 0, | |
270 | .brg_can_tune = 0, | |
271 | .brg_clk_src = 8, /* Default to TCLK */ | |
272 | .brg_clk_freq = 100000000, /* Default to 100 MHz */ | |
273 | }; | |
274 | ||
275 | static struct resource mv64x60_mpsc1_resources[] = { | |
276 | /* Do not change the order of the IORESOURCE_MEM resources */ | |
277 | [0] = { | |
278 | .name = "mpsc 1 base", | |
279 | .start = MV64x60_MPSC_1_OFFSET, | |
280 | .end = MV64x60_MPSC_1_OFFSET + MPSC_REG_BLOCK_SIZE - 1, | |
281 | .flags = IORESOURCE_MEM, | |
282 | }, | |
283 | [1] = { | |
284 | .name = "sdma 1 base", | |
285 | .start = MV64x60_SDMA_1_OFFSET, | |
286 | .end = MV64x60_SDMA_1_OFFSET + MPSC_SDMA_REG_BLOCK_SIZE - 1, | |
287 | .flags = IORESOURCE_MEM, | |
288 | }, | |
289 | [2] = { | |
290 | .name = "brg 1 base", | |
291 | .start = MV64x60_BRG_1_OFFSET, | |
292 | .end = MV64x60_BRG_1_OFFSET + MPSC_BRG_REG_BLOCK_SIZE - 1, | |
293 | .flags = IORESOURCE_MEM, | |
294 | }, | |
295 | [3] = { | |
296 | .name = "sdma 1 irq", | |
297 | .start = MV64360_IRQ_SDMA_1, | |
298 | .end = MV64360_IRQ_SDMA_1, | |
299 | .flags = IORESOURCE_IRQ, | |
300 | }, | |
301 | }; | |
302 | ||
303 | static struct platform_device mpsc1_device = { | |
304 | .name = MPSC_CTLR_NAME, | |
305 | .id = 1, | |
306 | .num_resources = ARRAY_SIZE(mv64x60_mpsc1_resources), | |
307 | .resource = mv64x60_mpsc1_resources, | |
308 | .dev = { | |
309 | .platform_data = &mv64x60_mpsc1_pdata, | |
310 | }, | |
311 | }; | |
312 | #endif | |
313 | ||
6651a5c3 | 314 | #if defined(CONFIG_MV643XX_ETH) || defined(CONFIG_MV643XX_ETH_MODULE) |
1da177e4 LT |
315 | static struct resource mv64x60_eth_shared_resources[] = { |
316 | [0] = { | |
317 | .name = "ethernet shared base", | |
318 | .start = MV643XX_ETH_SHARED_REGS, | |
319 | .end = MV643XX_ETH_SHARED_REGS + | |
320 | MV643XX_ETH_SHARED_REGS_SIZE - 1, | |
321 | .flags = IORESOURCE_MEM, | |
322 | }, | |
323 | }; | |
324 | ||
325 | static struct platform_device mv64x60_eth_shared_device = { | |
326 | .name = MV643XX_ETH_SHARED_NAME, | |
327 | .id = 0, | |
328 | .num_resources = ARRAY_SIZE(mv64x60_eth_shared_resources), | |
329 | .resource = mv64x60_eth_shared_resources, | |
330 | }; | |
331 | ||
332 | #ifdef CONFIG_MV643XX_ETH_0 | |
333 | static struct resource mv64x60_eth0_resources[] = { | |
334 | [0] = { | |
335 | .name = "eth0 irq", | |
336 | .start = MV64x60_IRQ_ETH_0, | |
337 | .end = MV64x60_IRQ_ETH_0, | |
338 | .flags = IORESOURCE_IRQ, | |
339 | }, | |
340 | }; | |
341 | ||
84dd619e DF |
342 | static struct mv643xx_eth_platform_data eth0_pd = { |
343 | .port_number = 0, | |
344 | }; | |
1da177e4 LT |
345 | |
346 | static struct platform_device eth0_device = { | |
347 | .name = MV643XX_ETH_NAME, | |
348 | .id = 0, | |
349 | .num_resources = ARRAY_SIZE(mv64x60_eth0_resources), | |
350 | .resource = mv64x60_eth0_resources, | |
351 | .dev = { | |
352 | .platform_data = ð0_pd, | |
353 | }, | |
354 | }; | |
355 | #endif | |
356 | ||
357 | #ifdef CONFIG_MV643XX_ETH_1 | |
358 | static struct resource mv64x60_eth1_resources[] = { | |
359 | [0] = { | |
360 | .name = "eth1 irq", | |
361 | .start = MV64x60_IRQ_ETH_1, | |
362 | .end = MV64x60_IRQ_ETH_1, | |
363 | .flags = IORESOURCE_IRQ, | |
364 | }, | |
365 | }; | |
366 | ||
84dd619e DF |
367 | static struct mv643xx_eth_platform_data eth1_pd = { |
368 | .port_number = 1, | |
369 | }; | |
1da177e4 LT |
370 | |
371 | static struct platform_device eth1_device = { | |
372 | .name = MV643XX_ETH_NAME, | |
373 | .id = 1, | |
374 | .num_resources = ARRAY_SIZE(mv64x60_eth1_resources), | |
375 | .resource = mv64x60_eth1_resources, | |
376 | .dev = { | |
377 | .platform_data = ð1_pd, | |
378 | }, | |
379 | }; | |
380 | #endif | |
381 | ||
382 | #ifdef CONFIG_MV643XX_ETH_2 | |
383 | static struct resource mv64x60_eth2_resources[] = { | |
384 | [0] = { | |
385 | .name = "eth2 irq", | |
386 | .start = MV64x60_IRQ_ETH_2, | |
387 | .end = MV64x60_IRQ_ETH_2, | |
388 | .flags = IORESOURCE_IRQ, | |
389 | }, | |
390 | }; | |
391 | ||
84dd619e DF |
392 | static struct mv643xx_eth_platform_data eth2_pd = { |
393 | .port_number = 2, | |
394 | }; | |
1da177e4 LT |
395 | |
396 | static struct platform_device eth2_device = { | |
397 | .name = MV643XX_ETH_NAME, | |
398 | .id = 2, | |
399 | .num_resources = ARRAY_SIZE(mv64x60_eth2_resources), | |
400 | .resource = mv64x60_eth2_resources, | |
401 | .dev = { | |
402 | .platform_data = ð2_pd, | |
403 | }, | |
404 | }; | |
405 | #endif | |
406 | #endif | |
407 | ||
408 | #ifdef CONFIG_I2C_MV64XXX | |
409 | static struct mv64xxx_i2c_pdata mv64xxx_i2c_pdata = { | |
410 | .freq_m = 8, | |
411 | .freq_n = 3, | |
412 | .timeout = 1000, /* Default timeout of 1 second */ | |
413 | .retries = 1, | |
414 | }; | |
415 | ||
416 | static struct resource mv64xxx_i2c_resources[] = { | |
417 | /* Do not change the order of the IORESOURCE_MEM resources */ | |
418 | [0] = { | |
419 | .name = "mv64xxx i2c base", | |
420 | .start = MV64XXX_I2C_OFFSET, | |
421 | .end = MV64XXX_I2C_OFFSET + MV64XXX_I2C_REG_BLOCK_SIZE - 1, | |
422 | .flags = IORESOURCE_MEM, | |
423 | }, | |
424 | [1] = { | |
425 | .name = "mv64xxx i2c irq", | |
426 | .start = MV64x60_IRQ_I2C, | |
427 | .end = MV64x60_IRQ_I2C, | |
428 | .flags = IORESOURCE_IRQ, | |
429 | }, | |
430 | }; | |
431 | ||
432 | static struct platform_device i2c_device = { | |
433 | .name = MV64XXX_I2C_CTLR_NAME, | |
434 | .id = 0, | |
435 | .num_resources = ARRAY_SIZE(mv64xxx_i2c_resources), | |
436 | .resource = mv64xxx_i2c_resources, | |
437 | .dev = { | |
438 | .platform_data = &mv64xxx_i2c_pdata, | |
439 | }, | |
440 | }; | |
441 | #endif | |
442 | ||
d01c08c9 MG |
443 | #if defined(CONFIG_SYSFS) && !defined(CONFIG_GT64260) |
444 | static struct mv64xxx_pdata mv64xxx_pdata = { | |
445 | .hs_reg_valid = 0, | |
446 | }; | |
447 | ||
448 | static struct platform_device mv64xxx_device = { /* general mv64x60 stuff */ | |
449 | .name = MV64XXX_DEV_NAME, | |
450 | .id = 0, | |
451 | .dev = { | |
452 | .platform_data = &mv64xxx_pdata, | |
453 | }, | |
454 | }; | |
455 | #endif | |
456 | ||
1da177e4 LT |
457 | static struct platform_device *mv64x60_pd_devs[] __initdata = { |
458 | #ifdef CONFIG_SERIAL_MPSC | |
459 | &mpsc_shared_device, | |
460 | &mpsc0_device, | |
461 | &mpsc1_device, | |
462 | #endif | |
6651a5c3 | 463 | #if defined(CONFIG_MV643XX_ETH) || defined(CONFIG_MV643XX_ETH_MODULE) |
1da177e4 LT |
464 | &mv64x60_eth_shared_device, |
465 | #endif | |
466 | #ifdef CONFIG_MV643XX_ETH_0 | |
467 | ð0_device, | |
468 | #endif | |
469 | #ifdef CONFIG_MV643XX_ETH_1 | |
470 | ð1_device, | |
471 | #endif | |
472 | #ifdef CONFIG_MV643XX_ETH_2 | |
473 | ð2_device, | |
474 | #endif | |
475 | #ifdef CONFIG_I2C_MV64XXX | |
476 | &i2c_device, | |
477 | #endif | |
d01c08c9 MG |
478 | #if defined(CONFIG_SYSFS) && !defined(CONFIG_GT64260) |
479 | &mv64xxx_device, | |
480 | #endif | |
1da177e4 LT |
481 | }; |
482 | ||
483 | /* | |
484 | ***************************************************************************** | |
485 | * | |
486 | * Bridge Initialization Routines | |
487 | * | |
488 | ***************************************************************************** | |
489 | */ | |
490 | /* | |
491 | * mv64x60_init() | |
492 | * | |
a8de5ce9 | 493 | * Initialize the bridge based on setting passed in via 'si'. The bridge |
1da177e4 LT |
494 | * handle, 'bh', will be set so that it can be used to make subsequent |
495 | * calls to routines in this file. | |
496 | */ | |
497 | int __init | |
498 | mv64x60_init(struct mv64x60_handle *bh, struct mv64x60_setup_info *si) | |
499 | { | |
500 | u32 mem_windows[MV64x60_CPU2MEM_WINDOWS][2]; | |
501 | ||
502 | if (ppc_md.progress) | |
503 | ppc_md.progress("mv64x60 initialization", 0x0); | |
504 | ||
505 | spin_lock_init(&mv64x60_lock); | |
506 | mv64x60_early_init(bh, si); | |
507 | ||
508 | if (mv64x60_get_type(bh) || mv64x60_setup_for_chip(bh)) { | |
509 | iounmap(bh->v_base); | |
510 | bh->v_base = 0; | |
511 | if (ppc_md.progress) | |
512 | ppc_md.progress("mv64x60_init: Can't determine chip",0); | |
513 | return -1; | |
514 | } | |
515 | ||
516 | bh->ci->disable_all_windows(bh, si); | |
517 | mv64x60_get_mem_windows(bh, mem_windows); | |
518 | mv64x60_config_cpu2mem_windows(bh, si, mem_windows); | |
519 | ||
520 | if (bh->ci->config_io2mem_windows) | |
521 | bh->ci->config_io2mem_windows(bh, si, mem_windows); | |
522 | if (bh->ci->set_mpsc2regs_window) | |
523 | bh->ci->set_mpsc2regs_window(bh, si->phys_reg_base); | |
524 | ||
525 | if (si->pci_1.enable_bus) { | |
526 | bh->io_base_b = (u32)ioremap(si->pci_1.pci_io.cpu_base, | |
527 | si->pci_1.pci_io.size); | |
528 | isa_io_base = bh->io_base_b; | |
529 | } | |
530 | ||
531 | if (si->pci_0.enable_bus) { | |
532 | bh->io_base_a = (u32)ioremap(si->pci_0.pci_io.cpu_base, | |
533 | si->pci_0.pci_io.size); | |
534 | isa_io_base = bh->io_base_a; | |
535 | ||
536 | mv64x60_alloc_hose(bh, MV64x60_PCI0_CONFIG_ADDR, | |
537 | MV64x60_PCI0_CONFIG_DATA, &bh->hose_a); | |
538 | mv64x60_config_resources(bh->hose_a, &si->pci_0, bh->io_base_a); | |
539 | mv64x60_config_pci_params(bh->hose_a, &si->pci_0); | |
540 | ||
541 | mv64x60_config_cpu2pci_windows(bh, &si->pci_0, 0); | |
542 | mv64x60_config_pci2mem_windows(bh, bh->hose_a, &si->pci_0, 0, | |
543 | mem_windows); | |
544 | bh->ci->set_pci2regs_window(bh, bh->hose_a, 0, | |
545 | si->phys_reg_base); | |
546 | } | |
547 | ||
548 | if (si->pci_1.enable_bus) { | |
549 | mv64x60_alloc_hose(bh, MV64x60_PCI1_CONFIG_ADDR, | |
550 | MV64x60_PCI1_CONFIG_DATA, &bh->hose_b); | |
551 | mv64x60_config_resources(bh->hose_b, &si->pci_1, bh->io_base_b); | |
552 | mv64x60_config_pci_params(bh->hose_b, &si->pci_1); | |
553 | ||
554 | mv64x60_config_cpu2pci_windows(bh, &si->pci_1, 1); | |
555 | mv64x60_config_pci2mem_windows(bh, bh->hose_b, &si->pci_1, 1, | |
556 | mem_windows); | |
557 | bh->ci->set_pci2regs_window(bh, bh->hose_b, 1, | |
558 | si->phys_reg_base); | |
559 | } | |
560 | ||
561 | bh->ci->chip_specific_init(bh, si); | |
562 | mv64x60_pd_fixup(bh, mv64x60_pd_devs, ARRAY_SIZE(mv64x60_pd_devs)); | |
563 | ||
564 | return 0; | |
565 | } | |
566 | ||
567 | /* | |
568 | * mv64x60_early_init() | |
569 | * | |
570 | * Do some bridge work that must take place before we start messing with | |
571 | * the bridge for real. | |
572 | */ | |
573 | void __init | |
574 | mv64x60_early_init(struct mv64x60_handle *bh, struct mv64x60_setup_info *si) | |
575 | { | |
576 | struct pci_controller hose_a, hose_b; | |
577 | ||
578 | memset(bh, 0, sizeof(*bh)); | |
579 | ||
580 | bh->p_base = si->phys_reg_base; | |
581 | bh->v_base = ioremap(bh->p_base, MV64x60_INTERNAL_SPACE_SIZE); | |
582 | ||
583 | mv64x60_bridge_pbase = bh->p_base; | |
584 | mv64x60_bridge_vbase = bh->v_base; | |
585 | ||
586 | /* Assuming pci mode [reserved] bits 4:5 on 64260 are 0 */ | |
587 | bh->pci_mode_a = mv64x60_read(bh, MV64x60_PCI0_MODE) & | |
588 | MV64x60_PCIMODE_MASK; | |
589 | bh->pci_mode_b = mv64x60_read(bh, MV64x60_PCI1_MODE) & | |
590 | MV64x60_PCIMODE_MASK; | |
591 | ||
592 | /* Need temporary hose structs to call mv64x60_set_bus() */ | |
593 | memset(&hose_a, 0, sizeof(hose_a)); | |
594 | memset(&hose_b, 0, sizeof(hose_b)); | |
595 | setup_indirect_pci_nomap(&hose_a, bh->v_base + MV64x60_PCI0_CONFIG_ADDR, | |
596 | bh->v_base + MV64x60_PCI0_CONFIG_DATA); | |
597 | setup_indirect_pci_nomap(&hose_b, bh->v_base + MV64x60_PCI1_CONFIG_ADDR, | |
598 | bh->v_base + MV64x60_PCI1_CONFIG_DATA); | |
599 | bh->hose_a = &hose_a; | |
600 | bh->hose_b = &hose_b; | |
601 | ||
d01c08c9 MG |
602 | #if defined(CONFIG_SYSFS) && !defined(CONFIG_GT64260) |
603 | /* Save a copy of hose_a for sysfs functions -- hack */ | |
604 | memcpy(&sysfs_hose_a, &hose_a, sizeof(hose_a)); | |
605 | #endif | |
606 | ||
1da177e4 LT |
607 | mv64x60_set_bus(bh, 0, 0); |
608 | mv64x60_set_bus(bh, 1, 0); | |
609 | ||
610 | bh->hose_a = NULL; | |
611 | bh->hose_b = NULL; | |
612 | ||
613 | /* Clear bit 0 of PCI addr decode control so PCI->CPU remap 1:1 */ | |
614 | mv64x60_clr_bits(bh, MV64x60_PCI0_PCI_DECODE_CNTL, 0x00000001); | |
615 | mv64x60_clr_bits(bh, MV64x60_PCI1_PCI_DECODE_CNTL, 0x00000001); | |
616 | ||
617 | /* Bit 12 MUST be 0; set bit 27--don't auto-update cpu remap regs */ | |
618 | mv64x60_clr_bits(bh, MV64x60_CPU_CONFIG, (1<<12)); | |
619 | mv64x60_set_bits(bh, MV64x60_CPU_CONFIG, (1<<27)); | |
620 | ||
621 | mv64x60_set_bits(bh, MV64x60_PCI0_TO_RETRY, 0xffff); | |
622 | mv64x60_set_bits(bh, MV64x60_PCI1_TO_RETRY, 0xffff); | |
1da177e4 LT |
623 | } |
624 | ||
625 | /* | |
626 | ***************************************************************************** | |
627 | * | |
628 | * Window Config Routines | |
629 | * | |
630 | ***************************************************************************** | |
631 | */ | |
632 | /* | |
633 | * mv64x60_get_32bit_window() | |
634 | * | |
635 | * Determine the base address and size of a 32-bit window on the bridge. | |
636 | */ | |
637 | void __init | |
638 | mv64x60_get_32bit_window(struct mv64x60_handle *bh, u32 window, | |
639 | u32 *base, u32 *size) | |
640 | { | |
641 | u32 val, base_reg, size_reg, base_bits, size_bits; | |
642 | u32 (*get_from_field)(u32 val, u32 num_bits); | |
643 | ||
644 | base_reg = bh->ci->window_tab_32bit[window].base_reg; | |
645 | ||
646 | if (base_reg != 0) { | |
647 | size_reg = bh->ci->window_tab_32bit[window].size_reg; | |
648 | base_bits = bh->ci->window_tab_32bit[window].base_bits; | |
649 | size_bits = bh->ci->window_tab_32bit[window].size_bits; | |
650 | get_from_field= bh->ci->window_tab_32bit[window].get_from_field; | |
651 | ||
652 | val = mv64x60_read(bh, base_reg); | |
653 | *base = get_from_field(val, base_bits); | |
654 | ||
655 | if (size_reg != 0) { | |
656 | val = mv64x60_read(bh, size_reg); | |
657 | val = get_from_field(val, size_bits); | |
658 | *size = bh->ci->untranslate_size(*base, val, size_bits); | |
d01c08c9 | 659 | } else |
1da177e4 | 660 | *size = 0; |
d01c08c9 | 661 | } else { |
1da177e4 LT |
662 | *base = 0; |
663 | *size = 0; | |
664 | } | |
665 | ||
666 | pr_debug("get 32bit window: %d, base: 0x%x, size: 0x%x\n", | |
667 | window, *base, *size); | |
1da177e4 LT |
668 | } |
669 | ||
670 | /* | |
671 | * mv64x60_set_32bit_window() | |
672 | * | |
673 | * Set the base address and size of a 32-bit window on the bridge. | |
674 | */ | |
675 | void __init | |
676 | mv64x60_set_32bit_window(struct mv64x60_handle *bh, u32 window, | |
677 | u32 base, u32 size, u32 other_bits) | |
678 | { | |
679 | u32 val, base_reg, size_reg, base_bits, size_bits; | |
680 | u32 (*map_to_field)(u32 val, u32 num_bits); | |
681 | ||
682 | pr_debug("set 32bit window: %d, base: 0x%x, size: 0x%x, other: 0x%x\n", | |
683 | window, base, size, other_bits); | |
684 | ||
685 | base_reg = bh->ci->window_tab_32bit[window].base_reg; | |
686 | ||
687 | if (base_reg != 0) { | |
688 | size_reg = bh->ci->window_tab_32bit[window].size_reg; | |
689 | base_bits = bh->ci->window_tab_32bit[window].base_bits; | |
690 | size_bits = bh->ci->window_tab_32bit[window].size_bits; | |
691 | map_to_field = bh->ci->window_tab_32bit[window].map_to_field; | |
692 | ||
693 | val = map_to_field(base, base_bits) | other_bits; | |
694 | mv64x60_write(bh, base_reg, val); | |
695 | ||
696 | if (size_reg != 0) { | |
697 | val = bh->ci->translate_size(base, size, size_bits); | |
698 | val = map_to_field(val, size_bits); | |
699 | mv64x60_write(bh, size_reg, val); | |
700 | } | |
701 | ||
702 | (void)mv64x60_read(bh, base_reg); /* Flush FIFO */ | |
703 | } | |
1da177e4 LT |
704 | } |
705 | ||
706 | /* | |
707 | * mv64x60_get_64bit_window() | |
708 | * | |
709 | * Determine the base address and size of a 64-bit window on the bridge. | |
710 | */ | |
711 | void __init | |
712 | mv64x60_get_64bit_window(struct mv64x60_handle *bh, u32 window, | |
713 | u32 *base_hi, u32 *base_lo, u32 *size) | |
714 | { | |
715 | u32 val, base_lo_reg, size_reg, base_lo_bits, size_bits; | |
716 | u32 (*get_from_field)(u32 val, u32 num_bits); | |
717 | ||
718 | base_lo_reg = bh->ci->window_tab_64bit[window].base_lo_reg; | |
719 | ||
720 | if (base_lo_reg != 0) { | |
721 | size_reg = bh->ci->window_tab_64bit[window].size_reg; | |
722 | base_lo_bits = bh->ci->window_tab_64bit[window].base_lo_bits; | |
723 | size_bits = bh->ci->window_tab_64bit[window].size_bits; | |
724 | get_from_field= bh->ci->window_tab_64bit[window].get_from_field; | |
725 | ||
726 | *base_hi = mv64x60_read(bh, | |
727 | bh->ci->window_tab_64bit[window].base_hi_reg); | |
728 | ||
729 | val = mv64x60_read(bh, base_lo_reg); | |
730 | *base_lo = get_from_field(val, base_lo_bits); | |
731 | ||
732 | if (size_reg != 0) { | |
733 | val = mv64x60_read(bh, size_reg); | |
734 | val = get_from_field(val, size_bits); | |
735 | *size = bh->ci->untranslate_size(*base_lo, val, | |
736 | size_bits); | |
d01c08c9 | 737 | } else |
1da177e4 | 738 | *size = 0; |
d01c08c9 | 739 | } else { |
1da177e4 LT |
740 | *base_hi = 0; |
741 | *base_lo = 0; | |
742 | *size = 0; | |
743 | } | |
744 | ||
745 | pr_debug("get 64bit window: %d, base hi: 0x%x, base lo: 0x%x, " | |
746 | "size: 0x%x\n", window, *base_hi, *base_lo, *size); | |
1da177e4 LT |
747 | } |
748 | ||
749 | /* | |
750 | * mv64x60_set_64bit_window() | |
751 | * | |
752 | * Set the base address and size of a 64-bit window on the bridge. | |
753 | */ | |
754 | void __init | |
755 | mv64x60_set_64bit_window(struct mv64x60_handle *bh, u32 window, | |
756 | u32 base_hi, u32 base_lo, u32 size, u32 other_bits) | |
757 | { | |
758 | u32 val, base_lo_reg, size_reg, base_lo_bits, size_bits; | |
759 | u32 (*map_to_field)(u32 val, u32 num_bits); | |
760 | ||
761 | pr_debug("set 64bit window: %d, base hi: 0x%x, base lo: 0x%x, " | |
762 | "size: 0x%x, other: 0x%x\n", | |
763 | window, base_hi, base_lo, size, other_bits); | |
764 | ||
765 | base_lo_reg = bh->ci->window_tab_64bit[window].base_lo_reg; | |
766 | ||
767 | if (base_lo_reg != 0) { | |
768 | size_reg = bh->ci->window_tab_64bit[window].size_reg; | |
769 | base_lo_bits = bh->ci->window_tab_64bit[window].base_lo_bits; | |
770 | size_bits = bh->ci->window_tab_64bit[window].size_bits; | |
771 | map_to_field = bh->ci->window_tab_64bit[window].map_to_field; | |
772 | ||
773 | mv64x60_write(bh, bh->ci->window_tab_64bit[window].base_hi_reg, | |
774 | base_hi); | |
775 | ||
776 | val = map_to_field(base_lo, base_lo_bits) | other_bits; | |
777 | mv64x60_write(bh, base_lo_reg, val); | |
778 | ||
779 | if (size_reg != 0) { | |
780 | val = bh->ci->translate_size(base_lo, size, size_bits); | |
781 | val = map_to_field(val, size_bits); | |
782 | mv64x60_write(bh, size_reg, val); | |
783 | } | |
784 | ||
785 | (void)mv64x60_read(bh, base_lo_reg); /* Flush FIFO */ | |
786 | } | |
1da177e4 LT |
787 | } |
788 | ||
789 | /* | |
790 | * mv64x60_mask() | |
791 | * | |
792 | * Take the high-order 'num_bits' of 'val' & mask off low bits. | |
793 | */ | |
794 | u32 __init | |
795 | mv64x60_mask(u32 val, u32 num_bits) | |
796 | { | |
797 | return val & (0xffffffff << (32 - num_bits)); | |
798 | } | |
799 | ||
800 | /* | |
801 | * mv64x60_shift_left() | |
802 | * | |
803 | * Take the low-order 'num_bits' of 'val', shift left to align at bit 31 (MSB). | |
804 | */ | |
805 | u32 __init | |
806 | mv64x60_shift_left(u32 val, u32 num_bits) | |
807 | { | |
808 | return val << (32 - num_bits); | |
809 | } | |
810 | ||
811 | /* | |
812 | * mv64x60_shift_right() | |
813 | * | |
814 | * Take the high-order 'num_bits' of 'val', shift right to align at bit 0 (LSB). | |
815 | */ | |
816 | u32 __init | |
817 | mv64x60_shift_right(u32 val, u32 num_bits) | |
818 | { | |
819 | return val >> (32 - num_bits); | |
820 | } | |
821 | ||
822 | /* | |
823 | ***************************************************************************** | |
824 | * | |
825 | * Chip Identification Routines | |
826 | * | |
827 | ***************************************************************************** | |
828 | */ | |
829 | /* | |
830 | * mv64x60_get_type() | |
831 | * | |
832 | * Determine the type of bridge chip we have. | |
833 | */ | |
834 | int __init | |
835 | mv64x60_get_type(struct mv64x60_handle *bh) | |
836 | { | |
837 | struct pci_controller hose; | |
838 | u16 val; | |
839 | u8 save_exclude; | |
840 | ||
841 | memset(&hose, 0, sizeof(hose)); | |
842 | setup_indirect_pci_nomap(&hose, bh->v_base + MV64x60_PCI0_CONFIG_ADDR, | |
843 | bh->v_base + MV64x60_PCI0_CONFIG_DATA); | |
844 | ||
845 | save_exclude = mv64x60_pci_exclude_bridge; | |
846 | mv64x60_pci_exclude_bridge = 0; | |
847 | /* Sanity check of bridge's Vendor ID */ | |
848 | early_read_config_word(&hose, 0, PCI_DEVFN(0, 0), PCI_VENDOR_ID, &val); | |
849 | ||
850 | if (val != PCI_VENDOR_ID_MARVELL) { | |
851 | mv64x60_pci_exclude_bridge = save_exclude; | |
852 | return -1; | |
853 | } | |
854 | ||
855 | /* Get the revision of the chip */ | |
856 | early_read_config_word(&hose, 0, PCI_DEVFN(0, 0), PCI_CLASS_REVISION, | |
857 | &val); | |
858 | bh->rev = (u32)(val & 0xff); | |
859 | ||
860 | /* Figure out the type of Marvell bridge it is */ | |
861 | early_read_config_word(&hose, 0, PCI_DEVFN(0, 0), PCI_DEVICE_ID, &val); | |
862 | mv64x60_pci_exclude_bridge = save_exclude; | |
863 | ||
864 | switch (val) { | |
865 | case PCI_DEVICE_ID_MARVELL_GT64260: | |
866 | switch (bh->rev) { | |
867 | case GT64260_REV_A: | |
868 | bh->type = MV64x60_TYPE_GT64260A; | |
869 | break; | |
870 | ||
871 | default: | |
872 | printk(KERN_WARNING "Unsupported GT64260 rev %04x\n", | |
873 | bh->rev); | |
874 | /* Assume its similar to a 'B' rev and fallthru */ | |
875 | case GT64260_REV_B: | |
876 | bh->type = MV64x60_TYPE_GT64260B; | |
877 | break; | |
878 | } | |
879 | break; | |
880 | ||
881 | case PCI_DEVICE_ID_MARVELL_MV64360: | |
882 | /* Marvell won't tell me how to distinguish a 64361 & 64362 */ | |
883 | bh->type = MV64x60_TYPE_MV64360; | |
884 | break; | |
885 | ||
886 | case PCI_DEVICE_ID_MARVELL_MV64460: | |
887 | bh->type = MV64x60_TYPE_MV64460; | |
888 | break; | |
889 | ||
890 | default: | |
891 | printk(KERN_ERR "Unknown Marvell bridge type %04x\n", val); | |
892 | return -1; | |
893 | } | |
894 | ||
895 | /* Hang onto bridge type & rev for PIC code */ | |
896 | mv64x60_bridge_type = bh->type; | |
897 | mv64x60_bridge_rev = bh->rev; | |
898 | ||
899 | return 0; | |
900 | } | |
901 | ||
902 | /* | |
903 | * mv64x60_setup_for_chip() | |
904 | * | |
905 | * Set 'bh' to use the proper set of routine for the bridge chip that we have. | |
906 | */ | |
907 | int __init | |
908 | mv64x60_setup_for_chip(struct mv64x60_handle *bh) | |
909 | { | |
910 | int rc = 0; | |
911 | ||
912 | /* Set up chip-specific info based on the chip/bridge type */ | |
913 | switch(bh->type) { | |
914 | case MV64x60_TYPE_GT64260A: | |
915 | bh->ci = >64260a_ci; | |
916 | break; | |
917 | ||
918 | case MV64x60_TYPE_GT64260B: | |
919 | bh->ci = >64260b_ci; | |
920 | break; | |
921 | ||
922 | case MV64x60_TYPE_MV64360: | |
923 | bh->ci = &mv64360_ci; | |
924 | break; | |
925 | ||
926 | case MV64x60_TYPE_MV64460: | |
927 | bh->ci = &mv64460_ci; | |
928 | break; | |
929 | ||
930 | case MV64x60_TYPE_INVALID: | |
931 | default: | |
932 | if (ppc_md.progress) | |
933 | ppc_md.progress("mv64x60: Unsupported bridge", 0x0); | |
934 | printk(KERN_ERR "mv64x60: Unsupported bridge\n"); | |
935 | rc = -1; | |
936 | } | |
937 | ||
938 | return rc; | |
939 | } | |
940 | ||
941 | /* | |
942 | * mv64x60_get_bridge_vbase() | |
943 | * | |
944 | * Return the virtual address of the bridge's registers. | |
945 | */ | |
a7625d6e | 946 | void __iomem * |
1da177e4 LT |
947 | mv64x60_get_bridge_vbase(void) |
948 | { | |
949 | return mv64x60_bridge_vbase; | |
950 | } | |
951 | ||
952 | /* | |
953 | * mv64x60_get_bridge_type() | |
954 | * | |
955 | * Return the type of bridge on the platform. | |
956 | */ | |
957 | u32 | |
958 | mv64x60_get_bridge_type(void) | |
959 | { | |
960 | return mv64x60_bridge_type; | |
961 | } | |
962 | ||
963 | /* | |
964 | * mv64x60_get_bridge_rev() | |
965 | * | |
966 | * Return the revision of the bridge on the platform. | |
967 | */ | |
968 | u32 | |
969 | mv64x60_get_bridge_rev(void) | |
970 | { | |
971 | return mv64x60_bridge_rev; | |
972 | } | |
973 | ||
974 | /* | |
975 | ***************************************************************************** | |
976 | * | |
977 | * System Memory Window Related Routines | |
978 | * | |
979 | ***************************************************************************** | |
980 | */ | |
981 | /* | |
982 | * mv64x60_get_mem_size() | |
983 | * | |
984 | * Calculate the amount of memory that the memory controller is set up for. | |
985 | * This should only be used by board-specific code if there is no other | |
986 | * way to determine the amount of memory in the system. | |
987 | */ | |
988 | u32 __init | |
989 | mv64x60_get_mem_size(u32 bridge_base, u32 chip_type) | |
990 | { | |
991 | struct mv64x60_handle bh; | |
992 | u32 mem_windows[MV64x60_CPU2MEM_WINDOWS][2]; | |
993 | u32 rc = 0; | |
994 | ||
995 | memset(&bh, 0, sizeof(bh)); | |
996 | ||
997 | bh.type = chip_type; | |
998 | bh.v_base = (void *)bridge_base; | |
999 | ||
1000 | if (!mv64x60_setup_for_chip(&bh)) { | |
1001 | mv64x60_get_mem_windows(&bh, mem_windows); | |
1002 | rc = mv64x60_calc_mem_size(&bh, mem_windows); | |
1003 | } | |
1004 | ||
1005 | return rc; | |
1006 | } | |
1007 | ||
1008 | /* | |
1009 | * mv64x60_get_mem_windows() | |
1010 | * | |
1011 | * Get the values in the memory controller & return in the 'mem_windows' array. | |
1012 | */ | |
1013 | void __init | |
1014 | mv64x60_get_mem_windows(struct mv64x60_handle *bh, | |
1015 | u32 mem_windows[MV64x60_CPU2MEM_WINDOWS][2]) | |
1016 | { | |
1017 | u32 i, win; | |
1018 | ||
1019 | for (win=MV64x60_CPU2MEM_0_WIN,i=0;win<=MV64x60_CPU2MEM_3_WIN;win++,i++) | |
1020 | if (bh->ci->is_enabled_32bit(bh, win)) | |
1021 | mv64x60_get_32bit_window(bh, win, | |
1022 | &mem_windows[i][0], &mem_windows[i][1]); | |
1023 | else { | |
1024 | mem_windows[i][0] = 0; | |
1025 | mem_windows[i][1] = 0; | |
1026 | } | |
1da177e4 LT |
1027 | } |
1028 | ||
1029 | /* | |
1030 | * mv64x60_calc_mem_size() | |
1031 | * | |
1032 | * Using the memory controller register values in 'mem_windows', determine | |
1033 | * how much memory it is set up for. | |
1034 | */ | |
1035 | u32 __init | |
1036 | mv64x60_calc_mem_size(struct mv64x60_handle *bh, | |
1037 | u32 mem_windows[MV64x60_CPU2MEM_WINDOWS][2]) | |
1038 | { | |
1039 | u32 i, total = 0; | |
1040 | ||
1041 | for (i=0; i<MV64x60_CPU2MEM_WINDOWS; i++) | |
1042 | total += mem_windows[i][1]; | |
1043 | ||
1044 | return total; | |
1045 | } | |
1046 | ||
1047 | /* | |
1048 | ***************************************************************************** | |
1049 | * | |
1050 | * CPU->System MEM, PCI Config Routines | |
1051 | * | |
1052 | ***************************************************************************** | |
1053 | */ | |
1054 | /* | |
1055 | * mv64x60_config_cpu2mem_windows() | |
1056 | * | |
1057 | * Configure CPU->Memory windows on the bridge. | |
1058 | */ | |
1059 | static u32 prot_tab[] __initdata = { | |
1060 | MV64x60_CPU_PROT_0_WIN, MV64x60_CPU_PROT_1_WIN, | |
1061 | MV64x60_CPU_PROT_2_WIN, MV64x60_CPU_PROT_3_WIN | |
1062 | }; | |
1063 | ||
1064 | static u32 cpu_snoop_tab[] __initdata = { | |
1065 | MV64x60_CPU_SNOOP_0_WIN, MV64x60_CPU_SNOOP_1_WIN, | |
1066 | MV64x60_CPU_SNOOP_2_WIN, MV64x60_CPU_SNOOP_3_WIN | |
1067 | }; | |
1068 | ||
1069 | void __init | |
1070 | mv64x60_config_cpu2mem_windows(struct mv64x60_handle *bh, | |
1071 | struct mv64x60_setup_info *si, | |
1072 | u32 mem_windows[MV64x60_CPU2MEM_WINDOWS][2]) | |
1073 | { | |
1074 | u32 i, win; | |
1075 | ||
1076 | /* Set CPU protection & snoop windows */ | |
1077 | for (win=MV64x60_CPU2MEM_0_WIN,i=0;win<=MV64x60_CPU2MEM_3_WIN;win++,i++) | |
1078 | if (bh->ci->is_enabled_32bit(bh, win)) { | |
1079 | mv64x60_set_32bit_window(bh, prot_tab[i], | |
1080 | mem_windows[i][0], mem_windows[i][1], | |
1081 | si->cpu_prot_options[i]); | |
1082 | bh->ci->enable_window_32bit(bh, prot_tab[i]); | |
1083 | ||
1084 | if (bh->ci->window_tab_32bit[cpu_snoop_tab[i]]. | |
1085 | base_reg != 0) { | |
1086 | mv64x60_set_32bit_window(bh, cpu_snoop_tab[i], | |
1087 | mem_windows[i][0], mem_windows[i][1], | |
1088 | si->cpu_snoop_options[i]); | |
1089 | bh->ci->enable_window_32bit(bh, | |
1090 | cpu_snoop_tab[i]); | |
1091 | } | |
1092 | ||
1093 | } | |
1da177e4 LT |
1094 | } |
1095 | ||
1096 | /* | |
1097 | * mv64x60_config_cpu2pci_windows() | |
1098 | * | |
1099 | * Configure the CPU->PCI windows for one of the PCI buses. | |
1100 | */ | |
1101 | static u32 win_tab[2][4] __initdata = { | |
1102 | { MV64x60_CPU2PCI0_IO_WIN, MV64x60_CPU2PCI0_MEM_0_WIN, | |
1103 | MV64x60_CPU2PCI0_MEM_1_WIN, MV64x60_CPU2PCI0_MEM_2_WIN }, | |
1104 | { MV64x60_CPU2PCI1_IO_WIN, MV64x60_CPU2PCI1_MEM_0_WIN, | |
1105 | MV64x60_CPU2PCI1_MEM_1_WIN, MV64x60_CPU2PCI1_MEM_2_WIN }, | |
1106 | }; | |
1107 | ||
1108 | static u32 remap_tab[2][4] __initdata = { | |
1109 | { MV64x60_CPU2PCI0_IO_REMAP_WIN, MV64x60_CPU2PCI0_MEM_0_REMAP_WIN, | |
1110 | MV64x60_CPU2PCI0_MEM_1_REMAP_WIN, MV64x60_CPU2PCI0_MEM_2_REMAP_WIN }, | |
1111 | { MV64x60_CPU2PCI1_IO_REMAP_WIN, MV64x60_CPU2PCI1_MEM_0_REMAP_WIN, | |
1112 | MV64x60_CPU2PCI1_MEM_1_REMAP_WIN, MV64x60_CPU2PCI1_MEM_2_REMAP_WIN } | |
1113 | }; | |
1114 | ||
1115 | void __init | |
1116 | mv64x60_config_cpu2pci_windows(struct mv64x60_handle *bh, | |
1117 | struct mv64x60_pci_info *pi, u32 bus) | |
1118 | { | |
1119 | int i; | |
1120 | ||
1121 | if (pi->pci_io.size > 0) { | |
1122 | mv64x60_set_32bit_window(bh, win_tab[bus][0], | |
1123 | pi->pci_io.cpu_base, pi->pci_io.size, pi->pci_io.swap); | |
1124 | mv64x60_set_32bit_window(bh, remap_tab[bus][0], | |
1125 | pi->pci_io.pci_base_lo, 0, 0); | |
1126 | bh->ci->enable_window_32bit(bh, win_tab[bus][0]); | |
d01c08c9 | 1127 | } else /* Actually, the window should already be disabled */ |
1da177e4 LT |
1128 | bh->ci->disable_window_32bit(bh, win_tab[bus][0]); |
1129 | ||
1130 | for (i=0; i<3; i++) | |
1131 | if (pi->pci_mem[i].size > 0) { | |
1132 | mv64x60_set_32bit_window(bh, win_tab[bus][i+1], | |
1133 | pi->pci_mem[i].cpu_base, pi->pci_mem[i].size, | |
1134 | pi->pci_mem[i].swap); | |
1135 | mv64x60_set_64bit_window(bh, remap_tab[bus][i+1], | |
1136 | pi->pci_mem[i].pci_base_hi, | |
1137 | pi->pci_mem[i].pci_base_lo, 0, 0); | |
1138 | bh->ci->enable_window_32bit(bh, win_tab[bus][i+1]); | |
d01c08c9 | 1139 | } else /* Actually, the window should already be disabled */ |
1da177e4 | 1140 | bh->ci->disable_window_32bit(bh, win_tab[bus][i+1]); |
1da177e4 LT |
1141 | } |
1142 | ||
1143 | /* | |
1144 | ***************************************************************************** | |
1145 | * | |
1146 | * PCI->System MEM Config Routines | |
1147 | * | |
1148 | ***************************************************************************** | |
1149 | */ | |
1150 | /* | |
1151 | * mv64x60_config_pci2mem_windows() | |
1152 | * | |
1153 | * Configure the PCI->Memory windows on the bridge. | |
1154 | */ | |
1155 | static u32 pci_acc_tab[2][4] __initdata = { | |
1156 | { MV64x60_PCI02MEM_ACC_CNTL_0_WIN, MV64x60_PCI02MEM_ACC_CNTL_1_WIN, | |
1157 | MV64x60_PCI02MEM_ACC_CNTL_2_WIN, MV64x60_PCI02MEM_ACC_CNTL_3_WIN }, | |
1158 | { MV64x60_PCI12MEM_ACC_CNTL_0_WIN, MV64x60_PCI12MEM_ACC_CNTL_1_WIN, | |
1159 | MV64x60_PCI12MEM_ACC_CNTL_2_WIN, MV64x60_PCI12MEM_ACC_CNTL_3_WIN } | |
1160 | }; | |
1161 | ||
1162 | static u32 pci_snoop_tab[2][4] __initdata = { | |
1163 | { MV64x60_PCI02MEM_SNOOP_0_WIN, MV64x60_PCI02MEM_SNOOP_1_WIN, | |
1164 | MV64x60_PCI02MEM_SNOOP_2_WIN, MV64x60_PCI02MEM_SNOOP_3_WIN }, | |
1165 | { MV64x60_PCI12MEM_SNOOP_0_WIN, MV64x60_PCI12MEM_SNOOP_1_WIN, | |
1166 | MV64x60_PCI12MEM_SNOOP_2_WIN, MV64x60_PCI12MEM_SNOOP_3_WIN } | |
1167 | }; | |
1168 | ||
1169 | static u32 pci_size_tab[2][4] __initdata = { | |
1170 | { MV64x60_PCI0_MEM_0_SIZE, MV64x60_PCI0_MEM_1_SIZE, | |
1171 | MV64x60_PCI0_MEM_2_SIZE, MV64x60_PCI0_MEM_3_SIZE }, | |
1172 | { MV64x60_PCI1_MEM_0_SIZE, MV64x60_PCI1_MEM_1_SIZE, | |
1173 | MV64x60_PCI1_MEM_2_SIZE, MV64x60_PCI1_MEM_3_SIZE } | |
1174 | }; | |
1175 | ||
1176 | void __init | |
1177 | mv64x60_config_pci2mem_windows(struct mv64x60_handle *bh, | |
1178 | struct pci_controller *hose, struct mv64x60_pci_info *pi, | |
1179 | u32 bus, u32 mem_windows[MV64x60_CPU2MEM_WINDOWS][2]) | |
1180 | { | |
1181 | u32 i, win; | |
1182 | ||
1183 | /* | |
1184 | * Set the access control, snoop, BAR size, and window base addresses. | |
1185 | * PCI->MEM windows base addresses will match exactly what the | |
1186 | * CPU->MEM windows are. | |
1187 | */ | |
1188 | for (win=MV64x60_CPU2MEM_0_WIN,i=0;win<=MV64x60_CPU2MEM_3_WIN;win++,i++) | |
1189 | if (bh->ci->is_enabled_32bit(bh, win)) { | |
1190 | mv64x60_set_64bit_window(bh, | |
1191 | pci_acc_tab[bus][i], 0, | |
1192 | mem_windows[i][0], mem_windows[i][1], | |
1193 | pi->acc_cntl_options[i]); | |
1194 | bh->ci->enable_window_64bit(bh, pci_acc_tab[bus][i]); | |
1195 | ||
1196 | if (bh->ci->window_tab_64bit[ | |
1197 | pci_snoop_tab[bus][i]].base_lo_reg != 0) { | |
1198 | ||
1199 | mv64x60_set_64bit_window(bh, | |
1200 | pci_snoop_tab[bus][i], 0, | |
1201 | mem_windows[i][0], mem_windows[i][1], | |
1202 | pi->snoop_options[i]); | |
1203 | bh->ci->enable_window_64bit(bh, | |
1204 | pci_snoop_tab[bus][i]); | |
1205 | } | |
1206 | ||
1207 | bh->ci->set_pci2mem_window(hose, bus, i, | |
1208 | mem_windows[i][0]); | |
1209 | mv64x60_write(bh, pci_size_tab[bus][i], | |
1210 | mv64x60_mask(mem_windows[i][1] - 1, 20)); | |
1211 | ||
1212 | /* Enable the window */ | |
1213 | mv64x60_clr_bits(bh, ((bus == 0) ? | |
1214 | MV64x60_PCI0_BAR_ENABLE : | |
1215 | MV64x60_PCI1_BAR_ENABLE), (1 << i)); | |
1216 | } | |
1da177e4 LT |
1217 | } |
1218 | ||
1219 | /* | |
1220 | ***************************************************************************** | |
1221 | * | |
1222 | * Hose & Resource Alloc/Init Routines | |
1223 | * | |
1224 | ***************************************************************************** | |
1225 | */ | |
1226 | /* | |
1227 | * mv64x60_alloc_hoses() | |
1228 | * | |
1229 | * Allocate the PCI hose structures for the bridge's PCI buses. | |
1230 | */ | |
1231 | void __init | |
1232 | mv64x60_alloc_hose(struct mv64x60_handle *bh, u32 cfg_addr, u32 cfg_data, | |
1233 | struct pci_controller **hose) | |
1234 | { | |
1235 | *hose = pcibios_alloc_controller(); | |
1236 | setup_indirect_pci_nomap(*hose, bh->v_base + cfg_addr, | |
1237 | bh->v_base + cfg_data); | |
1da177e4 LT |
1238 | } |
1239 | ||
1240 | /* | |
1241 | * mv64x60_config_resources() | |
1242 | * | |
1243 | * Calculate the offsets, etc. for the hose structures to reflect all of | |
1244 | * the address remapping that happens as you go from CPU->PCI and PCI->MEM. | |
1245 | */ | |
1246 | void __init | |
1247 | mv64x60_config_resources(struct pci_controller *hose, | |
1248 | struct mv64x60_pci_info *pi, u32 io_base) | |
1249 | { | |
1250 | int i; | |
1251 | /* 2 hoses; 4 resources/hose; string <= 64 bytes */ | |
1252 | static char s[2][4][64]; | |
1253 | ||
1254 | if (pi->pci_io.size != 0) { | |
1255 | sprintf(s[hose->index][0], "PCI hose %d I/O Space", | |
1256 | hose->index); | |
1257 | pci_init_resource(&hose->io_resource, io_base - isa_io_base, | |
1258 | io_base - isa_io_base + pi->pci_io.size - 1, | |
1259 | IORESOURCE_IO, s[hose->index][0]); | |
1260 | hose->io_space.start = pi->pci_io.pci_base_lo; | |
1261 | hose->io_space.end = pi->pci_io.pci_base_lo + pi->pci_io.size-1; | |
1262 | hose->io_base_phys = pi->pci_io.cpu_base; | |
1263 | hose->io_base_virt = (void *)isa_io_base; | |
1264 | } | |
1265 | ||
1266 | for (i=0; i<3; i++) | |
1267 | if (pi->pci_mem[i].size != 0) { | |
1268 | sprintf(s[hose->index][i+1], "PCI hose %d MEM Space %d", | |
1269 | hose->index, i); | |
1270 | pci_init_resource(&hose->mem_resources[i], | |
1271 | pi->pci_mem[i].cpu_base, | |
1272 | pi->pci_mem[i].cpu_base + pi->pci_mem[i].size-1, | |
1273 | IORESOURCE_MEM, s[hose->index][i+1]); | |
1274 | } | |
1275 | ||
1276 | hose->mem_space.end = pi->pci_mem[0].pci_base_lo + | |
1277 | pi->pci_mem[0].size - 1; | |
1278 | hose->pci_mem_offset = pi->pci_mem[0].cpu_base - | |
1279 | pi->pci_mem[0].pci_base_lo; | |
1da177e4 LT |
1280 | } |
1281 | ||
1282 | /* | |
1283 | * mv64x60_config_pci_params() | |
1284 | * | |
1285 | * Configure a hose's PCI config space parameters. | |
1286 | */ | |
1287 | void __init | |
1288 | mv64x60_config_pci_params(struct pci_controller *hose, | |
1289 | struct mv64x60_pci_info *pi) | |
1290 | { | |
1291 | u32 devfn; | |
1292 | u16 u16_val; | |
1293 | u8 save_exclude; | |
1294 | ||
1295 | devfn = PCI_DEVFN(0,0); | |
1296 | ||
1297 | save_exclude = mv64x60_pci_exclude_bridge; | |
1298 | mv64x60_pci_exclude_bridge = 0; | |
1299 | ||
1300 | /* Set class code to indicate host bridge */ | |
1301 | u16_val = PCI_CLASS_BRIDGE_HOST; /* 0x0600 (host bridge) */ | |
1302 | early_write_config_word(hose, 0, devfn, PCI_CLASS_DEVICE, u16_val); | |
1303 | ||
1304 | /* Enable bridge to be PCI master & respond to PCI MEM cycles */ | |
1305 | early_read_config_word(hose, 0, devfn, PCI_COMMAND, &u16_val); | |
1306 | u16_val &= ~(PCI_COMMAND_IO | PCI_COMMAND_INVALIDATE | | |
1307 | PCI_COMMAND_PARITY | PCI_COMMAND_SERR | PCI_COMMAND_FAST_BACK); | |
1308 | u16_val |= pi->pci_cmd_bits | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; | |
1309 | early_write_config_word(hose, 0, devfn, PCI_COMMAND, u16_val); | |
1310 | ||
1311 | /* Set latency timer, cache line size, clear BIST */ | |
7dffb720 | 1312 | u16_val = (pi->latency_timer << 8) | (L1_CACHE_BYTES >> 2); |
1da177e4 LT |
1313 | early_write_config_word(hose, 0, devfn, PCI_CACHE_LINE_SIZE, u16_val); |
1314 | ||
1315 | mv64x60_pci_exclude_bridge = save_exclude; | |
1da177e4 LT |
1316 | } |
1317 | ||
1318 | /* | |
1319 | ***************************************************************************** | |
1320 | * | |
1321 | * PCI Related Routine | |
1322 | * | |
1323 | ***************************************************************************** | |
1324 | */ | |
1325 | /* | |
1326 | * mv64x60_set_bus() | |
1327 | * | |
1328 | * Set the bus number for the hose directly under the bridge. | |
1329 | */ | |
1330 | void __init | |
1331 | mv64x60_set_bus(struct mv64x60_handle *bh, u32 bus, u32 child_bus) | |
1332 | { | |
1333 | struct pci_controller *hose; | |
1334 | u32 pci_mode, p2p_cfg, pci_cfg_offset, val; | |
1335 | u8 save_exclude; | |
1336 | ||
1337 | if (bus == 0) { | |
1338 | pci_mode = bh->pci_mode_a; | |
1339 | p2p_cfg = MV64x60_PCI0_P2P_CONFIG; | |
1340 | pci_cfg_offset = 0x64; | |
1341 | hose = bh->hose_a; | |
d01c08c9 | 1342 | } else { |
1da177e4 LT |
1343 | pci_mode = bh->pci_mode_b; |
1344 | p2p_cfg = MV64x60_PCI1_P2P_CONFIG; | |
1345 | pci_cfg_offset = 0xe4; | |
1346 | hose = bh->hose_b; | |
1347 | } | |
1348 | ||
1349 | child_bus &= 0xff; | |
1350 | val = mv64x60_read(bh, p2p_cfg); | |
1351 | ||
1352 | if (pci_mode == MV64x60_PCIMODE_CONVENTIONAL) { | |
1353 | val &= 0xe0000000; /* Force dev num to 0, turn off P2P bridge */ | |
1354 | val |= (child_bus << 16) | 0xff; | |
1355 | mv64x60_write(bh, p2p_cfg, val); | |
1356 | (void)mv64x60_read(bh, p2p_cfg); /* Flush FIFO */ | |
d01c08c9 | 1357 | } else { /* PCI-X */ |
1da177e4 LT |
1358 | /* |
1359 | * Need to use the current bus/dev number (that's in the | |
1360 | * P2P CONFIG reg) to access the bridge's pci config space. | |
1361 | */ | |
1362 | save_exclude = mv64x60_pci_exclude_bridge; | |
1363 | mv64x60_pci_exclude_bridge = 0; | |
1364 | early_write_config_dword(hose, (val & 0x00ff0000) >> 16, | |
1365 | PCI_DEVFN(((val & 0x1f000000) >> 24), 0), | |
1366 | pci_cfg_offset, child_bus << 8); | |
1367 | mv64x60_pci_exclude_bridge = save_exclude; | |
1368 | } | |
1da177e4 LT |
1369 | } |
1370 | ||
1371 | /* | |
1372 | * mv64x60_pci_exclude_device() | |
1373 | * | |
1374 | * This routine is used to make the bridge not appear when the | |
1375 | * PCI subsystem is accessing PCI devices (in PCI config space). | |
1376 | */ | |
1377 | int | |
1378 | mv64x60_pci_exclude_device(u8 bus, u8 devfn) | |
1379 | { | |
1380 | struct pci_controller *hose; | |
1381 | ||
1382 | hose = pci_bus_to_hose(bus); | |
1383 | ||
1384 | /* Skip slot 0 on both hoses */ | |
1385 | if ((mv64x60_pci_exclude_bridge == 1) && (PCI_SLOT(devfn) == 0) && | |
1386 | (hose->first_busno == bus)) | |
1387 | ||
1388 | return PCIBIOS_DEVICE_NOT_FOUND; | |
1389 | else | |
1390 | return PCIBIOS_SUCCESSFUL; | |
1391 | } /* mv64x60_pci_exclude_device() */ | |
1392 | ||
1393 | /* | |
1394 | ***************************************************************************** | |
1395 | * | |
1396 | * Platform Device Routines | |
1397 | * | |
1398 | ***************************************************************************** | |
1399 | */ | |
1400 | ||
1401 | /* | |
1402 | * mv64x60_pd_fixup() | |
1403 | * | |
1404 | * Need to add the base addr of where the bridge's regs are mapped in the | |
1405 | * physical addr space so drivers can ioremap() them. | |
1406 | */ | |
1407 | void __init | |
1408 | mv64x60_pd_fixup(struct mv64x60_handle *bh, struct platform_device *pd_devs[], | |
1409 | u32 entries) | |
1410 | { | |
1411 | struct resource *r; | |
1412 | u32 i, j; | |
1413 | ||
1414 | for (i=0; i<entries; i++) { | |
1415 | j = 0; | |
1416 | ||
1417 | while ((r = platform_get_resource(pd_devs[i],IORESOURCE_MEM,j)) | |
1418 | != NULL) { | |
1419 | ||
1420 | r->start += bh->p_base; | |
1421 | r->end += bh->p_base; | |
1422 | j++; | |
1423 | } | |
1424 | } | |
1da177e4 LT |
1425 | } |
1426 | ||
1427 | /* | |
1428 | * mv64x60_add_pds() | |
1429 | * | |
1430 | * Add the mv64x60 platform devices to the list of platform devices. | |
1431 | */ | |
1432 | static int __init | |
1433 | mv64x60_add_pds(void) | |
1434 | { | |
1435 | return platform_add_devices(mv64x60_pd_devs, | |
1436 | ARRAY_SIZE(mv64x60_pd_devs)); | |
1437 | } | |
1438 | arch_initcall(mv64x60_add_pds); | |
1439 | ||
1440 | /* | |
1441 | ***************************************************************************** | |
1442 | * | |
1443 | * GT64260-Specific Routines | |
1444 | * | |
1445 | ***************************************************************************** | |
1446 | */ | |
1447 | /* | |
1448 | * gt64260_translate_size() | |
1449 | * | |
1450 | * On the GT64260, the size register is really the "top" address of the window. | |
1451 | */ | |
1452 | static u32 __init | |
1453 | gt64260_translate_size(u32 base, u32 size, u32 num_bits) | |
1454 | { | |
1455 | return base + mv64x60_mask(size - 1, num_bits); | |
1456 | } | |
1457 | ||
1458 | /* | |
1459 | * gt64260_untranslate_size() | |
1460 | * | |
1461 | * Translate the top address of a window into a window size. | |
1462 | */ | |
1463 | static u32 __init | |
1464 | gt64260_untranslate_size(u32 base, u32 size, u32 num_bits) | |
1465 | { | |
1466 | if (size >= base) | |
1467 | size = size - base + (1 << (32 - num_bits)); | |
1468 | else | |
1469 | size = 0; | |
1470 | ||
1471 | return size; | |
1472 | } | |
1473 | ||
1474 | /* | |
1475 | * gt64260_set_pci2mem_window() | |
1476 | * | |
1477 | * The PCI->MEM window registers are actually in PCI config space so need | |
1478 | * to set them by setting the correct config space BARs. | |
1479 | */ | |
1480 | static u32 gt64260_reg_addrs[2][4] __initdata = { | |
1481 | { 0x10, 0x14, 0x18, 0x1c }, { 0x90, 0x94, 0x98, 0x9c } | |
1482 | }; | |
1483 | ||
1484 | static void __init | |
1485 | gt64260_set_pci2mem_window(struct pci_controller *hose, u32 bus, u32 window, | |
1486 | u32 base) | |
1487 | { | |
1488 | u8 save_exclude; | |
1489 | ||
1490 | pr_debug("set pci->mem window: %d, hose: %d, base: 0x%x\n", window, | |
1491 | hose->index, base); | |
1492 | ||
1493 | save_exclude = mv64x60_pci_exclude_bridge; | |
1494 | mv64x60_pci_exclude_bridge = 0; | |
1495 | early_write_config_dword(hose, 0, PCI_DEVFN(0, 0), | |
1496 | gt64260_reg_addrs[bus][window], mv64x60_mask(base, 20) | 0x8); | |
1497 | mv64x60_pci_exclude_bridge = save_exclude; | |
1da177e4 LT |
1498 | } |
1499 | ||
1500 | /* | |
1501 | * gt64260_set_pci2regs_window() | |
1502 | * | |
1503 | * Set where the bridge's registers appear in PCI MEM space. | |
1504 | */ | |
1505 | static u32 gt64260_offset[2] __initdata = {0x20, 0xa0}; | |
1506 | ||
1507 | static void __init | |
1508 | gt64260_set_pci2regs_window(struct mv64x60_handle *bh, | |
1509 | struct pci_controller *hose, u32 bus, u32 base) | |
1510 | { | |
1511 | u8 save_exclude; | |
1512 | ||
1513 | pr_debug("set pci->internal regs hose: %d, base: 0x%x\n", hose->index, | |
1514 | base); | |
1515 | ||
1516 | save_exclude = mv64x60_pci_exclude_bridge; | |
1517 | mv64x60_pci_exclude_bridge = 0; | |
1518 | early_write_config_dword(hose, 0, PCI_DEVFN(0,0), gt64260_offset[bus], | |
1519 | (base << 16)); | |
1520 | mv64x60_pci_exclude_bridge = save_exclude; | |
1da177e4 LT |
1521 | } |
1522 | ||
1523 | /* | |
1524 | * gt64260_is_enabled_32bit() | |
1525 | * | |
1526 | * On a GT64260, a window is enabled iff its top address is >= to its base | |
1527 | * address. | |
1528 | */ | |
1529 | static u32 __init | |
1530 | gt64260_is_enabled_32bit(struct mv64x60_handle *bh, u32 window) | |
1531 | { | |
1532 | u32 rc = 0; | |
1533 | ||
1534 | if ((gt64260_32bit_windows[window].base_reg != 0) && | |
1535 | (gt64260_32bit_windows[window].size_reg != 0) && | |
1536 | ((mv64x60_read(bh, gt64260_32bit_windows[window].size_reg) & | |
1537 | ((1 << gt64260_32bit_windows[window].size_bits) - 1)) >= | |
1538 | (mv64x60_read(bh, gt64260_32bit_windows[window].base_reg) & | |
1539 | ((1 << gt64260_32bit_windows[window].base_bits) - 1)))) | |
1540 | ||
1541 | rc = 1; | |
1542 | ||
1543 | return rc; | |
1544 | } | |
1545 | ||
1546 | /* | |
1547 | * gt64260_enable_window_32bit() | |
1548 | * | |
1549 | * On the GT64260, a window is enabled iff the top address is >= to the base | |
1550 | * address of the window. Since the window has already been configured by | |
1551 | * the time this routine is called, we have nothing to do here. | |
1552 | */ | |
1553 | static void __init | |
1554 | gt64260_enable_window_32bit(struct mv64x60_handle *bh, u32 window) | |
1555 | { | |
1556 | pr_debug("enable 32bit window: %d\n", window); | |
1da177e4 LT |
1557 | } |
1558 | ||
1559 | /* | |
1560 | * gt64260_disable_window_32bit() | |
1561 | * | |
1562 | * On a GT64260, you disable a window by setting its top address to be less | |
1563 | * than its base address. | |
1564 | */ | |
1565 | static void __init | |
1566 | gt64260_disable_window_32bit(struct mv64x60_handle *bh, u32 window) | |
1567 | { | |
1568 | pr_debug("disable 32bit window: %d, base_reg: 0x%x, size_reg: 0x%x\n", | |
1569 | window, gt64260_32bit_windows[window].base_reg, | |
1570 | gt64260_32bit_windows[window].size_reg); | |
1571 | ||
1572 | if ((gt64260_32bit_windows[window].base_reg != 0) && | |
1573 | (gt64260_32bit_windows[window].size_reg != 0)) { | |
1574 | ||
1575 | /* To disable, make bottom reg higher than top reg */ | |
1576 | mv64x60_write(bh, gt64260_32bit_windows[window].base_reg,0xfff); | |
1577 | mv64x60_write(bh, gt64260_32bit_windows[window].size_reg, 0); | |
1578 | } | |
1da177e4 LT |
1579 | } |
1580 | ||
1581 | /* | |
1582 | * gt64260_enable_window_64bit() | |
1583 | * | |
1584 | * On the GT64260, a window is enabled iff the top address is >= to the base | |
1585 | * address of the window. Since the window has already been configured by | |
1586 | * the time this routine is called, we have nothing to do here. | |
1587 | */ | |
1588 | static void __init | |
1589 | gt64260_enable_window_64bit(struct mv64x60_handle *bh, u32 window) | |
1590 | { | |
1591 | pr_debug("enable 64bit window: %d\n", window); | |
1da177e4 LT |
1592 | } |
1593 | ||
1594 | /* | |
1595 | * gt64260_disable_window_64bit() | |
1596 | * | |
1597 | * On a GT64260, you disable a window by setting its top address to be less | |
1598 | * than its base address. | |
1599 | */ | |
1600 | static void __init | |
1601 | gt64260_disable_window_64bit(struct mv64x60_handle *bh, u32 window) | |
1602 | { | |
1603 | pr_debug("disable 64bit window: %d, base_reg: 0x%x, size_reg: 0x%x\n", | |
1604 | window, gt64260_64bit_windows[window].base_lo_reg, | |
1605 | gt64260_64bit_windows[window].size_reg); | |
1606 | ||
1607 | if ((gt64260_64bit_windows[window].base_lo_reg != 0) && | |
1608 | (gt64260_64bit_windows[window].size_reg != 0)) { | |
1609 | ||
1610 | /* To disable, make bottom reg higher than top reg */ | |
1611 | mv64x60_write(bh, gt64260_64bit_windows[window].base_lo_reg, | |
1612 | 0xfff); | |
1613 | mv64x60_write(bh, gt64260_64bit_windows[window].base_hi_reg, 0); | |
1614 | mv64x60_write(bh, gt64260_64bit_windows[window].size_reg, 0); | |
1615 | } | |
1da177e4 LT |
1616 | } |
1617 | ||
1618 | /* | |
1619 | * gt64260_disable_all_windows() | |
1620 | * | |
1621 | * The GT64260 has several windows that aren't represented in the table of | |
1622 | * windows at the top of this file. This routine turns all of them off | |
1623 | * except for the memory controller windows, of course. | |
1624 | */ | |
1625 | static void __init | |
1626 | gt64260_disable_all_windows(struct mv64x60_handle *bh, | |
1627 | struct mv64x60_setup_info *si) | |
1628 | { | |
1629 | u32 i, preserve; | |
1630 | ||
1631 | /* Disable 32bit windows (don't disable cpu->mem windows) */ | |
1632 | for (i=MV64x60_CPU2DEV_0_WIN; i<MV64x60_32BIT_WIN_COUNT; i++) { | |
1633 | if (i < 32) | |
1634 | preserve = si->window_preserve_mask_32_lo & (1 << i); | |
1635 | else | |
1636 | preserve = si->window_preserve_mask_32_hi & (1<<(i-32)); | |
1637 | ||
1638 | if (!preserve) | |
1639 | gt64260_disable_window_32bit(bh, i); | |
1640 | } | |
1641 | ||
1642 | /* Disable 64bit windows */ | |
1643 | for (i=0; i<MV64x60_64BIT_WIN_COUNT; i++) | |
1644 | if (!(si->window_preserve_mask_64 & (1<<i))) | |
1645 | gt64260_disable_window_64bit(bh, i); | |
1646 | ||
1647 | /* Turn off cpu protection windows not in gt64260_32bit_windows[] */ | |
1648 | mv64x60_write(bh, GT64260_CPU_PROT_BASE_4, 0xfff); | |
1649 | mv64x60_write(bh, GT64260_CPU_PROT_SIZE_4, 0); | |
1650 | mv64x60_write(bh, GT64260_CPU_PROT_BASE_5, 0xfff); | |
1651 | mv64x60_write(bh, GT64260_CPU_PROT_SIZE_5, 0); | |
1652 | mv64x60_write(bh, GT64260_CPU_PROT_BASE_6, 0xfff); | |
1653 | mv64x60_write(bh, GT64260_CPU_PROT_SIZE_6, 0); | |
1654 | mv64x60_write(bh, GT64260_CPU_PROT_BASE_7, 0xfff); | |
1655 | mv64x60_write(bh, GT64260_CPU_PROT_SIZE_7, 0); | |
1656 | ||
1657 | /* Turn off PCI->MEM access cntl wins not in gt64260_64bit_windows[] */ | |
1658 | mv64x60_write(bh, MV64x60_PCI0_ACC_CNTL_4_BASE_LO, 0xfff); | |
1659 | mv64x60_write(bh, MV64x60_PCI0_ACC_CNTL_4_BASE_HI, 0); | |
1660 | mv64x60_write(bh, MV64x60_PCI0_ACC_CNTL_4_SIZE, 0); | |
1661 | mv64x60_write(bh, MV64x60_PCI0_ACC_CNTL_5_BASE_LO, 0xfff); | |
1662 | mv64x60_write(bh, MV64x60_PCI0_ACC_CNTL_5_BASE_HI, 0); | |
1663 | mv64x60_write(bh, MV64x60_PCI0_ACC_CNTL_5_SIZE, 0); | |
1664 | mv64x60_write(bh, GT64260_PCI0_ACC_CNTL_6_BASE_LO, 0xfff); | |
1665 | mv64x60_write(bh, GT64260_PCI0_ACC_CNTL_6_BASE_HI, 0); | |
1666 | mv64x60_write(bh, GT64260_PCI0_ACC_CNTL_6_SIZE, 0); | |
1667 | mv64x60_write(bh, GT64260_PCI0_ACC_CNTL_7_BASE_LO, 0xfff); | |
1668 | mv64x60_write(bh, GT64260_PCI0_ACC_CNTL_7_BASE_HI, 0); | |
1669 | mv64x60_write(bh, GT64260_PCI0_ACC_CNTL_7_SIZE, 0); | |
1670 | ||
1671 | mv64x60_write(bh, MV64x60_PCI1_ACC_CNTL_4_BASE_LO, 0xfff); | |
1672 | mv64x60_write(bh, MV64x60_PCI1_ACC_CNTL_4_BASE_HI, 0); | |
1673 | mv64x60_write(bh, MV64x60_PCI1_ACC_CNTL_4_SIZE, 0); | |
1674 | mv64x60_write(bh, MV64x60_PCI1_ACC_CNTL_5_BASE_LO, 0xfff); | |
1675 | mv64x60_write(bh, MV64x60_PCI1_ACC_CNTL_5_BASE_HI, 0); | |
1676 | mv64x60_write(bh, MV64x60_PCI1_ACC_CNTL_5_SIZE, 0); | |
1677 | mv64x60_write(bh, GT64260_PCI1_ACC_CNTL_6_BASE_LO, 0xfff); | |
1678 | mv64x60_write(bh, GT64260_PCI1_ACC_CNTL_6_BASE_HI, 0); | |
1679 | mv64x60_write(bh, GT64260_PCI1_ACC_CNTL_6_SIZE, 0); | |
1680 | mv64x60_write(bh, GT64260_PCI1_ACC_CNTL_7_BASE_LO, 0xfff); | |
1681 | mv64x60_write(bh, GT64260_PCI1_ACC_CNTL_7_BASE_HI, 0); | |
1682 | mv64x60_write(bh, GT64260_PCI1_ACC_CNTL_7_SIZE, 0); | |
1683 | ||
1684 | /* Disable all PCI-><whatever> windows */ | |
1685 | mv64x60_set_bits(bh, MV64x60_PCI0_BAR_ENABLE, 0x07fffdff); | |
1686 | mv64x60_set_bits(bh, MV64x60_PCI1_BAR_ENABLE, 0x07fffdff); | |
1687 | ||
1688 | /* | |
1689 | * Some firmwares enable a bunch of intr sources | |
1690 | * for the PCI INT output pins. | |
1691 | */ | |
1692 | mv64x60_write(bh, GT64260_IC_CPU_INTR_MASK_LO, 0); | |
1693 | mv64x60_write(bh, GT64260_IC_CPU_INTR_MASK_HI, 0); | |
1694 | mv64x60_write(bh, GT64260_IC_PCI0_INTR_MASK_LO, 0); | |
1695 | mv64x60_write(bh, GT64260_IC_PCI0_INTR_MASK_HI, 0); | |
1696 | mv64x60_write(bh, GT64260_IC_PCI1_INTR_MASK_LO, 0); | |
1697 | mv64x60_write(bh, GT64260_IC_PCI1_INTR_MASK_HI, 0); | |
1698 | mv64x60_write(bh, GT64260_IC_CPU_INT_0_MASK, 0); | |
1699 | mv64x60_write(bh, GT64260_IC_CPU_INT_1_MASK, 0); | |
1700 | mv64x60_write(bh, GT64260_IC_CPU_INT_2_MASK, 0); | |
1701 | mv64x60_write(bh, GT64260_IC_CPU_INT_3_MASK, 0); | |
1da177e4 LT |
1702 | } |
1703 | ||
1704 | /* | |
1705 | * gt64260a_chip_specific_init() | |
1706 | * | |
a8de5ce9 | 1707 | * Implement errata workarounds for the GT64260A. |
1da177e4 LT |
1708 | */ |
1709 | static void __init | |
1710 | gt64260a_chip_specific_init(struct mv64x60_handle *bh, | |
1711 | struct mv64x60_setup_info *si) | |
1712 | { | |
1713 | #ifdef CONFIG_SERIAL_MPSC | |
1714 | struct resource *r; | |
1715 | #endif | |
1716 | #if !defined(CONFIG_NOT_COHERENT_CACHE) | |
1717 | u32 val; | |
1718 | u8 save_exclude; | |
1719 | #endif | |
1720 | ||
1721 | if (si->pci_0.enable_bus) | |
1722 | mv64x60_set_bits(bh, MV64x60_PCI0_CMD, | |
1723 | ((1<<4) | (1<<5) | (1<<9) | (1<<13))); | |
1724 | ||
1725 | if (si->pci_1.enable_bus) | |
1726 | mv64x60_set_bits(bh, MV64x60_PCI1_CMD, | |
1727 | ((1<<4) | (1<<5) | (1<<9) | (1<<13))); | |
1728 | ||
1729 | /* | |
1730 | * Dave Wilhardt found that bit 4 in the PCI Command registers must | |
1731 | * be set if you are using cache coherency. | |
1732 | */ | |
1733 | #if !defined(CONFIG_NOT_COHERENT_CACHE) | |
1734 | /* Res #MEM-4 -- cpu read buffer to buffer 1 */ | |
1735 | if ((mv64x60_read(bh, MV64x60_CPU_MODE) & 0xf0) == 0x40) | |
1736 | mv64x60_set_bits(bh, GT64260_SDRAM_CONFIG, (1<<26)); | |
1737 | ||
1738 | save_exclude = mv64x60_pci_exclude_bridge; | |
1739 | mv64x60_pci_exclude_bridge = 0; | |
1740 | if (si->pci_0.enable_bus) { | |
1741 | early_read_config_dword(bh->hose_a, 0, PCI_DEVFN(0,0), | |
1742 | PCI_COMMAND, &val); | |
1743 | val |= PCI_COMMAND_INVALIDATE; | |
1744 | early_write_config_dword(bh->hose_a, 0, PCI_DEVFN(0,0), | |
1745 | PCI_COMMAND, val); | |
1746 | } | |
1747 | ||
1748 | if (si->pci_1.enable_bus) { | |
1749 | early_read_config_dword(bh->hose_b, 0, PCI_DEVFN(0,0), | |
1750 | PCI_COMMAND, &val); | |
1751 | val |= PCI_COMMAND_INVALIDATE; | |
1752 | early_write_config_dword(bh->hose_b, 0, PCI_DEVFN(0,0), | |
1753 | PCI_COMMAND, val); | |
1754 | } | |
1755 | mv64x60_pci_exclude_bridge = save_exclude; | |
1756 | #endif | |
1757 | ||
1758 | /* Disable buffer/descriptor snooping */ | |
1759 | mv64x60_clr_bits(bh, 0xf280, (1<< 6) | (1<<14) | (1<<22) | (1<<30)); | |
1760 | mv64x60_clr_bits(bh, 0xf2c0, (1<< 6) | (1<<14) | (1<<22) | (1<<30)); | |
1761 | ||
1762 | #ifdef CONFIG_SERIAL_MPSC | |
1763 | mv64x60_mpsc0_pdata.mirror_regs = 1; | |
1764 | mv64x60_mpsc0_pdata.cache_mgmt = 1; | |
1765 | mv64x60_mpsc1_pdata.mirror_regs = 1; | |
1766 | mv64x60_mpsc1_pdata.cache_mgmt = 1; | |
1767 | ||
1768 | if ((r = platform_get_resource(&mpsc1_device, IORESOURCE_IRQ, 0)) | |
d01c08c9 | 1769 | != NULL) { |
1da177e4 LT |
1770 | r->start = MV64x60_IRQ_SDMA_0; |
1771 | r->end = MV64x60_IRQ_SDMA_0; | |
1772 | } | |
1773 | #endif | |
1da177e4 LT |
1774 | } |
1775 | ||
1776 | /* | |
1777 | * gt64260b_chip_specific_init() | |
1778 | * | |
a8de5ce9 | 1779 | * Implement errata workarounds for the GT64260B. |
1da177e4 LT |
1780 | */ |
1781 | static void __init | |
1782 | gt64260b_chip_specific_init(struct mv64x60_handle *bh, | |
1783 | struct mv64x60_setup_info *si) | |
1784 | { | |
1785 | #ifdef CONFIG_SERIAL_MPSC | |
1786 | struct resource *r; | |
1787 | #endif | |
1788 | #if !defined(CONFIG_NOT_COHERENT_CACHE) | |
1789 | u32 val; | |
1790 | u8 save_exclude; | |
1791 | #endif | |
1792 | ||
1793 | if (si->pci_0.enable_bus) | |
1794 | mv64x60_set_bits(bh, MV64x60_PCI0_CMD, | |
1795 | ((1<<4) | (1<<5) | (1<<9) | (1<<13))); | |
1796 | ||
1797 | if (si->pci_1.enable_bus) | |
1798 | mv64x60_set_bits(bh, MV64x60_PCI1_CMD, | |
1799 | ((1<<4) | (1<<5) | (1<<9) | (1<<13))); | |
1800 | ||
1801 | /* | |
1802 | * Dave Wilhardt found that bit 4 in the PCI Command registers must | |
1803 | * be set if you are using cache coherency. | |
1804 | */ | |
1805 | #if !defined(CONFIG_NOT_COHERENT_CACHE) | |
1806 | mv64x60_set_bits(bh, GT64260_CPU_WB_PRIORITY_BUFFER_DEPTH, 0xf); | |
1807 | ||
1808 | /* Res #MEM-4 -- cpu read buffer to buffer 1 */ | |
1809 | if ((mv64x60_read(bh, MV64x60_CPU_MODE) & 0xf0) == 0x40) | |
1810 | mv64x60_set_bits(bh, GT64260_SDRAM_CONFIG, (1<<26)); | |
1811 | ||
1812 | save_exclude = mv64x60_pci_exclude_bridge; | |
1813 | mv64x60_pci_exclude_bridge = 0; | |
1814 | if (si->pci_0.enable_bus) { | |
1815 | early_read_config_dword(bh->hose_a, 0, PCI_DEVFN(0,0), | |
1816 | PCI_COMMAND, &val); | |
1817 | val |= PCI_COMMAND_INVALIDATE; | |
1818 | early_write_config_dword(bh->hose_a, 0, PCI_DEVFN(0,0), | |
1819 | PCI_COMMAND, val); | |
1820 | } | |
1821 | ||
1822 | if (si->pci_1.enable_bus) { | |
1823 | early_read_config_dword(bh->hose_b, 0, PCI_DEVFN(0,0), | |
1824 | PCI_COMMAND, &val); | |
1825 | val |= PCI_COMMAND_INVALIDATE; | |
1826 | early_write_config_dword(bh->hose_b, 0, PCI_DEVFN(0,0), | |
1827 | PCI_COMMAND, val); | |
1828 | } | |
1829 | mv64x60_pci_exclude_bridge = save_exclude; | |
1830 | #endif | |
1831 | ||
1832 | /* Disable buffer/descriptor snooping */ | |
1833 | mv64x60_clr_bits(bh, 0xf280, (1<< 6) | (1<<14) | (1<<22) | (1<<30)); | |
1834 | mv64x60_clr_bits(bh, 0xf2c0, (1<< 6) | (1<<14) | (1<<22) | (1<<30)); | |
1835 | ||
1836 | #ifdef CONFIG_SERIAL_MPSC | |
1837 | /* | |
1838 | * The 64260B is not supposed to have the bug where the MPSC & ENET | |
1839 | * can't access cache coherent regions. However, testing has shown | |
1840 | * that the MPSC, at least, still has this bug. | |
1841 | */ | |
1842 | mv64x60_mpsc0_pdata.cache_mgmt = 1; | |
1843 | mv64x60_mpsc1_pdata.cache_mgmt = 1; | |
1844 | ||
1845 | if ((r = platform_get_resource(&mpsc1_device, IORESOURCE_IRQ, 0)) | |
d01c08c9 | 1846 | != NULL) { |
1da177e4 LT |
1847 | r->start = MV64x60_IRQ_SDMA_0; |
1848 | r->end = MV64x60_IRQ_SDMA_0; | |
1849 | } | |
1850 | #endif | |
1da177e4 LT |
1851 | } |
1852 | ||
1853 | /* | |
1854 | ***************************************************************************** | |
1855 | * | |
1856 | * MV64360-Specific Routines | |
1857 | * | |
1858 | ***************************************************************************** | |
1859 | */ | |
1860 | /* | |
1861 | * mv64360_translate_size() | |
1862 | * | |
1863 | * On the MV64360, the size register is set similar to the size you get | |
1864 | * from a pci config space BAR register. That is, programmed from LSB to MSB | |
1865 | * as a sequence of 1's followed by a sequence of 0's. IOW, "size -1" with the | |
1866 | * assumption that the size is a power of 2. | |
1867 | */ | |
1868 | static u32 __init | |
1869 | mv64360_translate_size(u32 base_addr, u32 size, u32 num_bits) | |
1870 | { | |
1871 | return mv64x60_mask(size - 1, num_bits); | |
1872 | } | |
1873 | ||
1874 | /* | |
1875 | * mv64360_untranslate_size() | |
1876 | * | |
1877 | * Translate the size register value of a window into a window size. | |
1878 | */ | |
1879 | static u32 __init | |
1880 | mv64360_untranslate_size(u32 base_addr, u32 size, u32 num_bits) | |
1881 | { | |
1882 | if (size > 0) { | |
1883 | size >>= (32 - num_bits); | |
1884 | size++; | |
1885 | size <<= (32 - num_bits); | |
1886 | } | |
1887 | ||
1888 | return size; | |
1889 | } | |
1890 | ||
1891 | /* | |
1892 | * mv64360_set_pci2mem_window() | |
1893 | * | |
1894 | * The PCI->MEM window registers are actually in PCI config space so need | |
1895 | * to set them by setting the correct config space BARs. | |
1896 | */ | |
1897 | struct { | |
1898 | u32 fcn; | |
1899 | u32 base_hi_bar; | |
1900 | u32 base_lo_bar; | |
1901 | } static mv64360_reg_addrs[2][4] __initdata = { | |
1902 | {{ 0, 0x14, 0x10 }, { 0, 0x1c, 0x18 }, | |
1903 | { 1, 0x14, 0x10 }, { 1, 0x1c, 0x18 }}, | |
1904 | {{ 0, 0x94, 0x90 }, { 0, 0x9c, 0x98 }, | |
1905 | { 1, 0x94, 0x90 }, { 1, 0x9c, 0x98 }} | |
1906 | }; | |
1907 | ||
1908 | static void __init | |
1909 | mv64360_set_pci2mem_window(struct pci_controller *hose, u32 bus, u32 window, | |
1910 | u32 base) | |
1911 | { | |
1912 | u8 save_exclude; | |
1913 | ||
1914 | pr_debug("set pci->mem window: %d, hose: %d, base: 0x%x\n", window, | |
1915 | hose->index, base); | |
1916 | ||
1917 | save_exclude = mv64x60_pci_exclude_bridge; | |
1918 | mv64x60_pci_exclude_bridge = 0; | |
1919 | early_write_config_dword(hose, 0, | |
1920 | PCI_DEVFN(0, mv64360_reg_addrs[bus][window].fcn), | |
1921 | mv64360_reg_addrs[bus][window].base_hi_bar, 0); | |
1922 | early_write_config_dword(hose, 0, | |
1923 | PCI_DEVFN(0, mv64360_reg_addrs[bus][window].fcn), | |
1924 | mv64360_reg_addrs[bus][window].base_lo_bar, | |
1925 | mv64x60_mask(base,20) | 0xc); | |
1926 | mv64x60_pci_exclude_bridge = save_exclude; | |
1da177e4 LT |
1927 | } |
1928 | ||
1929 | /* | |
1930 | * mv64360_set_pci2regs_window() | |
1931 | * | |
1932 | * Set where the bridge's registers appear in PCI MEM space. | |
1933 | */ | |
1934 | static u32 mv64360_offset[2][2] __initdata = {{0x20, 0x24}, {0xa0, 0xa4}}; | |
1935 | ||
1936 | static void __init | |
1937 | mv64360_set_pci2regs_window(struct mv64x60_handle *bh, | |
1938 | struct pci_controller *hose, u32 bus, u32 base) | |
1939 | { | |
1940 | u8 save_exclude; | |
1941 | ||
1942 | pr_debug("set pci->internal regs hose: %d, base: 0x%x\n", hose->index, | |
1943 | base); | |
1944 | ||
1945 | save_exclude = mv64x60_pci_exclude_bridge; | |
1946 | mv64x60_pci_exclude_bridge = 0; | |
1947 | early_write_config_dword(hose, 0, PCI_DEVFN(0,0), | |
1948 | mv64360_offset[bus][0], (base << 16)); | |
1949 | early_write_config_dword(hose, 0, PCI_DEVFN(0,0), | |
1950 | mv64360_offset[bus][1], 0); | |
1951 | mv64x60_pci_exclude_bridge = save_exclude; | |
1da177e4 LT |
1952 | } |
1953 | ||
1954 | /* | |
1955 | * mv64360_is_enabled_32bit() | |
1956 | * | |
1957 | * On a MV64360, a window is enabled by either clearing a bit in the | |
1958 | * CPU BAR Enable reg or setting a bit in the window's base reg. | |
1959 | * Note that this doesn't work for windows on the PCI slave side but we don't | |
1960 | * check those so its okay. | |
1961 | */ | |
1962 | static u32 __init | |
1963 | mv64360_is_enabled_32bit(struct mv64x60_handle *bh, u32 window) | |
1964 | { | |
1965 | u32 extra, rc = 0; | |
1966 | ||
1967 | if (((mv64360_32bit_windows[window].base_reg != 0) && | |
1968 | (mv64360_32bit_windows[window].size_reg != 0)) || | |
1969 | (window == MV64x60_CPU2SRAM_WIN)) { | |
1970 | ||
1971 | extra = mv64360_32bit_windows[window].extra; | |
1972 | ||
1973 | switch (extra & MV64x60_EXTRA_MASK) { | |
1974 | case MV64x60_EXTRA_CPUWIN_ENAB: | |
1975 | rc = (mv64x60_read(bh, MV64360_CPU_BAR_ENABLE) & | |
1976 | (1 << (extra & 0x1f))) == 0; | |
1977 | break; | |
1978 | ||
1979 | case MV64x60_EXTRA_CPUPROT_ENAB: | |
1980 | rc = (mv64x60_read(bh, | |
1981 | mv64360_32bit_windows[window].base_reg) & | |
1982 | (1 << (extra & 0x1f))) != 0; | |
1983 | break; | |
1984 | ||
1985 | case MV64x60_EXTRA_ENET_ENAB: | |
1986 | rc = (mv64x60_read(bh, MV64360_ENET2MEM_BAR_ENABLE) & | |
1987 | (1 << (extra & 0x7))) == 0; | |
1988 | break; | |
1989 | ||
1990 | case MV64x60_EXTRA_MPSC_ENAB: | |
1991 | rc = (mv64x60_read(bh, MV64360_MPSC2MEM_BAR_ENABLE) & | |
1992 | (1 << (extra & 0x3))) == 0; | |
1993 | break; | |
1994 | ||
1995 | case MV64x60_EXTRA_IDMA_ENAB: | |
1996 | rc = (mv64x60_read(bh, MV64360_IDMA2MEM_BAR_ENABLE) & | |
1997 | (1 << (extra & 0x7))) == 0; | |
1998 | break; | |
1999 | ||
2000 | default: | |
2001 | printk(KERN_ERR "mv64360_is_enabled: %s\n", | |
2002 | "32bit table corrupted"); | |
2003 | } | |
2004 | } | |
2005 | ||
2006 | return rc; | |
2007 | } | |
2008 | ||
2009 | /* | |
2010 | * mv64360_enable_window_32bit() | |
2011 | * | |
2012 | * On a MV64360, a window is enabled by either clearing a bit in the | |
2013 | * CPU BAR Enable reg or setting a bit in the window's base reg. | |
2014 | */ | |
2015 | static void __init | |
2016 | mv64360_enable_window_32bit(struct mv64x60_handle *bh, u32 window) | |
2017 | { | |
2018 | u32 extra; | |
2019 | ||
2020 | pr_debug("enable 32bit window: %d\n", window); | |
2021 | ||
2022 | if (((mv64360_32bit_windows[window].base_reg != 0) && | |
2023 | (mv64360_32bit_windows[window].size_reg != 0)) || | |
2024 | (window == MV64x60_CPU2SRAM_WIN)) { | |
2025 | ||
2026 | extra = mv64360_32bit_windows[window].extra; | |
2027 | ||
2028 | switch (extra & MV64x60_EXTRA_MASK) { | |
2029 | case MV64x60_EXTRA_CPUWIN_ENAB: | |
2030 | mv64x60_clr_bits(bh, MV64360_CPU_BAR_ENABLE, | |
2031 | (1 << (extra & 0x1f))); | |
2032 | break; | |
2033 | ||
2034 | case MV64x60_EXTRA_CPUPROT_ENAB: | |
2035 | mv64x60_set_bits(bh, | |
2036 | mv64360_32bit_windows[window].base_reg, | |
2037 | (1 << (extra & 0x1f))); | |
2038 | break; | |
2039 | ||
2040 | case MV64x60_EXTRA_ENET_ENAB: | |
2041 | mv64x60_clr_bits(bh, MV64360_ENET2MEM_BAR_ENABLE, | |
2042 | (1 << (extra & 0x7))); | |
2043 | break; | |
2044 | ||
2045 | case MV64x60_EXTRA_MPSC_ENAB: | |
2046 | mv64x60_clr_bits(bh, MV64360_MPSC2MEM_BAR_ENABLE, | |
2047 | (1 << (extra & 0x3))); | |
2048 | break; | |
2049 | ||
2050 | case MV64x60_EXTRA_IDMA_ENAB: | |
2051 | mv64x60_clr_bits(bh, MV64360_IDMA2MEM_BAR_ENABLE, | |
2052 | (1 << (extra & 0x7))); | |
2053 | break; | |
2054 | ||
2055 | default: | |
2056 | printk(KERN_ERR "mv64360_enable: %s\n", | |
2057 | "32bit table corrupted"); | |
2058 | } | |
2059 | } | |
1da177e4 LT |
2060 | } |
2061 | ||
2062 | /* | |
2063 | * mv64360_disable_window_32bit() | |
2064 | * | |
2065 | * On a MV64360, a window is disabled by either setting a bit in the | |
2066 | * CPU BAR Enable reg or clearing a bit in the window's base reg. | |
2067 | */ | |
2068 | static void __init | |
2069 | mv64360_disable_window_32bit(struct mv64x60_handle *bh, u32 window) | |
2070 | { | |
2071 | u32 extra; | |
2072 | ||
2073 | pr_debug("disable 32bit window: %d, base_reg: 0x%x, size_reg: 0x%x\n", | |
2074 | window, mv64360_32bit_windows[window].base_reg, | |
2075 | mv64360_32bit_windows[window].size_reg); | |
2076 | ||
2077 | if (((mv64360_32bit_windows[window].base_reg != 0) && | |
2078 | (mv64360_32bit_windows[window].size_reg != 0)) || | |
2079 | (window == MV64x60_CPU2SRAM_WIN)) { | |
2080 | ||
2081 | extra = mv64360_32bit_windows[window].extra; | |
2082 | ||
2083 | switch (extra & MV64x60_EXTRA_MASK) { | |
2084 | case MV64x60_EXTRA_CPUWIN_ENAB: | |
2085 | mv64x60_set_bits(bh, MV64360_CPU_BAR_ENABLE, | |
2086 | (1 << (extra & 0x1f))); | |
2087 | break; | |
2088 | ||
2089 | case MV64x60_EXTRA_CPUPROT_ENAB: | |
2090 | mv64x60_clr_bits(bh, | |
2091 | mv64360_32bit_windows[window].base_reg, | |
2092 | (1 << (extra & 0x1f))); | |
2093 | break; | |
2094 | ||
2095 | case MV64x60_EXTRA_ENET_ENAB: | |
2096 | mv64x60_set_bits(bh, MV64360_ENET2MEM_BAR_ENABLE, | |
2097 | (1 << (extra & 0x7))); | |
2098 | break; | |
2099 | ||
2100 | case MV64x60_EXTRA_MPSC_ENAB: | |
2101 | mv64x60_set_bits(bh, MV64360_MPSC2MEM_BAR_ENABLE, | |
2102 | (1 << (extra & 0x3))); | |
2103 | break; | |
2104 | ||
2105 | case MV64x60_EXTRA_IDMA_ENAB: | |
2106 | mv64x60_set_bits(bh, MV64360_IDMA2MEM_BAR_ENABLE, | |
2107 | (1 << (extra & 0x7))); | |
2108 | break; | |
2109 | ||
2110 | default: | |
2111 | printk(KERN_ERR "mv64360_disable: %s\n", | |
2112 | "32bit table corrupted"); | |
2113 | } | |
2114 | } | |
1da177e4 LT |
2115 | } |
2116 | ||
2117 | /* | |
2118 | * mv64360_enable_window_64bit() | |
2119 | * | |
2120 | * On the MV64360, a 64-bit window is enabled by setting a bit in the window's | |
2121 | * base reg. | |
2122 | */ | |
2123 | static void __init | |
2124 | mv64360_enable_window_64bit(struct mv64x60_handle *bh, u32 window) | |
2125 | { | |
2126 | pr_debug("enable 64bit window: %d\n", window); | |
2127 | ||
2128 | if ((mv64360_64bit_windows[window].base_lo_reg!= 0) && | |
2129 | (mv64360_64bit_windows[window].size_reg != 0)) { | |
2130 | ||
2131 | if ((mv64360_64bit_windows[window].extra & MV64x60_EXTRA_MASK) | |
d01c08c9 | 2132 | == MV64x60_EXTRA_PCIACC_ENAB) |
1da177e4 LT |
2133 | mv64x60_set_bits(bh, |
2134 | mv64360_64bit_windows[window].base_lo_reg, | |
2135 | (1 << (mv64360_64bit_windows[window].extra & | |
2136 | 0x1f))); | |
2137 | else | |
2138 | printk(KERN_ERR "mv64360_enable: %s\n", | |
2139 | "64bit table corrupted"); | |
2140 | } | |
1da177e4 LT |
2141 | } |
2142 | ||
2143 | /* | |
2144 | * mv64360_disable_window_64bit() | |
2145 | * | |
2146 | * On a MV64360, a 64-bit window is disabled by clearing a bit in the window's | |
2147 | * base reg. | |
2148 | */ | |
2149 | static void __init | |
2150 | mv64360_disable_window_64bit(struct mv64x60_handle *bh, u32 window) | |
2151 | { | |
2152 | pr_debug("disable 64bit window: %d, base_reg: 0x%x, size_reg: 0x%x\n", | |
2153 | window, mv64360_64bit_windows[window].base_lo_reg, | |
2154 | mv64360_64bit_windows[window].size_reg); | |
2155 | ||
2156 | if ((mv64360_64bit_windows[window].base_lo_reg != 0) && | |
d01c08c9 | 2157 | (mv64360_64bit_windows[window].size_reg != 0)) { |
1da177e4 | 2158 | if ((mv64360_64bit_windows[window].extra & MV64x60_EXTRA_MASK) |
d01c08c9 | 2159 | == MV64x60_EXTRA_PCIACC_ENAB) |
1da177e4 LT |
2160 | mv64x60_clr_bits(bh, |
2161 | mv64360_64bit_windows[window].base_lo_reg, | |
2162 | (1 << (mv64360_64bit_windows[window].extra & | |
2163 | 0x1f))); | |
2164 | else | |
2165 | printk(KERN_ERR "mv64360_disable: %s\n", | |
2166 | "64bit table corrupted"); | |
2167 | } | |
1da177e4 LT |
2168 | } |
2169 | ||
2170 | /* | |
2171 | * mv64360_disable_all_windows() | |
2172 | * | |
2173 | * The MV64360 has a few windows that aren't represented in the table of | |
2174 | * windows at the top of this file. This routine turns all of them off | |
2175 | * except for the memory controller windows, of course. | |
2176 | */ | |
2177 | static void __init | |
2178 | mv64360_disable_all_windows(struct mv64x60_handle *bh, | |
2179 | struct mv64x60_setup_info *si) | |
2180 | { | |
2181 | u32 preserve, i; | |
2182 | ||
2183 | /* Disable 32bit windows (don't disable cpu->mem windows) */ | |
2184 | for (i=MV64x60_CPU2DEV_0_WIN; i<MV64x60_32BIT_WIN_COUNT; i++) { | |
2185 | if (i < 32) | |
2186 | preserve = si->window_preserve_mask_32_lo & (1 << i); | |
2187 | else | |
2188 | preserve = si->window_preserve_mask_32_hi & (1<<(i-32)); | |
2189 | ||
2190 | if (!preserve) | |
2191 | mv64360_disable_window_32bit(bh, i); | |
2192 | } | |
2193 | ||
2194 | /* Disable 64bit windows */ | |
2195 | for (i=0; i<MV64x60_64BIT_WIN_COUNT; i++) | |
2196 | if (!(si->window_preserve_mask_64 & (1<<i))) | |
2197 | mv64360_disable_window_64bit(bh, i); | |
2198 | ||
2199 | /* Turn off PCI->MEM access cntl wins not in mv64360_64bit_windows[] */ | |
2200 | mv64x60_clr_bits(bh, MV64x60_PCI0_ACC_CNTL_4_BASE_LO, 0); | |
2201 | mv64x60_clr_bits(bh, MV64x60_PCI0_ACC_CNTL_5_BASE_LO, 0); | |
2202 | mv64x60_clr_bits(bh, MV64x60_PCI1_ACC_CNTL_4_BASE_LO, 0); | |
2203 | mv64x60_clr_bits(bh, MV64x60_PCI1_ACC_CNTL_5_BASE_LO, 0); | |
2204 | ||
2205 | /* Disable all PCI-><whatever> windows */ | |
2206 | mv64x60_set_bits(bh, MV64x60_PCI0_BAR_ENABLE, 0x0000f9ff); | |
2207 | mv64x60_set_bits(bh, MV64x60_PCI1_BAR_ENABLE, 0x0000f9ff); | |
1da177e4 LT |
2208 | } |
2209 | ||
2210 | /* | |
2211 | * mv64360_config_io2mem_windows() | |
2212 | * | |
2213 | * ENET, MPSC, and IDMA ctlrs on the MV64[34]60 have separate windows that | |
2214 | * must be set up so that the respective ctlr can access system memory. | |
2215 | */ | |
2216 | static u32 enet_tab[MV64x60_CPU2MEM_WINDOWS] __initdata = { | |
2217 | MV64x60_ENET2MEM_0_WIN, MV64x60_ENET2MEM_1_WIN, | |
2218 | MV64x60_ENET2MEM_2_WIN, MV64x60_ENET2MEM_3_WIN, | |
2219 | }; | |
2220 | ||
2221 | static u32 mpsc_tab[MV64x60_CPU2MEM_WINDOWS] __initdata = { | |
2222 | MV64x60_MPSC2MEM_0_WIN, MV64x60_MPSC2MEM_1_WIN, | |
2223 | MV64x60_MPSC2MEM_2_WIN, MV64x60_MPSC2MEM_3_WIN, | |
2224 | }; | |
2225 | ||
2226 | static u32 idma_tab[MV64x60_CPU2MEM_WINDOWS] __initdata = { | |
2227 | MV64x60_IDMA2MEM_0_WIN, MV64x60_IDMA2MEM_1_WIN, | |
2228 | MV64x60_IDMA2MEM_2_WIN, MV64x60_IDMA2MEM_3_WIN, | |
2229 | }; | |
2230 | ||
2231 | static u32 dram_selects[MV64x60_CPU2MEM_WINDOWS] __initdata = | |
2232 | { 0xe, 0xd, 0xb, 0x7 }; | |
2233 | ||
2234 | static void __init | |
2235 | mv64360_config_io2mem_windows(struct mv64x60_handle *bh, | |
2236 | struct mv64x60_setup_info *si, | |
2237 | u32 mem_windows[MV64x60_CPU2MEM_WINDOWS][2]) | |
2238 | { | |
2239 | u32 i, win; | |
2240 | ||
2241 | pr_debug("config_io2regs_windows: enet, mpsc, idma -> bridge regs\n"); | |
2242 | ||
2243 | mv64x60_write(bh, MV64360_ENET2MEM_ACC_PROT_0, 0); | |
2244 | mv64x60_write(bh, MV64360_ENET2MEM_ACC_PROT_1, 0); | |
2245 | mv64x60_write(bh, MV64360_ENET2MEM_ACC_PROT_2, 0); | |
2246 | ||
2247 | mv64x60_write(bh, MV64360_MPSC2MEM_ACC_PROT_0, 0); | |
2248 | mv64x60_write(bh, MV64360_MPSC2MEM_ACC_PROT_1, 0); | |
2249 | ||
2250 | mv64x60_write(bh, MV64360_IDMA2MEM_ACC_PROT_0, 0); | |
2251 | mv64x60_write(bh, MV64360_IDMA2MEM_ACC_PROT_1, 0); | |
2252 | mv64x60_write(bh, MV64360_IDMA2MEM_ACC_PROT_2, 0); | |
2253 | mv64x60_write(bh, MV64360_IDMA2MEM_ACC_PROT_3, 0); | |
2254 | ||
2255 | /* Assume that mem ctlr has no more windows than embedded I/O ctlr */ | |
2256 | for (win=MV64x60_CPU2MEM_0_WIN,i=0;win<=MV64x60_CPU2MEM_3_WIN;win++,i++) | |
2257 | if (bh->ci->is_enabled_32bit(bh, win)) { | |
2258 | mv64x60_set_32bit_window(bh, enet_tab[i], | |
2259 | mem_windows[i][0], mem_windows[i][1], | |
2260 | (dram_selects[i] << 8) | | |
2261 | (si->enet_options[i] & 0x3000)); | |
2262 | bh->ci->enable_window_32bit(bh, enet_tab[i]); | |
2263 | ||
2264 | /* Give enet r/w access to memory region */ | |
2265 | mv64x60_set_bits(bh, MV64360_ENET2MEM_ACC_PROT_0, | |
2266 | (0x3 << (i << 1))); | |
2267 | mv64x60_set_bits(bh, MV64360_ENET2MEM_ACC_PROT_1, | |
2268 | (0x3 << (i << 1))); | |
2269 | mv64x60_set_bits(bh, MV64360_ENET2MEM_ACC_PROT_2, | |
2270 | (0x3 << (i << 1))); | |
2271 | ||
2272 | mv64x60_set_32bit_window(bh, mpsc_tab[i], | |
2273 | mem_windows[i][0], mem_windows[i][1], | |
2274 | (dram_selects[i] << 8) | | |
2275 | (si->mpsc_options[i] & 0x3000)); | |
2276 | bh->ci->enable_window_32bit(bh, mpsc_tab[i]); | |
2277 | ||
2278 | /* Give mpsc r/w access to memory region */ | |
2279 | mv64x60_set_bits(bh, MV64360_MPSC2MEM_ACC_PROT_0, | |
2280 | (0x3 << (i << 1))); | |
2281 | mv64x60_set_bits(bh, MV64360_MPSC2MEM_ACC_PROT_1, | |
2282 | (0x3 << (i << 1))); | |
2283 | ||
2284 | mv64x60_set_32bit_window(bh, idma_tab[i], | |
2285 | mem_windows[i][0], mem_windows[i][1], | |
2286 | (dram_selects[i] << 8) | | |
2287 | (si->idma_options[i] & 0x3000)); | |
2288 | bh->ci->enable_window_32bit(bh, idma_tab[i]); | |
2289 | ||
2290 | /* Give idma r/w access to memory region */ | |
2291 | mv64x60_set_bits(bh, MV64360_IDMA2MEM_ACC_PROT_0, | |
2292 | (0x3 << (i << 1))); | |
2293 | mv64x60_set_bits(bh, MV64360_IDMA2MEM_ACC_PROT_1, | |
2294 | (0x3 << (i << 1))); | |
2295 | mv64x60_set_bits(bh, MV64360_IDMA2MEM_ACC_PROT_2, | |
2296 | (0x3 << (i << 1))); | |
2297 | mv64x60_set_bits(bh, MV64360_IDMA2MEM_ACC_PROT_3, | |
2298 | (0x3 << (i << 1))); | |
2299 | } | |
1da177e4 LT |
2300 | } |
2301 | ||
2302 | /* | |
2303 | * mv64360_set_mpsc2regs_window() | |
2304 | * | |
2305 | * MPSC has a window to the bridge's internal registers. Call this routine | |
2306 | * to change that window so it doesn't conflict with the windows mapping the | |
2307 | * mpsc to system memory. | |
2308 | */ | |
2309 | static void __init | |
2310 | mv64360_set_mpsc2regs_window(struct mv64x60_handle *bh, u32 base) | |
2311 | { | |
2312 | pr_debug("set mpsc->internal regs, base: 0x%x\n", base); | |
1da177e4 | 2313 | mv64x60_write(bh, MV64360_MPSC2REGS_BASE, base & 0xffff0000); |
1da177e4 LT |
2314 | } |
2315 | ||
2316 | /* | |
2317 | * mv64360_chip_specific_init() | |
2318 | * | |
a8de5ce9 | 2319 | * Implement errata workarounds for the MV64360. |
1da177e4 LT |
2320 | */ |
2321 | static void __init | |
2322 | mv64360_chip_specific_init(struct mv64x60_handle *bh, | |
2323 | struct mv64x60_setup_info *si) | |
2324 | { | |
d01c08c9 MG |
2325 | #if !defined(CONFIG_NOT_COHERENT_CACHE) |
2326 | mv64x60_set_bits(bh, MV64360_D_UNIT_CONTROL_HIGH, (1<<24)); | |
2327 | #endif | |
1da177e4 LT |
2328 | #ifdef CONFIG_SERIAL_MPSC |
2329 | mv64x60_mpsc0_pdata.brg_can_tune = 1; | |
2330 | mv64x60_mpsc0_pdata.cache_mgmt = 1; | |
2331 | mv64x60_mpsc1_pdata.brg_can_tune = 1; | |
2332 | mv64x60_mpsc1_pdata.cache_mgmt = 1; | |
2333 | #endif | |
1da177e4 LT |
2334 | } |
2335 | ||
2336 | /* | |
2337 | * mv64460_chip_specific_init() | |
2338 | * | |
a8de5ce9 | 2339 | * Implement errata workarounds for the MV64460. |
1da177e4 LT |
2340 | */ |
2341 | static void __init | |
2342 | mv64460_chip_specific_init(struct mv64x60_handle *bh, | |
2343 | struct mv64x60_setup_info *si) | |
2344 | { | |
d01c08c9 MG |
2345 | #if !defined(CONFIG_NOT_COHERENT_CACHE) |
2346 | mv64x60_set_bits(bh, MV64360_D_UNIT_CONTROL_HIGH, (1<<24) | (1<<25)); | |
2347 | mv64x60_set_bits(bh, MV64460_D_UNIT_MMASK, (1<<1) | (1<<4)); | |
2348 | #endif | |
1da177e4 LT |
2349 | #ifdef CONFIG_SERIAL_MPSC |
2350 | mv64x60_mpsc0_pdata.brg_can_tune = 1; | |
d01c08c9 | 2351 | mv64x60_mpsc0_pdata.cache_mgmt = 1; |
1da177e4 | 2352 | mv64x60_mpsc1_pdata.brg_can_tune = 1; |
d01c08c9 | 2353 | mv64x60_mpsc1_pdata.cache_mgmt = 1; |
1da177e4 | 2354 | #endif |
1da177e4 | 2355 | } |
d01c08c9 MG |
2356 | |
2357 | ||
2358 | #if defined(CONFIG_SYSFS) && !defined(CONFIG_GT64260) | |
2359 | /* Export the hotswap register via sysfs for enum event monitoring */ | |
2360 | #define VAL_LEN_MAX 11 /* 32-bit hex or dec stringified number + '\n' */ | |
2361 | ||
2362 | DECLARE_MUTEX(mv64xxx_hs_lock); | |
2363 | ||
2364 | static ssize_t | |
2365 | mv64xxx_hs_reg_read(struct kobject *kobj, char *buf, loff_t off, size_t count) | |
2366 | { | |
2367 | u32 v; | |
2368 | u8 save_exclude; | |
2369 | ||
2370 | if (off > 0) | |
2371 | return 0; | |
2372 | if (count < VAL_LEN_MAX) | |
2373 | return -EINVAL; | |
2374 | ||
2375 | if (down_interruptible(&mv64xxx_hs_lock)) | |
2376 | return -ERESTARTSYS; | |
2377 | save_exclude = mv64x60_pci_exclude_bridge; | |
2378 | mv64x60_pci_exclude_bridge = 0; | |
2379 | early_read_config_dword(&sysfs_hose_a, 0, PCI_DEVFN(0, 0), | |
2380 | MV64360_PCICFG_CPCI_HOTSWAP, &v); | |
2381 | mv64x60_pci_exclude_bridge = save_exclude; | |
2382 | up(&mv64xxx_hs_lock); | |
2383 | ||
2384 | return sprintf(buf, "0x%08x\n", v); | |
2385 | } | |
2386 | ||
2387 | static ssize_t | |
2388 | mv64xxx_hs_reg_write(struct kobject *kobj, char *buf, loff_t off, size_t count) | |
2389 | { | |
2390 | u32 v; | |
2391 | u8 save_exclude; | |
2392 | ||
2393 | if (off > 0) | |
2394 | return 0; | |
2395 | if (count <= 0) | |
2396 | return -EINVAL; | |
2397 | ||
2398 | if (sscanf(buf, "%i", &v) == 1) { | |
2399 | if (down_interruptible(&mv64xxx_hs_lock)) | |
2400 | return -ERESTARTSYS; | |
2401 | save_exclude = mv64x60_pci_exclude_bridge; | |
2402 | mv64x60_pci_exclude_bridge = 0; | |
2403 | early_write_config_dword(&sysfs_hose_a, 0, PCI_DEVFN(0, 0), | |
2404 | MV64360_PCICFG_CPCI_HOTSWAP, v); | |
2405 | mv64x60_pci_exclude_bridge = save_exclude; | |
2406 | up(&mv64xxx_hs_lock); | |
2407 | } | |
2408 | else | |
2409 | count = -EINVAL; | |
2410 | ||
2411 | return count; | |
2412 | } | |
2413 | ||
2414 | static struct bin_attribute mv64xxx_hs_reg_attr = { /* Hotswap register */ | |
2415 | .attr = { | |
2416 | .name = "hs_reg", | |
2417 | .mode = S_IRUGO | S_IWUSR, | |
d01c08c9 MG |
2418 | }, |
2419 | .size = VAL_LEN_MAX, | |
2420 | .read = mv64xxx_hs_reg_read, | |
2421 | .write = mv64xxx_hs_reg_write, | |
2422 | }; | |
2423 | ||
2424 | /* Provide sysfs file indicating if this platform supports the hs_reg */ | |
2425 | static ssize_t | |
2426 | mv64xxx_hs_reg_valid_show(struct device *dev, struct device_attribute *attr, | |
2427 | char *buf) | |
2428 | { | |
2429 | struct platform_device *pdev; | |
2430 | struct mv64xxx_pdata *pdp; | |
2431 | u32 v; | |
2432 | ||
2433 | pdev = container_of(dev, struct platform_device, dev); | |
2434 | pdp = (struct mv64xxx_pdata *)pdev->dev.platform_data; | |
2435 | ||
2436 | if (down_interruptible(&mv64xxx_hs_lock)) | |
2437 | return -ERESTARTSYS; | |
2438 | v = pdp->hs_reg_valid; | |
2439 | up(&mv64xxx_hs_lock); | |
2440 | ||
2441 | return sprintf(buf, "%i\n", v); | |
2442 | } | |
2443 | static DEVICE_ATTR(hs_reg_valid, S_IRUGO, mv64xxx_hs_reg_valid_show, NULL); | |
2444 | ||
2445 | static int __init | |
2446 | mv64xxx_sysfs_init(void) | |
2447 | { | |
2448 | sysfs_create_bin_file(&mv64xxx_device.dev.kobj, &mv64xxx_hs_reg_attr); | |
2449 | sysfs_create_file(&mv64xxx_device.dev.kobj,&dev_attr_hs_reg_valid.attr); | |
2450 | return 0; | |
2451 | } | |
2452 | subsys_initcall(mv64xxx_sysfs_init); | |
2453 | #endif |