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[POWERPC] Spelling fixes: arch/ppc/
[linux-2.6-block.git] / arch / ppc / platforms / sandpoint.c
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1da177e4 1/*
1da177e4
LT		 2 * Board setup routines for the Motorola SPS Sandpoint Test Platform.
3 *
4 * Author: Mark A. Greer
5 * mgreer@mvista.com
6 *
7 * 2000-2003 (c) MontaVista Software, Inc. This file is licensed under
8 * the terms of the GNU General Public License version 2. This program
9 * is licensed "as is" without any warranty of any kind, whether express
10 * or implied.
11 */
12
13/*
14 * This file adds support for the Motorola SPS Sandpoint Test Platform.
15 * These boards have a PPMC slot for the processor so any combination
16 * of cpu and host bridge can be attached. This port is for an 8240 PPMC
17 * module from Motorola SPS and other closely related cpu/host bridge
18 * combinations (e.g., 750/755/7400 with MPC107 host bridge).
19 * The sandpoint itself has a Windbond 83c553 (PCI-ISA bridge, 2 DMA ctlrs, 2
20 * cascaded 8259 interrupt ctlrs, 8254 Timer/Counter, and an IDE ctlr), a
21 * National 87308 (RTC, 2 UARTs, Keyboard & mouse ctlrs, and a floppy ctlr),
22 * and 4 PCI slots (only 2 of which are usable; the other 2 are keyed for 3.3V
23 * but are really 5V).
24 *
25 * The firmware on the sandpoint is called DINK (not my acronym :). This port
26 * depends on DINK to do some basic initialization (e.g., initialize the memory
27 * ctlr) and to ensure that the processor is using MAP B (CHRP map).
28 *
29 * The switch settings for the Sandpoint board MUST be as follows:
30 * S3: down
31 * S4: up
32 * S5: up
33 * S6: down
34 *
35 * 'down' is in the direction from the PCI slots towards the PPMC slot;
36 * 'up' is in the direction from the PPMC slot towards the PCI slots.
37 * Be careful, the way the sandpoint board is installed in XT chasses will
38 * make the directions reversed.
39 *
40 * Since Motorola listened to our suggestions for improvement, we now have
41 * the Sandpoint X3 board. All of the PCI slots are available, it uses
42 * the serial interrupt interface (just a hardware thing we need to
43 * configure properly).
44 *
45 * Use the default X3 switch settings. The interrupts are then:
46 * EPIC Source
47 * 0 SIOINT (8259, active low)
48 * 1 PCI #1
49 * 2 PCI #2
50 * 3 PCI #3
51 * 4 PCI #4
52 * 7 Winbond INTC (IDE interrupt)
53 * 8 Winbond INTD (IDE interrupt)
54 *
55 *
56 * Motorola has finally released a version of DINK32 that correctly
a8de5ce9 57 * (seemingly) initializes the memory controller correctly, regardless
1da177e4
LT		 58 * of the amount of memory in the system. Once a method of determining
59 * what version of DINK initializes the system for us, if applicable, is
60 * found, we can hopefully stop hardcoding 32MB of RAM.
61 */
62
1da177e4
LT		 63#include <linux/stddef.h>
64#include <linux/kernel.h>
65#include <linux/init.h>
66#include <linux/errno.h>
67#include <linux/reboot.h>
68#include <linux/pci.h>
69#include <linux/kdev_t.h>
70#include <linux/major.h>
71#include <linux/initrd.h>
72#include <linux/console.h>
73#include <linux/delay.h>
1da177e4
LT		 74#include <linux/ide.h>
75#include <linux/seq_file.h>
76#include <linux/root_dev.h>
77#include <linux/serial.h>
78#include <linux/tty.h> /* for linux/serial_core.h */
79#include <linux/serial_core.h>
682afbbd 80#include <linux/serial_8250.h>
1da177e4
LT		 81
82#include <asm/system.h>
83#include <asm/pgtable.h>
84#include <asm/page.h>
85#include <asm/time.h>
86#include <asm/dma.h>
87#include <asm/io.h>
88#include <asm/machdep.h>
89#include <asm/prom.h>
90#include <asm/smp.h>
91#include <asm/vga.h>
92#include <asm/open_pic.h>
93#include <asm/i8259.h>
94#include <asm/todc.h>
95#include <asm/bootinfo.h>
96#include <asm/mpc10x.h>
97#include <asm/pci-bridge.h>
98#include <asm/kgdb.h>
682afbbd 99#include <asm/ppc_sys.h>
1da177e4
LT		 100
101#include "sandpoint.h"
102
103/* Set non-zero if an X2 Sandpoint detected. */
104static int sandpoint_is_x2;
105
106unsigned char __res[sizeof(bd_t)];
107
108static void sandpoint_halt(void);
109static void sandpoint_probe_type(void);
110
111/*
112 * Define all of the IRQ senses and polarities. Taken from the
113 * Sandpoint X3 User's manual.
114 */
115static u_char sandpoint_openpic_initsenses[] __initdata = {
116 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* 0: SIOINT */
117 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* 2: PCI Slot 1 */
118 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* 3: PCI Slot 2 */
119 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* 4: PCI Slot 3 */
120 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* 5: PCI Slot 4 */
121 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* 8: IDE (INT C) */
122 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE) /* 9: IDE (INT D) */
123};
124
125/*
126 * Motorola SPS Sandpoint interrupt routing.
127 */
128static inline int
129x3_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
130{
131 static char pci_irq_table[][4] =
132 /*
133 * PCI IDSEL/INTPIN->INTLINE
134 * A B C D
135 */
136 {
137 { 16, 0, 0, 0 }, /* IDSEL 11 - i8259 on Winbond */
138 { 0, 0, 0, 0 }, /* IDSEL 12 - unused */
139 { 18, 21, 20, 19 }, /* IDSEL 13 - PCI slot 1 */
140 { 19, 18, 21, 20 }, /* IDSEL 14 - PCI slot 2 */
141 { 20, 19, 18, 21 }, /* IDSEL 15 - PCI slot 3 */
142 { 21, 20, 19, 18 }, /* IDSEL 16 - PCI slot 4 */
143 };
144
145 const long min_idsel = 11, max_idsel = 16, irqs_per_slot = 4;
146 return PCI_IRQ_TABLE_LOOKUP;
147}
148
149static inline int
150x2_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
151{
152 static char pci_irq_table[][4] =
153 /*
154 * PCI IDSEL/INTPIN->INTLINE
155 * A B C D
156 */
157 {
158 { 18, 0, 0, 0 }, /* IDSEL 11 - i8259 on Windbond */
159 { 0, 0, 0, 0 }, /* IDSEL 12 - unused */
160 { 16, 17, 18, 19 }, /* IDSEL 13 - PCI slot 1 */
161 { 17, 18, 19, 16 }, /* IDSEL 14 - PCI slot 2 */
162 { 18, 19, 16, 17 }, /* IDSEL 15 - PCI slot 3 */
163 { 19, 16, 17, 18 }, /* IDSEL 16 - PCI slot 4 */
164 };
165
166 const long min_idsel = 11, max_idsel = 16, irqs_per_slot = 4;
167 return PCI_IRQ_TABLE_LOOKUP;
168}
169
170static void __init
171sandpoint_setup_winbond_83553(struct pci_controller *hose)
172{
173 int devfn;
174
175 /*
176 * Route IDE interrupts directly to the 8259's IRQ 14 & 15.
177 * We can't route the IDE interrupt to PCI INTC# or INTD# because those
178 * woule interfere with the PMC's INTC# and INTD# lines.
179 */
180 /*
181 * Winbond Fcn 0
182 */
183 devfn = PCI_DEVFN(11,0);
184
185 early_write_config_byte(hose,
186 0,
187 devfn,
188 0x43, /* IDE Interrupt Routing Control */
189 0xef);
190 early_write_config_word(hose,
191 0,
192 devfn,
193 0x44, /* PCI Interrupt Routing Control */
194 0x0000);
195
196 /* Want ISA memory cycles to be forwarded to PCI bus */
197 early_write_config_byte(hose,
198 0,
199 devfn,
200 0x48, /* ISA-to-PCI Addr Decoder Control */
201 0xf0);
202
203 /* Enable Port 92. */
204 early_write_config_byte(hose,
205 0,
206 devfn,
207 0x4e, /* AT System Control Register */
208 0x06);
209 /*
210 * Winbond Fcn 1
211 */
212 devfn = PCI_DEVFN(11,1);
213
214 /* Put IDE controller into native mode. */
215 early_write_config_byte(hose,
216 0,
217 devfn,
218 0x09, /* Programming interface Register */
219 0x8f);
220
221 /* Init IRQ routing, enable both ports, disable fast 16 */
222 early_write_config_dword(hose,
223 0,
224 devfn,
225 0x40, /* IDE Control/Status Register */
226 0x00ff0011);
227 return;
228}
229
230/* On the sandpoint X2, we must avoid sending configuration cycles to
231 * device #12 (IDSEL addr = AD12).
232 */
233static int
234x2_exclude_device(u_char bus, u_char devfn)
235{
236 if ((bus == 0) && (PCI_SLOT(devfn) == SANDPOINT_HOST_BRIDGE_IDSEL))
237 return PCIBIOS_DEVICE_NOT_FOUND;
238 else
239 return PCIBIOS_SUCCESSFUL;
240}
241
242static void __init
243sandpoint_find_bridges(void)
244{
245 struct pci_controller *hose;
246
247 hose = pcibios_alloc_controller();
248
249 if (!hose)
250 return;
251
252 hose->first_busno = 0;
253 hose->last_busno = 0xff;
254
255 if (mpc10x_bridge_init(hose,
256 MPC10X_MEM_MAP_B,
257 MPC10X_MEM_MAP_B,
258 MPC10X_MAPB_EUMB_BASE) == 0) {
259
260 /* Do early winbond init, then scan PCI bus */
261 sandpoint_setup_winbond_83553(hose);
262 hose->last_busno = pciauto_bus_scan(hose, hose->first_busno);
263
264 ppc_md.pcibios_fixup = NULL;
265 ppc_md.pcibios_fixup_bus = NULL;
266 ppc_md.pci_swizzle = common_swizzle;
267 if (sandpoint_is_x2) {
268 ppc_md.pci_map_irq = x2_map_irq;
269 ppc_md.pci_exclude_device = x2_exclude_device;
270 } else
271 ppc_md.pci_map_irq = x3_map_irq;
272 }
273 else {
274 if (ppc_md.progress)
275 ppc_md.progress("Bridge init failed", 0x100);
276 printk("Host bridge init failed\n");
277 }
278
279 return;
280}
281
282static void __init
283sandpoint_setup_arch(void)
284{
285 /* Probe for Sandpoint model */
286 sandpoint_probe_type();
287 if (sandpoint_is_x2)
288 epic_serial_mode = 0;
289
290 loops_per_jiffy = 100000000 / HZ;
291
292#ifdef CONFIG_BLK_DEV_INITRD
293 if (initrd_start)
294 ROOT_DEV = Root_RAM0;
295 else
296#endif
297#ifdef CONFIG_ROOT_NFS
298 ROOT_DEV = Root_NFS;
299#else
300 ROOT_DEV = Root_HDA1;
301#endif
302
303 /* Lookup PCI host bridges */
304 sandpoint_find_bridges();
305
682afbbd
KG		 306 if (strncmp (cur_ppc_sys_spec->ppc_sys_name, "8245", 4) == 0)
307 {
308 bd_t *bp = (bd_t *)__res;
309 struct plat_serial8250_port *pdata;
682afbbd 310
13e886c3 311 pdata = (struct plat_serial8250_port *) ppc_sys_get_pdata(MPC10X_UART0);
682afbbd
KG		 312 if (pdata)
313 {
314 pdata[0].uartclk = bp->bi_busfreq;
13e886c3 315 }
682afbbd 316
13e886c3
KG		 317#ifdef CONFIG_SANDPOINT_ENABLE_UART1
318 pdata = (struct plat_serial8250_port *) ppc_sys_get_pdata(MPC10X_UART1);
319 if (pdata)
320 {
321 pdata[0].uartclk = bp->bi_busfreq;
682afbbd 322 }
13e886c3
KG		 323#else
324 ppc_sys_device_remove(MPC10X_UART1);
325#endif
9c4142a1 326 }
682afbbd 327
1da177e4
LT		 328 printk(KERN_INFO "Motorola SPS Sandpoint Test Platform\n");
329 printk(KERN_INFO "Port by MontaVista Software, Inc. (source@mvista.com)\n");
330
331 /* DINK32 12.3 and below do not correctly enable any caches.
332 * We will do this now with good known values. Future versions
333 * of DINK32 are supposed to get this correct.
334 */
335 if (cpu_has_feature(CPU_FTR_SPEC7450))
336 /* 745x is different. We only want to pass along enable. */
337 _set_L2CR(L2CR_L2E);
338 else if (cpu_has_feature(CPU_FTR_L2CR))
339 /* All modules have 1MB of L2. We also assume that an
340 * L2 divisor of 3 will work.
341 */
342 _set_L2CR(L2CR_L2E | L2CR_L2SIZ_1MB | L2CR_L2CLK_DIV3
343 | L2CR_L2RAM_PIPE | L2CR_L2OH_1_0 | L2CR_L2DF);
344#if 0
345 /* Untested right now. */
346 if (cpu_has_feature(CPU_FTR_L3CR)) {
347 /* Magic value. */
348 _set_L3CR(0x8f032000);
349 }
350#endif
351}
352
353#define SANDPOINT_87308_CFG_ADDR 0x15c
354#define SANDPOINT_87308_CFG_DATA 0x15d
355
356#define SANDPOINT_87308_CFG_INB(addr, byte) { \
357 outb((addr), SANDPOINT_87308_CFG_ADDR); \
358 (byte) = inb(SANDPOINT_87308_CFG_DATA); \
359}
360
361#define SANDPOINT_87308_CFG_OUTB(addr, byte) { \
362 outb((addr), SANDPOINT_87308_CFG_ADDR); \
363 outb((byte), SANDPOINT_87308_CFG_DATA); \
364}
365
366#define SANDPOINT_87308_SELECT_DEV(dev_num) { \
367 SANDPOINT_87308_CFG_OUTB(0x07, (dev_num)); \
368}
369
370#define SANDPOINT_87308_DEV_ENABLE(dev_num) { \
371 SANDPOINT_87308_SELECT_DEV(dev_num); \
372 SANDPOINT_87308_CFG_OUTB(0x30, 0x01); \
373}
374
375/*
376 * To probe the Sandpoint type, we need to check for a connection between GPIO
377 * pins 6 and 7 on the NS87308 SuperIO.
378 */
379static void __init sandpoint_probe_type(void)
380{
381 u8 x;
382 /* First, ensure that the GPIO pins are enabled. */
383 SANDPOINT_87308_SELECT_DEV(0x07); /* Select GPIO logical device */
384 SANDPOINT_87308_CFG_OUTB(0x60, 0x07); /* Base address 0x700 */
385 SANDPOINT_87308_CFG_OUTB(0x61, 0x00);
386 SANDPOINT_87308_CFG_OUTB(0x30, 0x01); /* Enable */
387
388 /* Now, set pin 7 to output and pin 6 to input. */
389 outb((inb(0x701) | 0x80) & 0xbf, 0x701);
390 /* Set push-pull output */
391 outb(inb(0x702) | 0x80, 0x702);
392 /* Set pull-up on input */
393 outb(inb(0x703) | 0x40, 0x703);
394 /* Set output high and check */
395 x = inb(0x700);
396 outb(x | 0x80, 0x700);
397 x = inb(0x700);
398 sandpoint_is_x2 = ! (x & 0x40);
399 if (ppc_md.progress && sandpoint_is_x2)
400 ppc_md.progress("High output says X2", 0);
401 /* Set output low and check */
402 outb(x & 0x7f, 0x700);
403 sandpoint_is_x2 |= inb(0x700) & 0x40;
404 if (ppc_md.progress && sandpoint_is_x2)
405 ppc_md.progress("Low output says X2", 0);
406 if (ppc_md.progress && ! sandpoint_is_x2)
407 ppc_md.progress("Sandpoint is X3", 0);
408}
409
410/*
411 * Fix IDE interrupts.
412 */
413static int __init
414sandpoint_fix_winbond_83553(void)
415{
416 /* Make some 8259 interrupt level sensitive */
417 outb(0xe0, 0x4d0);
418 outb(0xde, 0x4d1);
419
420 return 0;
421}
422
423arch_initcall(sandpoint_fix_winbond_83553);
424
425/*
426 * Initialize the ISA devices on the Nat'l PC87308VUL SuperIO chip.
427 */
428static int __init
429sandpoint_setup_natl_87308(void)
430{
431 u_char reg;
432
433 /*
434 * Enable all the devices on the Super I/O chip.
435 */
436 SANDPOINT_87308_SELECT_DEV(0x00); /* Select kbd logical device */
437 SANDPOINT_87308_CFG_OUTB(0xf0, 0x00); /* Set KBC clock to 8 Mhz */
438 SANDPOINT_87308_DEV_ENABLE(0x00); /* Enable keyboard */
439 SANDPOINT_87308_DEV_ENABLE(0x01); /* Enable mouse */
440 SANDPOINT_87308_DEV_ENABLE(0x02); /* Enable rtc */
441 SANDPOINT_87308_DEV_ENABLE(0x03); /* Enable fdc (floppy) */
442 SANDPOINT_87308_DEV_ENABLE(0x04); /* Enable parallel */
443 SANDPOINT_87308_DEV_ENABLE(0x05); /* Enable UART 2 */
444 SANDPOINT_87308_CFG_OUTB(0xf0, 0x82); /* Enable bank select regs */
445 SANDPOINT_87308_DEV_ENABLE(0x06); /* Enable UART 1 */
446 SANDPOINT_87308_CFG_OUTB(0xf0, 0x82); /* Enable bank select regs */
447
448 /* Set up floppy in PS/2 mode */
449 outb(0x09, SIO_CONFIG_RA);
450 reg = inb(SIO_CONFIG_RD);
451 reg = (reg & 0x3F) | 0x40;
452 outb(reg, SIO_CONFIG_RD);
453 outb(reg, SIO_CONFIG_RD); /* Have to write twice to change! */
454
455 return 0;
456}
457
458arch_initcall(sandpoint_setup_natl_87308);
459
460static int __init
461sandpoint_request_io(void)
462{
463 request_region(0x00,0x20,"dma1");
464 request_region(0x20,0x20,"pic1");
465 request_region(0x40,0x20,"timer");
466 request_region(0x80,0x10,"dma page reg");
467 request_region(0xa0,0x20,"pic2");
468 request_region(0xc0,0x20,"dma2");
469
470 return 0;
471}
472
473arch_initcall(sandpoint_request_io);
474
475/*
a8de5ce9 476 * Interrupt setup and service. Interrupts on the Sandpoint come
1da177e4
LT		 477 * from the four PCI slots plus the 8259 in the Winbond Super I/O (SIO).
478 * The 8259 is cascaded from EPIC IRQ0, IRQ1-4 map to PCI slots 1-4,
479 * IDE is on EPIC 7 and 8.
480 */
481static void __init
482sandpoint_init_IRQ(void)
483{
484 int i;
485
486 OpenPIC_InitSenses = sandpoint_openpic_initsenses;
487 OpenPIC_NumInitSenses = sizeof(sandpoint_openpic_initsenses);
488
489 mpc10x_set_openpic();
490 openpic_hookup_cascade(sandpoint_is_x2 ? 17 : NUM_8259_INTERRUPTS, "82c59 cascade",
491 i8259_irq);
492
1da177e4
LT		 493 /*
494 * The EPIC allows for a read in the range of 0xFEF00000 ->
495 * 0xFEFFFFFF to generate a PCI interrupt-acknowledge transaction.
496 */
f9bd170a 497 i8259_init(0xfef00000, 0);
1da177e4
LT		 498}
499
1da177e4
LT		 500static unsigned long __init
501sandpoint_find_end_of_memory(void)
502{
503 bd_t *bp = (bd_t *)__res;
504
505 if (bp->bi_memsize)
506 return bp->bi_memsize;
507
a8de5ce9 508 /* DINK32 13.0 correctly initializes things, so iff you use
1da177e4
LT		 509 * this you _should_ be able to change this instead of a
510 * hardcoded value. */
511#if 0
512 return mpc10x_get_mem_size(MPC10X_MEM_MAP_B);
513#else
514 return 32*1024*1024;
515#endif
516}
517
518static void __init
519sandpoint_map_io(void)
520{
521 io_block_mapping(0xfe000000, 0xfe000000, 0x02000000, _PAGE_IO);
522}
523
524static void
525sandpoint_restart(char *cmd)
526{
527 local_irq_disable();
528
529 /* Set exception prefix high - to the firmware */
530 _nmask_and_or_msr(0, MSR_IP);
531
532 /* Reset system via Port 92 */
533 outb(0x00, 0x92);
534 outb(0x01, 0x92);
535 for(;;); /* Spin until reset happens */
536}
537
538static void
539sandpoint_power_off(void)
540{
541 local_irq_disable();
542 for(;;); /* No way to shut power off with software */
543 /* NOTREACHED */
544}
545
546static void
547sandpoint_halt(void)
548{
549 sandpoint_power_off();
550 /* NOTREACHED */
551}
552
553static int
554sandpoint_show_cpuinfo(struct seq_file *m)
555{
556 seq_printf(m, "vendor\t\t: Motorola SPS\n");
557 seq_printf(m, "machine\t\t: Sandpoint\n");
558
559 return 0;
560}
561
562#if defined(CONFIG_BLK_DEV_IDE) || defined(CONFIG_BLK_DEV_IDE_MODULE)
563/*
564 * IDE support.
565 */
566static int sandpoint_ide_ports_known = 0;
567static unsigned long sandpoint_ide_regbase[MAX_HWIFS];
568static unsigned long sandpoint_ide_ctl_regbase[MAX_HWIFS];
569static unsigned long sandpoint_idedma_regbase;
570
571static void
572sandpoint_ide_probe(void)
573{
574 struct pci_dev *pdev = pci_get_device(PCI_VENDOR_ID_WINBOND,
575 PCI_DEVICE_ID_WINBOND_82C105, NULL);
576
577 if (pdev) {
578 sandpoint_ide_regbase[0]=pdev->resource[0].start;
579 sandpoint_ide_regbase[1]=pdev->resource[2].start;
580 sandpoint_ide_ctl_regbase[0]=pdev->resource[1].start;
581 sandpoint_ide_ctl_regbase[1]=pdev->resource[3].start;
582 sandpoint_idedma_regbase=pdev->resource[4].start;
583 pci_dev_put(pdev);
584 }
585
586 sandpoint_ide_ports_known = 1;
587}
588
589static int
590sandpoint_ide_default_irq(unsigned long base)
591{
592 if (sandpoint_ide_ports_known == 0)
593 sandpoint_ide_probe();
594
595 if (base == sandpoint_ide_regbase[0])
596 return SANDPOINT_IDE_INT0;
597 else if (base == sandpoint_ide_regbase[1])
598 return SANDPOINT_IDE_INT1;
599 else
600 return 0;
601}
602
603static unsigned long
604sandpoint_ide_default_io_base(int index)
605{
606 if (sandpoint_ide_ports_known == 0)
607 sandpoint_ide_probe();
608
609 return sandpoint_ide_regbase[index];
610}
611
612static void __init
613sandpoint_ide_init_hwif_ports(hw_regs_t *hw, unsigned long data_port,
614 unsigned long ctrl_port, int *irq)
615{
616 unsigned long reg = data_port;
617 uint alt_status_base;
618 int i;
619
620 for (i = IDE_DATA_OFFSET; i <= IDE_STATUS_OFFSET; i++) {
621 hw->io_ports[i] = reg++;
622 }
623
624 if (data_port == sandpoint_ide_regbase[0]) {
625 alt_status_base = sandpoint_ide_ctl_regbase[0] + 2;
626 hw->irq = 14;
627 }
628 else if (data_port == sandpoint_ide_regbase[1]) {
629 alt_status_base = sandpoint_ide_ctl_regbase[1] + 2;
630 hw->irq = 15;
631 }
632 else {
633 alt_status_base = 0;
634 hw->irq = 0;
635 }
636
637 if (ctrl_port) {
638 hw->io_ports[IDE_CONTROL_OFFSET] = ctrl_port;
639 } else {
640 hw->io_ports[IDE_CONTROL_OFFSET] = alt_status_base;
641 }
642
643 if (irq != NULL) {
644 *irq = hw->irq;
645 }
646}
647#endif
648
649/*
650 * Set BAT 3 to map 0xf8000000 to end of physical memory space 1-to-1.
651 */
652static __inline__ void
653sandpoint_set_bat(void)
654{
655 unsigned long bat3u, bat3l;
656
657 __asm__ __volatile__(
658 " lis %0,0xf800\n \
659 ori %1,%0,0x002a\n \
660 ori %0,%0,0x0ffe\n \
661 mtspr 0x21e,%0\n \
662 mtspr 0x21f,%1\n \
663 isync\n \
664 sync "
665 : "=r" (bat3u), "=r" (bat3l));
666}
667
668TODC_ALLOC();
669
670void __init
671platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
672 unsigned long r6, unsigned long r7)
673{
674 parse_bootinfo(find_bootinfo());
675
676 /* ASSUMPTION: If both r3 (bd_t pointer) and r6 (cmdline pointer)
677 * are non-zero, then we should use the board info from the bd_t
678 * structure and the cmdline pointed to by r6 instead of the
679 * information from birecs, if any. Otherwise, use the information
a8de5ce9 680 * from birecs as discovered by the preceding call to
1da177e4
LT		 681 * parse_bootinfo(). This rule should work with both PPCBoot, which
682 * uses a bd_t board info structure, and the kernel boot wrapper,
683 * which uses birecs.
684 */
685 if (r3 && r6) {
686 /* copy board info structure */
687 memcpy( (void *)__res,(void *)(r3+KERNELBASE), sizeof(bd_t) );
688 /* copy command line */
689 *(char *)(r7+KERNELBASE) = 0;
690 strcpy(cmd_line, (char *)(r6+KERNELBASE));
691 }
692
693#ifdef CONFIG_BLK_DEV_INITRD
694 /* take care of initrd if we have one */
695 if (r4) {
696 initrd_start = r4 + KERNELBASE;
697 initrd_end = r5 + KERNELBASE;
698 }
699#endif /* CONFIG_BLK_DEV_INITRD */
700
701 /* Map in board regs, etc. */
702 sandpoint_set_bat();
703
704 isa_io_base = MPC10X_MAPB_ISA_IO_BASE;
705 isa_mem_base = MPC10X_MAPB_ISA_MEM_BASE;
706 pci_dram_offset = MPC10X_MAPB_DRAM_OFFSET;
707 ISA_DMA_THRESHOLD = 0x00ffffff;
708 DMA_MODE_READ = 0x44;
709 DMA_MODE_WRITE = 0x48;
35d81a4b 710 ppc_do_canonicalize_irqs = 1;
1da177e4
LT		 711
712 ppc_md.setup_arch = sandpoint_setup_arch;
713 ppc_md.show_cpuinfo = sandpoint_show_cpuinfo;
1da177e4
LT		 714 ppc_md.init_IRQ = sandpoint_init_IRQ;
715 ppc_md.get_irq = openpic_get_irq;
716
717 ppc_md.restart = sandpoint_restart;
718 ppc_md.power_off = sandpoint_power_off;
719 ppc_md.halt = sandpoint_halt;
720
721 ppc_md.find_end_of_memory = sandpoint_find_end_of_memory;
722 ppc_md.setup_io_mappings = sandpoint_map_io;
723
724 TODC_INIT(TODC_TYPE_PC97307, 0x70, 0x00, 0x71, 8);
725 ppc_md.time_init = todc_time_init;
726 ppc_md.set_rtc_time = todc_set_rtc_time;
727 ppc_md.get_rtc_time = todc_get_rtc_time;
728 ppc_md.calibrate_decr = todc_calibrate_decr;
729
730 ppc_md.nvram_read_val = todc_mc146818_read_val;
731 ppc_md.nvram_write_val = todc_mc146818_write_val;
732
733#ifdef CONFIG_KGDB
734 ppc_md.kgdb_map_scc = gen550_kgdb_map_scc;
735#endif
736#ifdef CONFIG_SERIAL_TEXT_DEBUG
737 ppc_md.progress = gen550_progress;
738#endif
739
740#if defined(CONFIG_BLK_DEV_IDE) || defined(CONFIG_BLK_DEV_IDE_MODULE)
741 ppc_ide_md.default_irq = sandpoint_ide_default_irq;
742 ppc_ide_md.default_io_base = sandpoint_ide_default_io_base;
743 ppc_ide_md.ide_init_hwif = sandpoint_ide_init_hwif_ports;
744#endif
745}
Linux 6.x block layer and io_uring tree(s)