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1da177e4 LT |
1 | /* |
2 | * arch/ppc/platform/85xx/mpc85xx_cds_common.c | |
3 | * | |
4 | * MPC85xx CDS board specific routines | |
5 | * | |
6 | * Maintainer: Kumar Gala <kumar.gala@freescale.com> | |
7 | * | |
8 | * Copyright 2004 Freescale Semiconductor, Inc | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify it | |
11 | * under the terms of the GNU General Public License as published by the | |
12 | * Free Software Foundation; either version 2 of the License, or (at your | |
13 | * option) any later version. | |
14 | */ | |
15 | ||
16 | #include <linux/config.h> | |
17 | #include <linux/stddef.h> | |
18 | #include <linux/kernel.h> | |
19 | #include <linux/init.h> | |
20 | #include <linux/errno.h> | |
21 | #include <linux/reboot.h> | |
22 | #include <linux/pci.h> | |
23 | #include <linux/kdev_t.h> | |
24 | #include <linux/major.h> | |
25 | #include <linux/console.h> | |
26 | #include <linux/delay.h> | |
1da177e4 LT |
27 | #include <linux/seq_file.h> |
28 | #include <linux/serial.h> | |
29 | #include <linux/module.h> | |
30 | #include <linux/root_dev.h> | |
31 | #include <linux/initrd.h> | |
32 | #include <linux/tty.h> | |
33 | #include <linux/serial_core.h> | |
34 | #include <linux/fsl_devices.h> | |
35 | ||
36 | #include <asm/system.h> | |
37 | #include <asm/pgtable.h> | |
38 | #include <asm/page.h> | |
39 | #include <asm/atomic.h> | |
40 | #include <asm/time.h> | |
41 | #include <asm/todc.h> | |
42 | #include <asm/io.h> | |
43 | #include <asm/machdep.h> | |
1da177e4 | 44 | #include <asm/open_pic.h> |
ed369596 | 45 | #include <asm/i8259.h> |
1da177e4 LT |
46 | #include <asm/bootinfo.h> |
47 | #include <asm/pci-bridge.h> | |
48 | #include <asm/mpc85xx.h> | |
49 | #include <asm/irq.h> | |
50 | #include <asm/immap_85xx.h> | |
d054b5ac | 51 | #include <asm/cpm2.h> |
1da177e4 LT |
52 | #include <asm/ppc_sys.h> |
53 | #include <asm/kgdb.h> | |
54 | ||
55 | #include <mm/mmu_decl.h> | |
56 | #include <syslib/cpm2_pic.h> | |
57 | #include <syslib/ppc85xx_common.h> | |
58 | #include <syslib/ppc85xx_setup.h> | |
59 | ||
60 | ||
61 | #ifndef CONFIG_PCI | |
62 | unsigned long isa_io_base = 0; | |
63 | unsigned long isa_mem_base = 0; | |
64 | #endif | |
65 | ||
66 | extern unsigned long total_memory; /* in mm/init */ | |
67 | ||
68 | unsigned char __res[sizeof (bd_t)]; | |
69 | ||
70 | static int cds_pci_slot = 2; | |
71 | static volatile u8 * cadmus; | |
72 | ||
73 | /* Internal interrupts are all Level Sensitive, and Positive Polarity */ | |
1da177e4 | 74 | static u_char mpc85xx_cds_openpic_initsenses[] __initdata = { |
65145e06 | 75 | MPC85XX_INTERNAL_IRQ_SENSES, |
1da177e4 LT |
76 | #if defined(CONFIG_PCI) |
77 | (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 0: PCI1 slot */ | |
78 | (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 1: PCI1 slot */ | |
79 | (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 2: PCI1 slot */ | |
80 | (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 3: PCI1 slot */ | |
81 | #else | |
82 | 0x0, /* External 0: */ | |
83 | 0x0, /* External 1: */ | |
84 | 0x0, /* External 2: */ | |
85 | 0x0, /* External 3: */ | |
86 | #endif | |
87 | 0x0, /* External 4: */ | |
88 | (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 5: PHY */ | |
89 | 0x0, /* External 6: */ | |
90 | 0x0, /* External 7: */ | |
91 | 0x0, /* External 8: */ | |
92 | 0x0, /* External 9: */ | |
93 | 0x0, /* External 10: */ | |
94 | #if defined(CONFIG_85xx_PCI2) && defined(CONFIG_PCI) | |
95 | (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 11: PCI2 slot 0 */ | |
96 | #else | |
97 | 0x0, /* External 11: */ | |
98 | #endif | |
99 | }; | |
100 | ||
101 | /* ************************************************************************ */ | |
102 | int | |
103 | mpc85xx_cds_show_cpuinfo(struct seq_file *m) | |
104 | { | |
105 | uint pvid, svid, phid1; | |
106 | uint memsize = total_memory; | |
107 | bd_t *binfo = (bd_t *) __res; | |
108 | unsigned int freq; | |
109 | ||
110 | /* get the core frequency */ | |
111 | freq = binfo->bi_intfreq; | |
112 | ||
113 | pvid = mfspr(SPRN_PVR); | |
114 | svid = mfspr(SPRN_SVR); | |
115 | ||
116 | seq_printf(m, "Vendor\t\t: Freescale Semiconductor\n"); | |
117 | seq_printf(m, "Machine\t\t: CDS - MPC%s (%x)\n", cur_ppc_sys_spec->ppc_sys_name, cadmus[CM_VER]); | |
118 | seq_printf(m, "clock\t\t: %dMHz\n", freq / 1000000); | |
119 | seq_printf(m, "PVR\t\t: 0x%x\n", pvid); | |
120 | seq_printf(m, "SVR\t\t: 0x%x\n", svid); | |
121 | ||
122 | /* Display cpu Pll setting */ | |
123 | phid1 = mfspr(SPRN_HID1); | |
124 | seq_printf(m, "PLL setting\t: 0x%x\n", ((phid1 >> 24) & 0x3f)); | |
125 | ||
126 | /* Display the amount of memory */ | |
127 | seq_printf(m, "Memory\t\t: %d MB\n", memsize / (1024 * 1024)); | |
128 | ||
129 | return 0; | |
130 | } | |
131 | ||
132 | #ifdef CONFIG_CPM2 | |
133 | static void cpm2_cascade(int irq, void *dev_id, struct pt_regs *regs) | |
134 | { | |
135 | while((irq = cpm2_get_irq(regs)) >= 0) | |
136 | __do_IRQ(irq, regs); | |
137 | } | |
138 | ||
139 | static struct irqaction cpm2_irqaction = { | |
140 | .handler = cpm2_cascade, | |
141 | .flags = SA_INTERRUPT, | |
142 | .mask = CPU_MASK_NONE, | |
143 | .name = "cpm2_cascade", | |
144 | }; | |
145 | #endif /* CONFIG_CPM2 */ | |
146 | ||
147 | void __init | |
148 | mpc85xx_cds_init_IRQ(void) | |
149 | { | |
150 | bd_t *binfo = (bd_t *) __res; | |
f1b04770 | 151 | int i; |
1da177e4 LT |
152 | |
153 | /* Determine the Physical Address of the OpenPIC regs */ | |
154 | phys_addr_t OpenPIC_PAddr = binfo->bi_immr_base + MPC85xx_OPENPIC_OFFSET; | |
155 | OpenPIC_Addr = ioremap(OpenPIC_PAddr, MPC85xx_OPENPIC_SIZE); | |
156 | OpenPIC_InitSenses = mpc85xx_cds_openpic_initsenses; | |
157 | OpenPIC_NumInitSenses = sizeof (mpc85xx_cds_openpic_initsenses); | |
158 | ||
159 | /* Skip reserved space and internal sources */ | |
65145e06 KG |
160 | #ifdef CONFIG_MPC8548 |
161 | openpic_set_sources(0, 48, OpenPIC_Addr + 0x10200); | |
162 | #else | |
1da177e4 | 163 | openpic_set_sources(0, 32, OpenPIC_Addr + 0x10200); |
65145e06 | 164 | #endif |
1da177e4 | 165 | /* Map PIC IRQs 0-11 */ |
65145e06 | 166 | openpic_set_sources(48, 12, OpenPIC_Addr + 0x10000); |
1da177e4 LT |
167 | |
168 | /* we let openpic interrupts starting from an offset, to | |
169 | * leave space for cascading interrupts underneath. | |
170 | */ | |
171 | openpic_init(MPC85xx_OPENPIC_IRQ_OFFSET); | |
172 | ||
6cf2b3fc | 173 | #ifdef CONFIG_PCI |
ed369596 KG |
174 | openpic_hookup_cascade(PIRQ0A, "82c59 cascade", i8259_irq); |
175 | ||
176 | for (i = 0; i < NUM_8259_INTERRUPTS; i++) | |
177 | irq_desc[i].handler = &i8259_pic; | |
178 | ||
179 | i8259_init(0); | |
6cf2b3fc | 180 | #endif |
ed369596 | 181 | |
1da177e4 LT |
182 | #ifdef CONFIG_CPM2 |
183 | /* Setup CPM2 PIC */ | |
184 | cpm2_init_IRQ(); | |
185 | ||
186 | setup_irq(MPC85xx_IRQ_CPM, &cpm2_irqaction); | |
187 | #endif | |
188 | ||
189 | return; | |
190 | } | |
191 | ||
192 | #ifdef CONFIG_PCI | |
193 | /* | |
194 | * interrupt routing | |
195 | */ | |
196 | int | |
197 | mpc85xx_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin) | |
198 | { | |
199 | struct pci_controller *hose = pci_bus_to_hose(dev->bus->number); | |
200 | ||
201 | if (!hose->index) | |
202 | { | |
203 | /* Handle PCI1 interrupts */ | |
204 | char pci_irq_table[][4] = | |
205 | /* | |
206 | * PCI IDSEL/INTPIN->INTLINE | |
207 | * A B C D | |
208 | */ | |
209 | ||
210 | /* Note IRQ assignment for slots is based on which slot the elysium is | |
211 | * in -- in this setup elysium is in slot #2 (this PIRQA as first | |
212 | * interrupt on slot */ | |
213 | { | |
214 | { 0, 1, 2, 3 }, /* 16 - PMC */ | |
ed369596 | 215 | { 0, 1, 2, 3 }, /* 17 P2P (Tsi320) */ |
1da177e4 LT |
216 | { 0, 1, 2, 3 }, /* 18 - Slot 1 */ |
217 | { 1, 2, 3, 0 }, /* 19 - Slot 2 */ | |
218 | { 2, 3, 0, 1 }, /* 20 - Slot 3 */ | |
219 | { 3, 0, 1, 2 }, /* 21 - Slot 4 */ | |
220 | }; | |
221 | ||
222 | const long min_idsel = 16, max_idsel = 21, irqs_per_slot = 4; | |
223 | int i, j; | |
224 | ||
225 | for (i = 0; i < 6; i++) | |
226 | for (j = 0; j < 4; j++) | |
227 | pci_irq_table[i][j] = | |
228 | ((pci_irq_table[i][j] + 5 - | |
229 | cds_pci_slot) & 0x3) + PIRQ0A; | |
230 | ||
231 | return PCI_IRQ_TABLE_LOOKUP; | |
232 | } else { | |
233 | /* Handle PCI2 interrupts (if we have one) */ | |
234 | char pci_irq_table[][4] = | |
235 | { | |
236 | /* | |
237 | * We only have one slot and one interrupt | |
238 | * going to PIRQA - PIRQD */ | |
239 | { PIRQ1A, PIRQ1A, PIRQ1A, PIRQ1A }, /* 21 - slot 0 */ | |
240 | }; | |
241 | ||
242 | const long min_idsel = 21, max_idsel = 21, irqs_per_slot = 4; | |
243 | ||
244 | return PCI_IRQ_TABLE_LOOKUP; | |
245 | } | |
246 | } | |
247 | ||
248 | #define ARCADIA_HOST_BRIDGE_IDSEL 17 | |
249 | #define ARCADIA_2ND_BRIDGE_IDSEL 3 | |
250 | ||
251 | extern int mpc85xx_pci1_last_busno; | |
252 | ||
253 | int | |
254 | mpc85xx_exclude_device(u_char bus, u_char devfn) | |
255 | { | |
256 | if (bus == 0 && PCI_SLOT(devfn) == 0) | |
257 | return PCIBIOS_DEVICE_NOT_FOUND; | |
258 | #ifdef CONFIG_85xx_PCI2 | |
259 | if (mpc85xx_pci1_last_busno) | |
260 | if (bus == (mpc85xx_pci1_last_busno + 1) && PCI_SLOT(devfn) == 0) | |
261 | return PCIBIOS_DEVICE_NOT_FOUND; | |
262 | #endif | |
263 | /* We explicitly do not go past the Tundra 320 Bridge */ | |
ed369596 | 264 | if ((bus == 1) && (PCI_SLOT(devfn) == ARCADIA_2ND_BRIDGE_IDSEL)) |
1da177e4 LT |
265 | return PCIBIOS_DEVICE_NOT_FOUND; |
266 | if ((bus == 0) && (PCI_SLOT(devfn) == ARCADIA_2ND_BRIDGE_IDSEL)) | |
267 | return PCIBIOS_DEVICE_NOT_FOUND; | |
268 | else | |
269 | return PCIBIOS_SUCCESSFUL; | |
270 | } | |
ed369596 KG |
271 | |
272 | void __init | |
273 | mpc85xx_cds_enable_via(struct pci_controller *hose) | |
274 | { | |
275 | u32 pci_class; | |
276 | u16 vid, did; | |
277 | ||
278 | early_read_config_dword(hose, 0, 0x88, PCI_CLASS_REVISION, &pci_class); | |
279 | if ((pci_class >> 16) != PCI_CLASS_BRIDGE_PCI) | |
280 | return; | |
281 | ||
282 | /* Configure P2P so that we can reach bus 1 */ | |
283 | early_write_config_byte(hose, 0, 0x88, PCI_PRIMARY_BUS, 0); | |
284 | early_write_config_byte(hose, 0, 0x88, PCI_SECONDARY_BUS, 1); | |
285 | early_write_config_byte(hose, 0, 0x88, PCI_SUBORDINATE_BUS, 0xff); | |
286 | ||
287 | early_read_config_word(hose, 1, 0x10, PCI_VENDOR_ID, &vid); | |
288 | early_read_config_word(hose, 1, 0x10, PCI_DEVICE_ID, &did); | |
289 | ||
290 | if ((vid != PCI_VENDOR_ID_VIA) || | |
291 | (did != PCI_DEVICE_ID_VIA_82C686)) | |
292 | return; | |
293 | ||
294 | /* Enable USB and IDE functions */ | |
295 | early_write_config_byte(hose, 1, 0x10, 0x48, 0x08); | |
296 | } | |
297 | ||
298 | void __init | |
299 | mpc85xx_cds_fixup_via(struct pci_controller *hose) | |
300 | { | |
301 | u32 pci_class; | |
302 | u16 vid, did; | |
303 | ||
304 | early_read_config_dword(hose, 0, 0x88, PCI_CLASS_REVISION, &pci_class); | |
305 | if ((pci_class >> 16) != PCI_CLASS_BRIDGE_PCI) | |
306 | return; | |
307 | ||
308 | /* | |
309 | * Force the backplane P2P bridge to have a window | |
310 | * open from 0x00000000-0x00001fff in PCI I/O space. | |
311 | * This allows legacy I/O (i8259, etc) on the VIA | |
312 | * southbridge to be accessed. | |
313 | */ | |
314 | early_write_config_byte(hose, 0, 0x88, PCI_IO_BASE, 0x00); | |
315 | early_write_config_word(hose, 0, 0x88, PCI_IO_BASE_UPPER16, 0x0000); | |
316 | early_write_config_byte(hose, 0, 0x88, PCI_IO_LIMIT, 0x10); | |
317 | early_write_config_word(hose, 0, 0x88, PCI_IO_LIMIT_UPPER16, 0x0000); | |
318 | ||
319 | early_read_config_word(hose, 1, 0x10, PCI_VENDOR_ID, &vid); | |
320 | early_read_config_word(hose, 1, 0x10, PCI_DEVICE_ID, &did); | |
321 | if ((vid != PCI_VENDOR_ID_VIA) || | |
322 | (did != PCI_DEVICE_ID_VIA_82C686)) | |
323 | return; | |
324 | ||
325 | /* | |
326 | * Since the P2P window was forced to cover the fixed | |
327 | * legacy I/O addresses, it is necessary to manually | |
328 | * place the base addresses for the IDE and USB functions | |
329 | * within this window. | |
330 | */ | |
331 | /* Function 1, IDE */ | |
332 | early_write_config_dword(hose, 1, 0x11, PCI_BASE_ADDRESS_0, 0x1ff8); | |
333 | early_write_config_dword(hose, 1, 0x11, PCI_BASE_ADDRESS_1, 0x1ff4); | |
334 | early_write_config_dword(hose, 1, 0x11, PCI_BASE_ADDRESS_2, 0x1fe8); | |
335 | early_write_config_dword(hose, 1, 0x11, PCI_BASE_ADDRESS_3, 0x1fe4); | |
336 | early_write_config_dword(hose, 1, 0x11, PCI_BASE_ADDRESS_4, 0x1fd0); | |
337 | ||
338 | /* Function 2, USB ports 0-1 */ | |
339 | early_write_config_dword(hose, 1, 0x12, PCI_BASE_ADDRESS_4, 0x1fa0); | |
340 | ||
341 | /* Function 3, USB ports 2-3 */ | |
342 | early_write_config_dword(hose, 1, 0x13, PCI_BASE_ADDRESS_4, 0x1f80); | |
343 | ||
344 | /* Function 5, Power Management */ | |
345 | early_write_config_dword(hose, 1, 0x15, PCI_BASE_ADDRESS_0, 0x1e00); | |
346 | early_write_config_dword(hose, 1, 0x15, PCI_BASE_ADDRESS_1, 0x1dfc); | |
347 | early_write_config_dword(hose, 1, 0x15, PCI_BASE_ADDRESS_2, 0x1df8); | |
348 | ||
349 | /* Function 6, AC97 Interface */ | |
350 | early_write_config_dword(hose, 1, 0x16, PCI_BASE_ADDRESS_0, 0x1c00); | |
351 | } | |
352 | ||
353 | void __init | |
354 | mpc85xx_cds_pcibios_fixup(void) | |
355 | { | |
356 | struct pci_dev *dev = NULL; | |
357 | u_char c; | |
358 | ||
359 | if ((dev = pci_find_device(PCI_VENDOR_ID_VIA, | |
360 | PCI_DEVICE_ID_VIA_82C586_1, NULL))) { | |
361 | /* | |
362 | * U-Boot does not set the enable bits | |
363 | * for the IDE device. Force them on here. | |
364 | */ | |
365 | pci_read_config_byte(dev, 0x40, &c); | |
366 | c |= 0x03; /* IDE: Chip Enable Bits */ | |
367 | pci_write_config_byte(dev, 0x40, c); | |
368 | ||
369 | /* | |
370 | * Since only primary interface works, force the | |
371 | * IDE function to standard primary IDE interrupt | |
372 | * w/ 8259 offset | |
373 | */ | |
374 | dev->irq = 14; | |
375 | pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq); | |
376 | } | |
377 | ||
378 | /* | |
379 | * Force legacy USB interrupt routing | |
380 | */ | |
381 | if ((dev = pci_find_device(PCI_VENDOR_ID_VIA, | |
382 | PCI_DEVICE_ID_VIA_82C586_2, NULL))) { | |
383 | dev->irq = 10; | |
384 | pci_write_config_byte(dev, PCI_INTERRUPT_LINE, 10); | |
385 | } | |
386 | ||
387 | if ((dev = pci_find_device(PCI_VENDOR_ID_VIA, | |
388 | PCI_DEVICE_ID_VIA_82C586_2, dev))) { | |
389 | dev->irq = 11; | |
390 | pci_write_config_byte(dev, PCI_INTERRUPT_LINE, 11); | |
391 | } | |
392 | } | |
1da177e4 LT |
393 | #endif /* CONFIG_PCI */ |
394 | ||
395 | TODC_ALLOC(); | |
396 | ||
397 | /* ************************************************************************ | |
398 | * | |
399 | * Setup the architecture | |
400 | * | |
401 | */ | |
402 | static void __init | |
403 | mpc85xx_cds_setup_arch(void) | |
404 | { | |
405 | bd_t *binfo = (bd_t *) __res; | |
406 | unsigned int freq; | |
407 | struct gianfar_platform_data *pdata; | |
408 | ||
409 | /* get the core frequency */ | |
410 | freq = binfo->bi_intfreq; | |
411 | ||
412 | printk("mpc85xx_cds_setup_arch\n"); | |
413 | ||
414 | #ifdef CONFIG_CPM2 | |
415 | cpm2_reset(); | |
416 | #endif | |
417 | ||
418 | cadmus = ioremap(CADMUS_BASE, CADMUS_SIZE); | |
419 | cds_pci_slot = ((cadmus[CM_CSR] >> 6) & 0x3) + 1; | |
420 | printk("CDS Version = %x in PCI slot %d\n", cadmus[CM_VER], cds_pci_slot); | |
421 | ||
422 | /* Setup TODC access */ | |
423 | TODC_INIT(TODC_TYPE_DS1743, | |
424 | 0, | |
425 | 0, | |
426 | ioremap(CDS_RTC_ADDR, CDS_RTC_SIZE), | |
427 | 8); | |
428 | ||
429 | /* Set loops_per_jiffy to a half-way reasonable value, | |
430 | for use until calibrate_delay gets called. */ | |
431 | loops_per_jiffy = freq / HZ; | |
432 | ||
433 | #ifdef CONFIG_PCI | |
91f9855a KG |
434 | /* VIA IDE configuration */ |
435 | ppc_md.pcibios_fixup = mpc85xx_cds_pcibios_fixup; | |
436 | ||
1da177e4 LT |
437 | /* setup PCI host bridges */ |
438 | mpc85xx_setup_hose(); | |
439 | #endif | |
440 | ||
441 | #ifdef CONFIG_SERIAL_8250 | |
442 | mpc85xx_early_serial_map(); | |
443 | #endif | |
444 | ||
445 | #ifdef CONFIG_SERIAL_TEXT_DEBUG | |
446 | /* Invalidate the entry we stole earlier the serial ports | |
447 | * should be properly mapped */ | |
5be061ee | 448 | invalidate_tlbcam_entry(num_tlbcam_entries - 1); |
1da177e4 LT |
449 | #endif |
450 | ||
451 | /* setup the board related information for the enet controllers */ | |
452 | pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_TSEC1); | |
c91999bb KG |
453 | if (pdata) { |
454 | pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR; | |
455 | pdata->interruptPHY = MPC85xx_IRQ_EXT5; | |
456 | pdata->phyid = 0; | |
457 | /* fixup phy address */ | |
458 | pdata->phy_reg_addr += binfo->bi_immr_base; | |
459 | memcpy(pdata->mac_addr, binfo->bi_enetaddr, 6); | |
460 | } | |
1da177e4 LT |
461 | |
462 | pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_TSEC2); | |
c91999bb KG |
463 | if (pdata) { |
464 | pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR; | |
465 | pdata->interruptPHY = MPC85xx_IRQ_EXT5; | |
466 | pdata->phyid = 1; | |
467 | /* fixup phy address */ | |
468 | pdata->phy_reg_addr += binfo->bi_immr_base; | |
469 | memcpy(pdata->mac_addr, binfo->bi_enet1addr, 6); | |
470 | } | |
471 | ||
472 | pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_eTSEC1); | |
473 | if (pdata) { | |
474 | pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR; | |
475 | pdata->interruptPHY = MPC85xx_IRQ_EXT5; | |
476 | pdata->phyid = 0; | |
477 | /* fixup phy address */ | |
478 | pdata->phy_reg_addr += binfo->bi_immr_base; | |
479 | memcpy(pdata->mac_addr, binfo->bi_enetaddr, 6); | |
480 | } | |
481 | ||
482 | pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_eTSEC2); | |
483 | if (pdata) { | |
484 | pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR; | |
485 | pdata->interruptPHY = MPC85xx_IRQ_EXT5; | |
486 | pdata->phyid = 1; | |
487 | /* fixup phy address */ | |
488 | pdata->phy_reg_addr += binfo->bi_immr_base; | |
489 | memcpy(pdata->mac_addr, binfo->bi_enet1addr, 6); | |
490 | } | |
1da177e4 | 491 | |
c91999bb KG |
492 | ppc_sys_device_remove(MPC85xx_eTSEC3); |
493 | ppc_sys_device_remove(MPC85xx_eTSEC4); | |
1da177e4 LT |
494 | |
495 | #ifdef CONFIG_BLK_DEV_INITRD | |
496 | if (initrd_start) | |
497 | ROOT_DEV = Root_RAM0; | |
498 | else | |
499 | #endif | |
500 | #ifdef CONFIG_ROOT_NFS | |
501 | ROOT_DEV = Root_NFS; | |
502 | #else | |
503 | ROOT_DEV = Root_HDA1; | |
504 | #endif | |
505 | } | |
506 | ||
507 | /* ************************************************************************ */ | |
508 | void __init | |
509 | platform_init(unsigned long r3, unsigned long r4, unsigned long r5, | |
510 | unsigned long r6, unsigned long r7) | |
511 | { | |
512 | /* parse_bootinfo must always be called first */ | |
513 | parse_bootinfo(find_bootinfo()); | |
514 | ||
515 | /* | |
516 | * If we were passed in a board information, copy it into the | |
517 | * residual data area. | |
518 | */ | |
519 | if (r3) { | |
520 | memcpy((void *) __res, (void *) (r3 + KERNELBASE), | |
521 | sizeof (bd_t)); | |
522 | ||
523 | } | |
524 | #ifdef CONFIG_SERIAL_TEXT_DEBUG | |
525 | { | |
526 | bd_t *binfo = (bd_t *) __res; | |
527 | struct uart_port p; | |
528 | ||
529 | /* Use the last TLB entry to map CCSRBAR to allow access to DUART regs */ | |
5be061ee | 530 | settlbcam(num_tlbcam_entries - 1, binfo->bi_immr_base, |
1da177e4 LT |
531 | binfo->bi_immr_base, MPC85xx_CCSRBAR_SIZE, _PAGE_IO, 0); |
532 | ||
533 | memset(&p, 0, sizeof (p)); | |
534 | p.iotype = SERIAL_IO_MEM; | |
535 | p.membase = (void *) binfo->bi_immr_base + MPC85xx_UART0_OFFSET; | |
536 | p.uartclk = binfo->bi_busfreq; | |
537 | ||
538 | gen550_init(0, &p); | |
539 | ||
540 | memset(&p, 0, sizeof (p)); | |
541 | p.iotype = SERIAL_IO_MEM; | |
542 | p.membase = (void *) binfo->bi_immr_base + MPC85xx_UART1_OFFSET; | |
543 | p.uartclk = binfo->bi_busfreq; | |
544 | ||
545 | gen550_init(1, &p); | |
546 | } | |
547 | #endif | |
548 | ||
549 | #if defined(CONFIG_BLK_DEV_INITRD) | |
550 | /* | |
551 | * If the init RAM disk has been configured in, and there's a valid | |
552 | * starting address for it, set it up. | |
553 | */ | |
554 | if (r4) { | |
555 | initrd_start = r4 + KERNELBASE; | |
556 | initrd_end = r5 + KERNELBASE; | |
557 | } | |
558 | #endif /* CONFIG_BLK_DEV_INITRD */ | |
559 | ||
560 | /* Copy the kernel command line arguments to a safe place. */ | |
561 | ||
562 | if (r6) { | |
563 | *(char *) (r7 + KERNELBASE) = 0; | |
564 | strcpy(cmd_line, (char *) (r6 + KERNELBASE)); | |
565 | } | |
566 | ||
567 | identify_ppc_sys_by_id(mfspr(SPRN_SVR)); | |
568 | ||
569 | /* setup the PowerPC module struct */ | |
570 | ppc_md.setup_arch = mpc85xx_cds_setup_arch; | |
571 | ppc_md.show_cpuinfo = mpc85xx_cds_show_cpuinfo; | |
572 | ||
573 | ppc_md.init_IRQ = mpc85xx_cds_init_IRQ; | |
574 | ppc_md.get_irq = openpic_get_irq; | |
575 | ||
576 | ppc_md.restart = mpc85xx_restart; | |
577 | ppc_md.power_off = mpc85xx_power_off; | |
578 | ppc_md.halt = mpc85xx_halt; | |
579 | ||
580 | ppc_md.find_end_of_memory = mpc85xx_find_end_of_memory; | |
581 | ||
582 | ppc_md.calibrate_decr = mpc85xx_calibrate_decr; | |
583 | ||
584 | ppc_md.time_init = todc_time_init; | |
585 | ppc_md.set_rtc_time = todc_set_rtc_time; | |
586 | ppc_md.get_rtc_time = todc_get_rtc_time; | |
587 | ||
588 | ppc_md.nvram_read_val = todc_direct_read_val; | |
589 | ppc_md.nvram_write_val = todc_direct_write_val; | |
590 | ||
591 | #if defined(CONFIG_SERIAL_8250) && defined(CONFIG_SERIAL_TEXT_DEBUG) | |
592 | ppc_md.progress = gen550_progress; | |
593 | #endif /* CONFIG_SERIAL_8250 && CONFIG_SERIAL_TEXT_DEBUG */ | |
252fcaed KG |
594 | #if defined(CONFIG_SERIAL_8250) && defined(CONFIG_KGDB) |
595 | ppc_md.early_serial_map = mpc85xx_early_serial_map; | |
596 | #endif /* CONFIG_SERIAL_8250 && CONFIG_KGDB */ | |
1da177e4 LT |
597 | |
598 | if (ppc_md.progress) | |
599 | ppc_md.progress("mpc85xx_cds_init(): exit", 0); | |
600 | ||
601 | return; | |
602 | } |