[linux-2.6-block.git] / arch / ppc / platforms / 4xx / ibmnp405h.c

/*
 * Author: Armin Kuster <akuster@mvista.com>
 *
 * 2000-2002 (c) MontaVista, Software, Inc.  This file is licensed under
 * the terms of the GNU General Public License version 2.  This program
 * is licensed "as is" without any warranty of any kind, whether express
 * or implied.
 */

#include <linux/config.h>
#include <linux/init.h>
#include <asm/ocp.h>
#include <platforms/4xx/ibmnp405h.h>

static struct ocp_func_emac_data ibmnp405h_emac0_def = {
	.rgmii_idx	= -1,		/* No RGMII */
	.rgmii_mux	= -1,		/* No RGMII */
	.zmii_idx	= 0,		/* ZMII device index */
	.zmii_mux	= 0,		/* ZMII input of this EMAC */
	.mal_idx	= 0,		/* MAL device index */
	.mal_rx_chan	= 0,		/* MAL rx channel number */
	.mal_tx_chan	= 0,		/* MAL tx channel number */
	.wol_irq	= 41,		/* WOL interrupt number */
	.mdio_idx	= -1,		/* No shared MDIO */
	.tah_idx	= -1,		/* No TAH */
};

static struct ocp_func_emac_data ibmnp405h_emac1_def = {
	.rgmii_idx	= -1,		/* No RGMII */
	.rgmii_mux	= -1,		/* No RGMII */
	.zmii_idx	= 0,		/* ZMII device index */
	.zmii_mux	= 1,		/* ZMII input of this EMAC */
	.mal_idx	= 0,		/* MAL device index */
	.mal_rx_chan	= 1,		/* MAL rx channel number */
	.mal_tx_chan	= 2,		/* MAL tx channel number */
	.wol_irq	= 41,		/* WOL interrupt number */
	.mdio_idx	= -1,		/* No shared MDIO */
	.tah_idx	= -1,		/* No TAH */
};
static struct ocp_func_emac_data ibmnp405h_emac2_def = {
	.rgmii_idx	= -1,		/* No RGMII */
	.rgmii_mux	= -1,		/* No RGMII */
	.zmii_idx	= 0,		/* ZMII device index */
	.zmii_mux	= 2,		/* ZMII input of this EMAC */
	.mal_idx	= 0,		/* MAL device index */
	.mal_rx_chan	= 2,		/* MAL rx channel number */
	.mal_tx_chan	= 4,		/* MAL tx channel number */
	.wol_irq	= 41,		/* WOL interrupt number */
	.mdio_idx	= -1,		/* No shared MDIO */
	.tah_idx	= -1,		/* No TAH */
};
static struct ocp_func_emac_data ibmnp405h_emac3_def = {
	.rgmii_idx	= -1,		/* No RGMII */
	.rgmii_mux	= -1,		/* No RGMII */
	.zmii_idx	= 0,		/* ZMII device index */
	.zmii_mux	= 3,		/* ZMII input of this EMAC */
	.mal_idx	= 0,		/* MAL device index */
	.mal_rx_chan	= 3,		/* MAL rx channel number */
	.mal_tx_chan	= 6,		/* MAL tx channel number */
	.wol_irq	= 41,		/* WOL interrupt number */
	.mdio_idx	= -1,		/* No shared MDIO */
	.tah_idx	= -1,		/* No TAH */
};
OCP_SYSFS_EMAC_DATA()

static struct ocp_func_mal_data ibmnp405h_mal0_def = {
	.num_tx_chans	= 8,		/* Number of TX channels */
	.num_rx_chans	= 4,		/* Number of RX channels */
	.txeob_irq	= 17,		/* TX End Of Buffer IRQ  */
	.rxeob_irq	= 18,		/* RX End Of Buffer IRQ  */
	.txde_irq	= 46,		/* TX Descriptor Error IRQ */
	.rxde_irq	= 47,		/* RX Descriptor Error IRQ */
	.serr_irq	= 45,		/* MAL System Error IRQ    */
	.dcr_base	= DCRN_MAL_BASE /* MAL0_CFG DCR number */
};
OCP_SYSFS_MAL_DATA()

static struct ocp_func_iic_data ibmnp405h_iic0_def = {
	.fast_mode	= 0,		/* Use standad mode (100Khz) */
};
OCP_SYSFS_IIC_DATA()

struct ocp_def core_ocp[] = {
	{ .vendor	= OCP_VENDOR_IBM,
	  .function	= OCP_FUNC_OPB,
	  .index	= 0,
	  .paddr	= 0xEF600000,
	  .irq		= OCP_IRQ_NA,
	  .pm		= OCP_CPM_NA,
	},
	{ .vendor	= OCP_VENDOR_IBM,
	  .function	= OCP_FUNC_16550,
	  .index	= 0,
	  .paddr	= UART0_IO_BASE,
	  .irq		= UART0_INT,
	  .pm		= IBM_CPM_UART0
	},
	{ .vendor	= OCP_VENDOR_IBM,
	  .function	= OCP_FUNC_16550,
	  .index	= 1,
	  .paddr	= UART1_IO_BASE,
	  .irq		= UART1_INT,
	  .pm		= IBM_CPM_UART1
	},
	{ .vendor	= OCP_VENDOR_IBM,
	  .function	= OCP_FUNC_IIC,
	  .paddr	= 0xEF600500,
	  .irq		= 2,
	  .pm		= IBM_CPM_IIC0,
	  .additions	= &ibmnp405h_iic0_def,
	  .show		= &ocp_show_iic_data
	},
	{ .vendor	= OCP_VENDOR_IBM,
	  .function	= OCP_FUNC_GPIO,
	  .paddr	= 0xEF600700,
	  .irq		= OCP_IRQ_NA,
	  .pm		= IBM_CPM_GPIO0
	},
	{ .vendor	= OCP_VENDOR_IBM,
	  .function	= OCP_FUNC_MAL,
	  .paddr	= OCP_PADDR_NA,
	  .irq		= OCP_IRQ_NA,
	  .pm		= OCP_CPM_NA,
	  .additions	= &ibmnp405h_mal0_def,
	  .show		= &ocp_show_mal_data,
	},
	{ .vendor	= OCP_VENDOR_IBM,
	  .function	= OCP_FUNC_EMAC,
	  .index	= 0,
	  .paddr	= EMAC0_BASE,
	  .irq		= 37,
	  .pm		= IBM_CPM_EMAC0,
	  .additions	= &ibmnp405h_emac0_def,
	  .show		= &ocp_show_emac_data,
	},
	{ .vendor	= OCP_VENDOR_IBM,
	  .function	= OCP_FUNC_EMAC,
	  .index	= 1,
	  .paddr	= 0xEF600900,
	  .irq		= 38,
	  .pm		= IBM_CPM_EMAC1,
	  .additions	= &ibmnp405h_emac1_def,
	  .show		= &ocp_show_emac_data,
	},
	{ .vendor	= OCP_VENDOR_IBM,
	  .function	= OCP_FUNC_EMAC,
	  .index	= 2,
	  .paddr	= 0xEF600a00,
	  .irq		= 39,
	  .pm		= IBM_CPM_EMAC2,
	  .additions	= &ibmnp405h_emac2_def,
	  .show		= &ocp_show_emac_data,
	},
	{ .vendor	= OCP_VENDOR_IBM,
	  .function	= OCP_FUNC_EMAC,
	  .index	= 3,
	  .paddr	= 0xEF600b00,
	  .irq		= 40,
	  .pm		= IBM_CPM_EMAC3,
	  .additions	= &ibmnp405h_emac3_def,
	  .show		= &ocp_show_emac_data,
	},
	{ .vendor	= OCP_VENDOR_IBM,
	  .function	= OCP_FUNC_ZMII,
	  .paddr	= 0xEF600C10,
	  .irq		= OCP_IRQ_NA,
	  .pm		= OCP_CPM_NA,
	},
	{ .vendor	= OCP_VENDOR_INVALID
	}
};
Commit	Line	Data
1da177e4	1	/*
1da177e4 LT	2	* Author: Armin Kuster <akuster@mvista.com>
	3	*
	4	* 2000-2002 (c) MontaVista, Software, Inc. This file is licensed under
	5	* the terms of the GNU General Public License version 2. This program
	6	* is licensed "as is" without any warranty of any kind, whether express
	7	* or implied.
	8	*/
	9
	10	#include <linux/config.h>
	11	#include <linux/init.h>
	12	#include <asm/ocp.h>
	13	#include <platforms/4xx/ibmnp405h.h>
	14
	15	static struct ocp_func_emac_data ibmnp405h_emac0_def = {
	16	.rgmii_idx = -1, /* No RGMII */
	17	.rgmii_mux = -1, /* No RGMII */
	18	.zmii_idx = 0, /* ZMII device index */
	19	.zmii_mux = 0, /* ZMII input of this EMAC */
	20	.mal_idx = 0, /* MAL device index */
	21	.mal_rx_chan = 0, /* MAL rx channel number */
	22	.mal_tx_chan = 0, /* MAL tx channel number */
	23	.wol_irq = 41, /* WOL interrupt number */
	24	.mdio_idx = -1, /* No shared MDIO */
	25	.tah_idx = -1, /* No TAH */
	26	};
	27
	28	static struct ocp_func_emac_data ibmnp405h_emac1_def = {
	29	.rgmii_idx = -1, /* No RGMII */
	30	.rgmii_mux = -1, /* No RGMII */
	31	.zmii_idx = 0, /* ZMII device index */
	32	.zmii_mux = 1, /* ZMII input of this EMAC */
	33	.mal_idx = 0, /* MAL device index */
	34	.mal_rx_chan = 1, /* MAL rx channel number */
cce9d7e3	35	.mal_tx_chan = 2, /* MAL tx channel number */
1da177e4 LT	36	.wol_irq = 41, /* WOL interrupt number */
	37	.mdio_idx = -1, /* No shared MDIO */
	38	.tah_idx = -1, /* No TAH */
	39	};
	40	static struct ocp_func_emac_data ibmnp405h_emac2_def = {
	41	.rgmii_idx = -1, /* No RGMII */
	42	.rgmii_mux = -1, /* No RGMII */
	43	.zmii_idx = 0, /* ZMII device index */
	44	.zmii_mux = 2, /* ZMII input of this EMAC */
	45	.mal_idx = 0, /* MAL device index */
	46	.mal_rx_chan = 2, /* MAL rx channel number */
cce9d7e3	47	.mal_tx_chan = 4, /* MAL tx channel number */
1da177e4 LT	48	.wol_irq = 41, /* WOL interrupt number */
	49	.mdio_idx = -1, /* No shared MDIO */
	50	.tah_idx = -1, /* No TAH */
	51	};
	52	static struct ocp_func_emac_data ibmnp405h_emac3_def = {
	53	.rgmii_idx = -1, /* No RGMII */
	54	.rgmii_mux = -1, /* No RGMII */
	55	.zmii_idx = 0, /* ZMII device index */
	56	.zmii_mux = 3, /* ZMII input of this EMAC */
	57	.mal_idx = 0, /* MAL device index */
	58	.mal_rx_chan = 3, /* MAL rx channel number */
cce9d7e3	59	.mal_tx_chan = 6, /* MAL tx channel number */
1da177e4 LT	60	.wol_irq = 41, /* WOL interrupt number */
	61	.mdio_idx = -1, /* No shared MDIO */
	62	.tah_idx = -1, /* No TAH */
	63	};
	64	OCP_SYSFS_EMAC_DATA()
	65
	66	static struct ocp_func_mal_data ibmnp405h_mal0_def = {
	67	.num_tx_chans = 8, /* Number of TX channels */
	68	.num_rx_chans = 4, /* Number of RX channels */
	69	.txeob_irq = 17, /* TX End Of Buffer IRQ */
	70	.rxeob_irq = 18, /* RX End Of Buffer IRQ */
	71	.txde_irq = 46, /* TX Descriptor Error IRQ */
	72	.rxde_irq = 47, /* RX Descriptor Error IRQ */
	73	.serr_irq = 45, /* MAL System Error IRQ */
3a0a401b	74	.dcr_base = DCRN_MAL_BASE /* MAL0_CFG DCR number */
1da177e4 LT	75	};
	76	OCP_SYSFS_MAL_DATA()
	77
	78	static struct ocp_func_iic_data ibmnp405h_iic0_def = {
	79	.fast_mode = 0, /* Use standad mode (100Khz) */
	80	};
	81	OCP_SYSFS_IIC_DATA()
	82
	83	struct ocp_def core_ocp[] = {
	84	{ .vendor = OCP_VENDOR_IBM,
	85	.function = OCP_FUNC_OPB,
	86	.index = 0,
	87	.paddr = 0xEF600000,
	88	.irq = OCP_IRQ_NA,
	89	.pm = OCP_CPM_NA,
	90	},
	91	{ .vendor = OCP_VENDOR_IBM,
	92	.function = OCP_FUNC_16550,
	93	.index = 0,
	94	.paddr = UART0_IO_BASE,
	95	.irq = UART0_INT,
	96	.pm = IBM_CPM_UART0
	97	},
	98	{ .vendor = OCP_VENDOR_IBM,
	99	.function = OCP_FUNC_16550,
	100	.index = 1,
	101	.paddr = UART1_IO_BASE,
	102	.irq = UART1_INT,
	103	.pm = IBM_CPM_UART1
	104	},
	105	{ .vendor = OCP_VENDOR_IBM,
	106	.function = OCP_FUNC_IIC,
	107	.paddr = 0xEF600500,
	108	.irq = 2,
	109	.pm = IBM_CPM_IIC0,
	110	.additions = &ibmnp405h_iic0_def,
	111	.show = &ocp_show_iic_data
	112	},
	113	{ .vendor = OCP_VENDOR_IBM,
	114	.function = OCP_FUNC_GPIO,
	115	.paddr = 0xEF600700,
	116	.irq = OCP_IRQ_NA,
	117	.pm = IBM_CPM_GPIO0
	118	},
	119	{ .vendor = OCP_VENDOR_IBM,
	120	.function = OCP_FUNC_MAL,
	121	.paddr = OCP_PADDR_NA,
	122	.irq = OCP_IRQ_NA,
	123	.pm = OCP_CPM_NA,
	124	.additions = &ibmnp405h_mal0_def,
	125	.show = &ocp_show_mal_data,
	126	},
	127	{ .vendor = OCP_VENDOR_IBM,
	128	.function = OCP_FUNC_EMAC,
	129	.index = 0,
	130	.paddr = EMAC0_BASE,
	131	.irq = 37,
	132	.pm = IBM_CPM_EMAC0,
	133	.additions = &ibmnp405h_emac0_def,
	134	.show = &ocp_show_emac_data,
	135	},
	136	{ .vendor = OCP_VENDOR_IBM,
	137	.function = OCP_FUNC_EMAC,
	138	.index = 1,
139	.paddr = 0xEF600900,
140	.irq = 38,
141	.pm = IBM_CPM_EMAC1,
142	.additions = &ibmnp405h_emac1_def,
143	.show = &ocp_show_emac_data,
144	},
145	{ .vendor = OCP_VENDOR_IBM,
146	.function = OCP_FUNC_EMAC,
147	.index = 2,
148	.paddr = 0xEF600a00,
149	.irq = 39,
150	.pm = IBM_CPM_EMAC2,
151	.additions = &ibmnp405h_emac2_def,
152	.show = &ocp_show_emac_data,
153	},
154	{ .vendor = OCP_VENDOR_IBM,
155	.function = OCP_FUNC_EMAC,
156	.index = 3,
157	.paddr = 0xEF600b00,
158	.irq = 40,
159	.pm = IBM_CPM_EMAC3,
160	.additions = &ibmnp405h_emac3_def,
161	.show = &ocp_show_emac_data,
162	},
163	{ .vendor = OCP_VENDOR_IBM,
164	.function = OCP_FUNC_ZMII,
165	.paddr = 0xEF600C10,
166	.irq = OCP_IRQ_NA,
167	.pm = OCP_CPM_NA,
168	},
169	{ .vendor = OCP_VENDOR_INVALID
170	}
171	};