Commit | Line | Data |
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1da177e4 | 1 | /* |
1da177e4 LT |
2 | * PPC440SP definitions |
3 | * | |
4 | * Matt Porter <mporter@kernel.crashing.org> | |
5 | * | |
6 | * Copyright 2004-2005 MontaVista Software, Inc. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify it | |
9 | * under the terms of the GNU General Public License as published by the | |
10 | * Free Software Foundation; either version 2 of the License, or (at your | |
11 | * option) any later version. | |
12 | */ | |
13 | ||
14 | #ifdef __KERNEL__ | |
15 | #ifndef __PPC_PLATFORMS_IBM440SP_H | |
16 | #define __PPC_PLATFORMS_IBM440SP_H | |
17 | ||
1da177e4 LT |
18 | |
19 | #include <asm/ibm44x.h> | |
20 | ||
21 | /* UART */ | |
22 | #define PPC440SP_UART0_ADDR 0x00000001f0000200ULL | |
23 | #define PPC440SP_UART1_ADDR 0x00000001f0000300ULL | |
24 | #define PPC440SP_UART2_ADDR 0x00000001f0000600ULL | |
25 | #define UART0_INT 0 | |
26 | #define UART1_INT 1 | |
27 | #define UART2_INT 2 | |
28 | ||
29 | /* Clock and Power Management */ | |
30 | #define IBM_CPM_IIC0 0x80000000 /* IIC interface */ | |
31 | #define IBM_CPM_IIC1 0x40000000 /* IIC interface */ | |
32 | #define IBM_CPM_PCI 0x20000000 /* PCI bridge */ | |
33 | #define IBM_CPM_CPU 0x02000000 /* processor core */ | |
34 | #define IBM_CPM_DMA 0x01000000 /* DMA controller */ | |
35 | #define IBM_CPM_BGO 0x00800000 /* PLB to OPB bus arbiter */ | |
36 | #define IBM_CPM_BGI 0x00400000 /* OPB to PLB bridge */ | |
37 | #define IBM_CPM_EBC 0x00200000 /* External Bux Controller */ | |
38 | #define IBM_CPM_EBM 0x00100000 /* Ext Bus Master Interface */ | |
39 | #define IBM_CPM_DMC 0x00080000 /* SDRAM peripheral controller */ | |
40 | #define IBM_CPM_PLB 0x00040000 /* PLB bus arbiter */ | |
41 | #define IBM_CPM_SRAM 0x00020000 /* SRAM memory controller */ | |
42 | #define IBM_CPM_PPM 0x00002000 /* PLB Performance Monitor */ | |
43 | #define IBM_CPM_UIC1 0x00001000 /* Universal Interrupt Controller */ | |
44 | #define IBM_CPM_GPIO0 0x00000800 /* General Purpose IO (??) */ | |
45 | #define IBM_CPM_GPT 0x00000400 /* General Purpose Timers */ | |
46 | #define IBM_CPM_UART0 0x00000200 /* serial port 0 */ | |
47 | #define IBM_CPM_UART1 0x00000100 /* serial port 1 */ | |
48 | #define IBM_CPM_UART2 0x00000100 /* serial port 1 */ | |
49 | #define IBM_CPM_UIC0 0x00000080 /* Universal Interrupt Controller */ | |
50 | #define IBM_CPM_TMRCLK 0x00000040 /* CPU timers */ | |
51 | #define IBM_CPM_EMAC0 0x00000020 /* EMAC 0 */ | |
52 | ||
53 | #define DFLT_IBM4xx_PM ~(IBM_CPM_UIC | IBM_CPM_UIC1 | IBM_CPM_CPU \ | |
54 | | IBM_CPM_EBC | IBM_CPM_SRAM | IBM_CPM_BGO \ | |
55 | | IBM_CPM_EBM | IBM_CPM_PLB | IBM_CPM_OPB \ | |
56 | | IBM_CPM_TMRCLK | IBM_CPM_DMA | IBM_CPM_PCI \ | |
57 | | IBM_CPM_TAHOE0 | IBM_CPM_TAHOE1 \ | |
58 | | IBM_CPM_EMAC0 | IBM_CPM_EMAC1 \ | |
59 | | IBM_CPM_EMAC2 | IBM_CPM_EMAC3 ) | |
60 | #endif /* __PPC_PLATFORMS_IBM440SP_H */ | |
61 | #endif /* __KERNEL__ */ |