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1da177e4 LT |
1 | /* |
2 | * | |
3 | * Copyright 2000-2001 MontaVista Software Inc. | |
4 | * Original author: Armin Kuster akuster@mvista.com | |
5 | * | |
6 | * Module name: ibm405gp.c | |
7 | * | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify it | |
10 | * under the terms of the GNU General Public License as published by the | |
11 | * Free Software Foundation; either version 2 of the License, or (at your | |
12 | * option) any later version. | |
13 | * | |
14 | */ | |
15 | ||
16 | #include <linux/config.h> | |
17 | #include <linux/init.h> | |
18 | #include <linux/smp.h> | |
19 | #include <linux/threads.h> | |
20 | #include <linux/param.h> | |
21 | #include <linux/string.h> | |
22 | #include <platforms/4xx/ibm405gp.h> | |
23 | #include <asm/ibm4xx.h> | |
24 | #include <asm/ocp.h> | |
25 | #include <asm/ppc4xx_pic.h> | |
26 | ||
27 | static struct ocp_func_emac_data ibm405gp_emac0_def = { | |
28 | .rgmii_idx = -1, /* No RGMII */ | |
29 | .rgmii_mux = -1, /* No RGMII */ | |
30 | .zmii_idx = -1, /* ZMII device index */ | |
31 | .zmii_mux = 0, /* ZMII input of this EMAC */ | |
32 | .mal_idx = 0, /* MAL device index */ | |
33 | .mal_rx_chan = 0, /* MAL rx channel number */ | |
34 | .mal_tx_chan = 0, /* MAL tx channel number */ | |
35 | .wol_irq = 9, /* WOL interrupt number */ | |
36 | .mdio_idx = -1, /* No shared MDIO */ | |
37 | .tah_idx = -1, /* No TAH */ | |
38 | }; | |
39 | OCP_SYSFS_EMAC_DATA() | |
40 | ||
41 | static struct ocp_func_mal_data ibm405gp_mal0_def = { | |
42 | .num_tx_chans = 1, /* Number of TX channels */ | |
43 | .num_rx_chans = 1, /* Number of RX channels */ | |
44 | .txeob_irq = 11, /* TX End Of Buffer IRQ */ | |
45 | .rxeob_irq = 12, /* RX End Of Buffer IRQ */ | |
46 | .txde_irq = 13, /* TX Descriptor Error IRQ */ | |
47 | .rxde_irq = 14, /* RX Descriptor Error IRQ */ | |
48 | .serr_irq = 10, /* MAL System Error IRQ */ | |
3a0a401b | 49 | .dcr_base = DCRN_MAL_BASE /* MAL0_CFG DCR number */ |
1da177e4 LT |
50 | }; |
51 | OCP_SYSFS_MAL_DATA() | |
52 | ||
53 | static struct ocp_func_iic_data ibm405gp_iic0_def = { | |
54 | .fast_mode = 0, /* Use standad mode (100Khz) */ | |
55 | }; | |
56 | OCP_SYSFS_IIC_DATA() | |
57 | ||
58 | struct ocp_def core_ocp[] = { | |
59 | { .vendor = OCP_VENDOR_IBM, | |
60 | .function = OCP_FUNC_OPB, | |
61 | .index = 0, | |
62 | .paddr = 0xEF600000, | |
63 | .irq = OCP_IRQ_NA, | |
64 | .pm = OCP_CPM_NA, | |
65 | }, | |
66 | { .vendor = OCP_VENDOR_IBM, | |
67 | .function = OCP_FUNC_16550, | |
68 | .index = 0, | |
69 | .paddr = UART0_IO_BASE, | |
70 | .irq = UART0_INT, | |
71 | .pm = IBM_CPM_UART0 | |
72 | }, | |
73 | { .vendor = OCP_VENDOR_IBM, | |
74 | .function = OCP_FUNC_16550, | |
75 | .index = 1, | |
76 | .paddr = UART1_IO_BASE, | |
77 | .irq = UART1_INT, | |
78 | .pm = IBM_CPM_UART1 | |
79 | }, | |
80 | { .vendor = OCP_VENDOR_IBM, | |
81 | .function = OCP_FUNC_IIC, | |
82 | .paddr = 0xEF600500, | |
83 | .irq = 2, | |
84 | .pm = IBM_CPM_IIC0, | |
85 | .additions = &ibm405gp_iic0_def, | |
86 | .show = &ocp_show_iic_data, | |
87 | }, | |
88 | { .vendor = OCP_VENDOR_IBM, | |
89 | .function = OCP_FUNC_GPIO, | |
90 | .paddr = 0xEF600700, | |
91 | .irq = OCP_IRQ_NA, | |
92 | .pm = IBM_CPM_GPIO0 | |
93 | }, | |
94 | { .vendor = OCP_VENDOR_IBM, | |
95 | .function = OCP_FUNC_MAL, | |
96 | .paddr = OCP_PADDR_NA, | |
97 | .irq = OCP_IRQ_NA, | |
98 | .pm = OCP_CPM_NA, | |
99 | .additions = &ibm405gp_mal0_def, | |
100 | .show = &ocp_show_mal_data, | |
101 | }, | |
102 | { .vendor = OCP_VENDOR_IBM, | |
103 | .function = OCP_FUNC_EMAC, | |
104 | .index = 0, | |
105 | .paddr = EMAC0_BASE, | |
106 | .irq = 15, | |
107 | .pm = IBM_CPM_EMAC0, | |
108 | .additions = &ibm405gp_emac0_def, | |
109 | .show = &ocp_show_emac_data, | |
110 | }, | |
111 | { .vendor = OCP_VENDOR_INVALID | |
112 | } | |
113 | }; | |
114 | ||
115 | /* Polarity and triggering settings for internal interrupt sources */ | |
116 | struct ppc4xx_uic_settings ppc4xx_core_uic_cfg[] __initdata = { | |
117 | { .polarity = 0xffffff80, | |
118 | .triggering = 0x10000000, | |
119 | .ext_irq_mask = 0x0000007f, /* IRQ0 - IRQ6 */ | |
120 | } | |
121 | }; |