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[PATCH] UML: add generic BUG support
[linux-2.6-block.git] / arch / ppc / kernel / traps.c
CommitLineData
1da177e4 1/*
1da177e4
LT		 2 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version
7 * 2 of the License, or (at your option) any later version.
8 *
9 * Modified by Cort Dougan (cort@cs.nmt.edu)
10 * and Paul Mackerras (paulus@cs.anu.edu.au)
11 */
12
13/*
14 * This file handles the architecture-dependent parts of hardware exceptions
15 */
16
17#include <linux/errno.h>
18#include <linux/sched.h>
19#include <linux/kernel.h>
20#include <linux/mm.h>
21#include <linux/stddef.h>
22#include <linux/unistd.h>
23#include <linux/ptrace.h>
24#include <linux/slab.h>
25#include <linux/user.h>
26#include <linux/a.out.h>
27#include <linux/interrupt.h>
1da177e4
LT		 28#include <linux/init.h>
29#include <linux/module.h>
30#include <linux/prctl.h>
31
32#include <asm/pgtable.h>
33#include <asm/uaccess.h>
34#include <asm/system.h>
35#include <asm/io.h>
36#include <asm/reg.h>
37#include <asm/xmon.h>
f7f6f4fe 38#include <asm/pmc.h>
1da177e4
LT		 39
40#ifdef CONFIG_XMON
fd582ec8
PM		 41extern int xmon_bpt(struct pt_regs *regs);
42extern int xmon_sstep(struct pt_regs *regs);
43extern int xmon_iabr_match(struct pt_regs *regs);
44extern int xmon_dabr_match(struct pt_regs *regs);
45
7b007de8 46int (*debugger)(struct pt_regs *regs) = xmon;
1da177e4
LT		 47int (*debugger_bpt)(struct pt_regs *regs) = xmon_bpt;
48int (*debugger_sstep)(struct pt_regs *regs) = xmon_sstep;
49int (*debugger_iabr_match)(struct pt_regs *regs) = xmon_iabr_match;
50int (*debugger_dabr_match)(struct pt_regs *regs) = xmon_dabr_match;
51void (*debugger_fault_handler)(struct pt_regs *regs);
52#else
53#ifdef CONFIG_KGDB
7b007de8 54int (*debugger)(struct pt_regs *regs);
1da177e4
LT		 55int (*debugger_bpt)(struct pt_regs *regs);
56int (*debugger_sstep)(struct pt_regs *regs);
57int (*debugger_iabr_match)(struct pt_regs *regs);
58int (*debugger_dabr_match)(struct pt_regs *regs);
59void (*debugger_fault_handler)(struct pt_regs *regs);
60#else
61#define debugger(regs) do { } while (0)
62#define debugger_bpt(regs) 0
63#define debugger_sstep(regs) 0
64#define debugger_iabr_match(regs) 0
65#define debugger_dabr_match(regs) 0
66#define debugger_fault_handler ((void (*)(struct pt_regs *))0)
67#endif
68#endif
69
70/*
71 * Trap & Exception support
72 */
73
74DEFINE_SPINLOCK(die_lock);
75
dc1c1ca3 76int die(const char * str, struct pt_regs * fp, long err)
1da177e4
LT		 77{
78 static int die_counter;
79 int nl = 0;
80 console_verbose();
81 spin_lock_irq(&die_lock);
1da177e4
LT		 82 printk("Oops: %s, sig: %ld [#%d]\n", str, err, ++die_counter);
83#ifdef CONFIG_PREEMPT
84 printk("PREEMPT ");
85 nl = 1;
86#endif
87#ifdef CONFIG_SMP
88 printk("SMP NR_CPUS=%d ", NR_CPUS);
89 nl = 1;
90#endif
91 if (nl)
92 printk("\n");
93 show_regs(fp);
94 spin_unlock_irq(&die_lock);
95 /* do_exit() should take care of panic'ing from an interrupt
96 * context so we don't handle it here
97 */
98 do_exit(err);
99}
100
101void _exception(int signr, struct pt_regs *regs, int code, unsigned long addr)
102{
103 siginfo_t info;
104
105 if (!user_mode(regs)) {
106 debugger(regs);
107 die("Exception in kernel mode", regs, signr);
108 }
109 info.si_signo = signr;
110 info.si_errno = 0;
111 info.si_code = code;
112 info.si_addr = (void __user *) addr;
113 force_sig_info(signr, &info, current);
bb0bb3b6
PM		 114
115 /*
116 * Init gets no signals that it doesn't have a handler for.
117 * That's all very well, but if it has caused a synchronous
118 * exception and we ignore the resulting signal, it will just
119 * generate the same exception over and over again and we get
120 * nowhere. Better to kill it and let the kernel panic.
121 */
f400e198 122 if (is_init(current)) {
bb0bb3b6
PM		 123 __sighandler_t handler;
124
125 spin_lock_irq(&current->sighand->siglock);
126 handler = current->sighand->action[signr-1].sa.sa_handler;
127 spin_unlock_irq(&current->sighand->siglock);
128 if (handler == SIG_DFL) {
129 /* init has generated a synchronous exception
130 and it doesn't have a handler for the signal */
131 printk(KERN_CRIT "init has generated signal %d "
132 "but has no handler for it\n", signr);
133 do_exit(signr);
134 }
135 }
1da177e4
LT		 136}
137
138/*
139 * I/O accesses can cause machine checks on powermacs.
140 * Check if the NIP corresponds to the address of a sync
141 * instruction for which there is an entry in the exception
142 * table.
143 * Note that the 601 only takes a machine check on TEA
144 * (transfer error ack) signal assertion, and does not
145 * set any of the top 16 bits of SRR1.
146 * -- paulus.
147 */
148static inline int check_io_access(struct pt_regs *regs)
149{
a7fdd90b 150#if defined CONFIG_8xx
1da177e4
LT		 151 unsigned long msr = regs->msr;
152 const struct exception_table_entry *entry;
153 unsigned int *nip = (unsigned int *)regs->nip;
154
155 if (((msr & 0xffff0000) == 0 || (msr & (0x80000 | 0x40000)))
156 && (entry = search_exception_tables(regs->nip)) != NULL) {
157 /*
158 * Check that it's a sync instruction, or somewhere
159 * in the twi; isync; nop sequence that inb/inw/inl uses.
160 * As the address is in the exception table
161 * we should be able to read the instr there.
162 * For the debug message, we look at the preceding
163 * load or store.
164 */
165 if (*nip == 0x60000000) /* nop */
166 nip -= 2;
167 else if (*nip == 0x4c00012c) /* isync */
168 --nip;
55b6332e
MT		 169 /* eieio from I/O string functions */
170 else if ((*nip) == 0x7c0006ac || *(nip+1) == 0x7c0006ac)
171 nip += 2;
172 if (*nip == 0x7c0004ac || (*nip >> 26) == 3 ||
173 (*(nip+1) >> 26) == 3) {
1da177e4
LT		 174 /* sync or twi */
175 unsigned int rb;
176
177 --nip;
178 rb = (*nip >> 11) & 0x1f;
179 printk(KERN_DEBUG "%s bad port %lx at %p\n",
180 (*nip & 0x100)? "OUT to": "IN from",
181 regs->gpr[rb] - _IO_BASE, nip);
182 regs->msr |= MSR_RI;
183 regs->nip = entry->fixup;
184 return 1;
185 }
186 }
a7fdd90b 187#endif /* CONFIG_8xx */
1da177e4
LT		 188 return 0;
189}
190
191#if defined(CONFIG_4xx) || defined(CONFIG_BOOKE)
192/* On 4xx, the reason for the machine check or program exception
193 is in the ESR. */
194#define get_reason(regs) ((regs)->dsisr)
33d9e9b5 195#ifndef CONFIG_FSL_BOOKE
1da177e4
LT		 196#define get_mc_reason(regs) ((regs)->dsisr)
197#else
198#define get_mc_reason(regs) (mfspr(SPRN_MCSR))
199#endif
443a848c 200#define REASON_FP ESR_FP
33d9e9b5 201#define REASON_ILLEGAL (ESR_PIL | ESR_PUO)
1da177e4
LT		 202#define REASON_PRIVILEGED ESR_PPR
203#define REASON_TRAP ESR_PTR
204
205/* single-step stuff */
206#define single_stepping(regs) (current->thread.dbcr0 & DBCR0_IC)
207#define clear_single_step(regs) (current->thread.dbcr0 &= ~DBCR0_IC)
208
209#else
210/* On non-4xx, the reason for the machine check or program
211 exception is in the MSR. */
212#define get_reason(regs) ((regs)->msr)
213#define get_mc_reason(regs) ((regs)->msr)
214#define REASON_FP 0x100000
215#define REASON_ILLEGAL 0x80000
216#define REASON_PRIVILEGED 0x40000
217#define REASON_TRAP 0x20000
218
219#define single_stepping(regs) ((regs)->msr & MSR_SE)
220#define clear_single_step(regs) ((regs)->msr &= ~MSR_SE)
221#endif
222
223/*
224 * This is "fall-back" implementation for configurations
225 * which don't provide platform-specific machine check info
226 */
227void __attribute__ ((weak))
228platform_machine_check(struct pt_regs *regs)
229{
230}
231
dc1c1ca3 232void machine_check_exception(struct pt_regs *regs)
1da177e4
LT		 233{
234 unsigned long reason = get_mc_reason(regs);
235
236 if (user_mode(regs)) {
237 regs->msr |= MSR_RI;
238 _exception(SIGBUS, regs, BUS_ADRERR, regs->nip);
239 return;
240 }
241
242#if defined(CONFIG_8xx) && defined(CONFIG_PCI)
243 /* the qspan pci read routines can cause machine checks -- Cort */
244 bad_page_fault(regs, regs->dar, SIGBUS);
245 return;
246#endif
247
248 if (debugger_fault_handler) {
249 debugger_fault_handler(regs);
250 regs->msr |= MSR_RI;
251 return;
252 }
253
254 if (check_io_access(regs))
255 return;
256
257#if defined(CONFIG_4xx) && !defined(CONFIG_440A)
258 if (reason & ESR_IMCP) {
259 printk("Instruction");
260 mtspr(SPRN_ESR, reason & ~ESR_IMCP);
261 } else
262 printk("Data");
263 printk(" machine check in kernel mode.\n");
264#elif defined(CONFIG_440A)
265 printk("Machine check in kernel mode.\n");
266 if (reason & ESR_IMCP){
267 printk("Instruction Synchronous Machine Check exception\n");
268 mtspr(SPRN_ESR, reason & ~ESR_IMCP);
269 }
270 else {
271 u32 mcsr = mfspr(SPRN_MCSR);
272 if (mcsr & MCSR_IB)
273 printk("Instruction Read PLB Error\n");
274 if (mcsr & MCSR_DRB)
275 printk("Data Read PLB Error\n");
276 if (mcsr & MCSR_DWB)
277 printk("Data Write PLB Error\n");
278 if (mcsr & MCSR_TLBP)
279 printk("TLB Parity Error\n");
280 if (mcsr & MCSR_ICP){
281 flush_instruction_cache();
282 printk("I-Cache Parity Error\n");
283 }
284 if (mcsr & MCSR_DCSP)
285 printk("D-Cache Search Parity Error\n");
286 if (mcsr & MCSR_DCFP)
287 printk("D-Cache Flush Parity Error\n");
288 if (mcsr & MCSR_IMPE)
289 printk("Machine Check exception is imprecise\n");
290
291 /* Clear MCSR */
292 mtspr(SPRN_MCSR, mcsr);
293 }
294#elif defined (CONFIG_E500)
295 printk("Machine check in kernel mode.\n");
296 printk("Caused by (from MCSR=%lx): ", reason);
297
298 if (reason & MCSR_MCP)
299 printk("Machine Check Signal\n");
300 if (reason & MCSR_ICPERR)
301 printk("Instruction Cache Parity Error\n");
302 if (reason & MCSR_DCP_PERR)
303 printk("Data Cache Push Parity Error\n");
304 if (reason & MCSR_DCPERR)
305 printk("Data Cache Parity Error\n");
306 if (reason & MCSR_GL_CI)
307 printk("Guarded Load or Cache-Inhibited stwcx.\n");
308 if (reason & MCSR_BUS_IAERR)
309 printk("Bus - Instruction Address Error\n");
310 if (reason & MCSR_BUS_RAERR)
311 printk("Bus - Read Address Error\n");
312 if (reason & MCSR_BUS_WAERR)
313 printk("Bus - Write Address Error\n");
314 if (reason & MCSR_BUS_IBERR)
315 printk("Bus - Instruction Data Error\n");
316 if (reason & MCSR_BUS_RBERR)
317 printk("Bus - Read Data Bus Error\n");
318 if (reason & MCSR_BUS_WBERR)
d6a0005c 319 printk("Bus - Write Data Bus Error\n");
1da177e4
LT		 320 if (reason & MCSR_BUS_IPERR)
321 printk("Bus - Instruction Parity Error\n");
322 if (reason & MCSR_BUS_RPERR)
323 printk("Bus - Read Parity Error\n");
33d9e9b5
KG		 324#elif defined (CONFIG_E200)
325 printk("Machine check in kernel mode.\n");
326 printk("Caused by (from MCSR=%lx): ", reason);
327
328 if (reason & MCSR_MCP)
329 printk("Machine Check Signal\n");
330 if (reason & MCSR_CP_PERR)
331 printk("Cache Push Parity Error\n");
332 if (reason & MCSR_CPERR)
333 printk("Cache Parity Error\n");
334 if (reason & MCSR_EXCP_ERR)
335 printk("ISI, ITLB, or Bus Error on first instruction fetch for an exception handler\n");
336 if (reason & MCSR_BUS_IRERR)
337 printk("Bus - Read Bus Error on instruction fetch\n");
338 if (reason & MCSR_BUS_DRERR)
339 printk("Bus - Read Bus Error on data load\n");
340 if (reason & MCSR_BUS_WRERR)
341 printk("Bus - Write Bus Error on buffered store or cache line push\n");
342#else /* !CONFIG_4xx && !CONFIG_E500 && !CONFIG_E200 */
1da177e4
LT		 343 printk("Machine check in kernel mode.\n");
344 printk("Caused by (from SRR1=%lx): ", reason);
345 switch (reason & 0x601F0000) {
346 case 0x80000:
347 printk("Machine check signal\n");
348 break;
349 case 0: /* for 601 */
350 case 0x40000:
351 case 0x140000: /* 7450 MSS error and TEA */
352 printk("Transfer error ack signal\n");
353 break;
354 case 0x20000:
355 printk("Data parity error signal\n");
356 break;
357 case 0x10000:
358 printk("Address parity error signal\n");
359 break;
360 case 0x20000000:
361 printk("L1 Data Cache error\n");
362 break;
363 case 0x40000000:
364 printk("L1 Instruction Cache error\n");
365 break;
366 case 0x00100000:
367 printk("L2 data cache parity error\n");
368 break;
369 default:
370 printk("Unknown values in msr\n");
371 }
372#endif /* CONFIG_4xx */
373
374 /*
375 * Optional platform-provided routine to print out
376 * additional info, e.g. bus error registers.
377 */
378 platform_machine_check(regs);
379
380 debugger(regs);
381 die("machine check", regs, SIGBUS);
382}
383
384void SMIException(struct pt_regs *regs)
385{
386 debugger(regs);
387#if !(defined(CONFIG_XMON) || defined(CONFIG_KGDB))
388 show_regs(regs);
389 panic("System Management Interrupt");
390#endif
391}
392
dc1c1ca3 393void unknown_exception(struct pt_regs *regs)
1da177e4
LT		 394{
395 printk("Bad trap at PC: %lx, MSR: %lx, vector=%lx %s\n",
396 regs->nip, regs->msr, regs->trap, print_tainted());
397 _exception(SIGTRAP, regs, 0, 0);
398}
399
dc1c1ca3 400void instruction_breakpoint_exception(struct pt_regs *regs)
1da177e4
LT		 401{
402 if (debugger_iabr_match(regs))
403 return;
404 _exception(SIGTRAP, regs, TRAP_BRKPT, 0);
405}
406
407void RunModeException(struct pt_regs *regs)
408{
409 _exception(SIGTRAP, regs, 0, 0);
410}
411
412/* Illegal instruction emulation support. Originally written to
413 * provide the PVR to user applications using the mfspr rd, PVR.
414 * Return non-zero if we can't emulate, or -EFAULT if the associated
415 * memory access caused an access fault. Return zero on success.
416 *
417 * There are a couple of ways to do this, either "decode" the instruction
418 * or directly match lots of bits. In this case, matching lots of
419 * bits is faster and easier.
420 *
421 */
422#define INST_MFSPR_PVR 0x7c1f42a6
423#define INST_MFSPR_PVR_MASK 0xfc1fffff
424
425#define INST_DCBA 0x7c0005ec
426#define INST_DCBA_MASK 0x7c0007fe
427
428#define INST_MCRXR 0x7c000400
429#define INST_MCRXR_MASK 0x7c0007fe
430
431#define INST_STRING 0x7c00042a
432#define INST_STRING_MASK 0x7c0007fe
433#define INST_STRING_GEN_MASK 0x7c00067e
434#define INST_LSWI 0x7c0004aa
435#define INST_LSWX 0x7c00042a
436#define INST_STSWI 0x7c0005aa
437#define INST_STSWX 0x7c00052a
438
439static int emulate_string_inst(struct pt_regs *regs, u32 instword)
440{
441 u8 rT = (instword >> 21) & 0x1f;
442 u8 rA = (instword >> 16) & 0x1f;
443 u8 NB_RB = (instword >> 11) & 0x1f;
444 u32 num_bytes;
91de1fff 445 unsigned long EA;
1da177e4
LT		 446 int pos = 0;
447
448 /* Early out if we are an invalid form of lswx */
449 if ((instword & INST_STRING_MASK) == INST_LSWX)
92b4dc16 450 if ((rT == rA) || (rT == NB_RB))
1da177e4
LT		 451 return -EINVAL;
452
453 EA = (rA == 0) ? 0 : regs->gpr[rA];
454
455 switch (instword & INST_STRING_MASK) {
456 case INST_LSWX:
457 case INST_STSWX:
458 EA += NB_RB;
459 num_bytes = regs->xer & 0x7f;
460 break;
461 case INST_LSWI:
462 case INST_STSWI:
463 num_bytes = (NB_RB == 0) ? 32 : NB_RB;
464 break;
465 default:
466 return -EINVAL;
467 }
468
469 while (num_bytes != 0)
470 {
471 u8 val;
472 u32 shift = 8 * (3 - (pos & 0x3));
473
474 switch ((instword & INST_STRING_MASK)) {
475 case INST_LSWX:
476 case INST_LSWI:
477 if (get_user(val, (u8 __user *)EA))
478 return -EFAULT;
479 /* first time updating this reg,
480 * zero it out */
481 if (pos == 0)
482 regs->gpr[rT] = 0;
483 regs->gpr[rT] |= val << shift;
484 break;
485 case INST_STSWI:
486 case INST_STSWX:
487 val = regs->gpr[rT] >> shift;
488 if (put_user(val, (u8 __user *)EA))
489 return -EFAULT;
490 break;
491 }
492 /* move EA to next address */
493 EA += 1;
494 num_bytes--;
495
496 /* manage our position within the register */
497 if (++pos == 4) {
498 pos = 0;
499 if (++rT == 32)
500 rT = 0;
501 }
502 }
503
504 return 0;
505}
506
507static int emulate_instruction(struct pt_regs *regs)
508{
509 u32 instword;
510 u32 rd;
511
512 if (!user_mode(regs))
513 return -EINVAL;
514 CHECK_FULL_REGS(regs);
515
516 if (get_user(instword, (u32 __user *)(regs->nip)))
517 return -EFAULT;
518
519 /* Emulate the mfspr rD, PVR.
520 */
521 if ((instword & INST_MFSPR_PVR_MASK) == INST_MFSPR_PVR) {
522 rd = (instword >> 21) & 0x1f;
523 regs->gpr[rd] = mfspr(SPRN_PVR);
524 return 0;
525 }
526
527 /* Emulating the dcba insn is just a no-op. */
528 if ((instword & INST_DCBA_MASK) == INST_DCBA)
529 return 0;
530
531 /* Emulate the mcrxr insn. */
532 if ((instword & INST_MCRXR_MASK) == INST_MCRXR) {
533 int shift = (instword >> 21) & 0x1c;
534 unsigned long msk = 0xf0000000UL >> shift;
535
536 regs->ccr = (regs->ccr & ~msk) | ((regs->xer >> shift) & msk);
537 regs->xer &= ~0xf0000000UL;
538 return 0;
539 }
540
541 /* Emulate load/store string insn. */
542 if ((instword & INST_STRING_GEN_MASK) == INST_STRING)
543 return emulate_string_inst(regs, instword);
544
545 return -EINVAL;
546}
547
548/*
549 * After we have successfully emulated an instruction, we have to
550 * check if the instruction was being single-stepped, and if so,
551 * pretend we got a single-step exception. This was pointed out
552 * by Kumar Gala. -- paulus
553 */
554static void emulate_single_step(struct pt_regs *regs)
555{
556 if (single_stepping(regs)) {
557 clear_single_step(regs);
558 _exception(SIGTRAP, regs, TRAP_TRACE, 0);
559 }
560}
561
562/*
563 * Look through the list of trap instructions that are used for BUG(),
564 * BUG_ON() and WARN_ON() and see if we hit one. At this point we know
565 * that the exception was caused by a trap instruction of some kind.
566 * Returns 1 if we should continue (i.e. it was a WARN_ON) or 0
567 * otherwise.
568 */
569extern struct bug_entry __start___bug_table[], __stop___bug_table[];
570
571#ifndef CONFIG_MODULES
572#define module_find_bug(x) NULL
573#endif
574
25433b12 575struct bug_entry *find_bug(unsigned long bugaddr)
1da177e4
LT		 576{
577 struct bug_entry *bug;
578
579 for (bug = __start___bug_table; bug < __stop___bug_table; ++bug)
580 if (bugaddr == bug->bug_addr)
581 return bug;
582 return module_find_bug(bugaddr);
583}
584
585int check_bug_trap(struct pt_regs *regs)
586{
587 struct bug_entry *bug;
588 unsigned long addr;
589
590 if (regs->msr & MSR_PR)
591 return 0; /* not in kernel */
592 addr = regs->nip; /* address of trap instruction */
593 if (addr < PAGE_OFFSET)
594 return 0;
595 bug = find_bug(regs->nip);
596 if (bug == NULL)
597 return 0;
598 if (bug->line & BUG_WARNING_TRAP) {
599 /* this is a WARN_ON rather than BUG/BUG_ON */
600#ifdef CONFIG_XMON
9122ee33 601 xmon_printf(KERN_ERR "Badness in %s at %s:%ld\n",
1da177e4
LT		 602 bug->function, bug->file,
603 bug->line & ~BUG_WARNING_TRAP);
604#endif /* CONFIG_XMON */
9122ee33 605 printk(KERN_ERR "Badness in %s at %s:%ld\n",
1da177e4
LT		 606 bug->function, bug->file,
607 bug->line & ~BUG_WARNING_TRAP);
608 dump_stack();
609 return 1;
610 }
611#ifdef CONFIG_XMON
9122ee33 612 xmon_printf(KERN_CRIT "kernel BUG in %s at %s:%ld!\n",
1da177e4
LT		 613 bug->function, bug->file, bug->line);
614 xmon(regs);
615#endif /* CONFIG_XMON */
9122ee33 616 printk(KERN_CRIT "kernel BUG in %s at %s:%ld!\n",
1da177e4
LT		 617 bug->function, bug->file, bug->line);
618
619 return 0;
620}
621
dc1c1ca3 622void program_check_exception(struct pt_regs *regs)
1da177e4
LT		 623{
624 unsigned int reason = get_reason(regs);
625 extern int do_mathemu(struct pt_regs *regs);
626
627#ifdef CONFIG_MATH_EMULATION
628 /* (reason & REASON_ILLEGAL) would be the obvious thing here,
629 * but there seems to be a hardware bug on the 405GP (RevD)
630 * that means ESR is sometimes set incorrectly - either to
631 * ESR_DST (!?) or 0. In the process of chasing this with the
632 * hardware people - not sure if it can happen on any illegal
633 * instruction or only on FP instructions, whether there is a
634 * pattern to occurences etc. -dgibson 31/Mar/2003 */
635 if (!(reason & REASON_TRAP) && do_mathemu(regs) == 0) {
636 emulate_single_step(regs);
637 return;
638 }
639#endif /* CONFIG_MATH_EMULATION */
640
641 if (reason & REASON_FP) {
642 /* IEEE FP exception */
643 int code = 0;
644 u32 fpscr;
645
646 /* We must make sure the FP state is consistent with
647 * our MSR_FP in regs
648 */
649 preempt_disable();
650 if (regs->msr & MSR_FP)
651 giveup_fpu(current);
652 preempt_enable();
653
25c8a78b 654 fpscr = current->thread.fpscr.val;
1da177e4
LT		 655 fpscr &= fpscr << 22; /* mask summary bits with enables */
656 if (fpscr & FPSCR_VX)
657 code = FPE_FLTINV;
658 else if (fpscr & FPSCR_OX)
659 code = FPE_FLTOVF;
660 else if (fpscr & FPSCR_UX)
661 code = FPE_FLTUND;
662 else if (fpscr & FPSCR_ZX)
663 code = FPE_FLTDIV;
664 else if (fpscr & FPSCR_XX)
665 code = FPE_FLTRES;
666 _exception(SIGFPE, regs, code, regs->nip);
667 return;
668 }
669
670 if (reason & REASON_TRAP) {
671 /* trap exception */
672 if (debugger_bpt(regs))
673 return;
674 if (check_bug_trap(regs)) {
675 regs->nip += 4;
676 return;
677 }
678 _exception(SIGTRAP, regs, TRAP_BRKPT, 0);
679 return;
680 }
681
682 /* Try to emulate it if we should. */
683 if (reason & (REASON_ILLEGAL | REASON_PRIVILEGED)) {
684 switch (emulate_instruction(regs)) {
685 case 0:
686 regs->nip += 4;
687 emulate_single_step(regs);
688 return;
689 case -EFAULT:
690 _exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip);
691 return;
692 }
693 }
694
695 if (reason & REASON_PRIVILEGED)
696 _exception(SIGILL, regs, ILL_PRVOPC, regs->nip);
697 else
698 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
699}
700
dc1c1ca3 701void single_step_exception(struct pt_regs *regs)
1da177e4
LT		 702{
703 regs->msr &= ~(MSR_SE | MSR_BE); /* Turn off 'trace' bits */
704 if (debugger_sstep(regs))
705 return;
706 _exception(SIGTRAP, regs, TRAP_TRACE, 0);
707}
708
dc1c1ca3 709void alignment_exception(struct pt_regs *regs)
1da177e4 710{
4393c4f6 711 int sig, code, fixed = 0;
1da177e4
LT		 712
713 fixed = fix_alignment(regs);
714 if (fixed == 1) {
715 regs->nip += 4; /* skip over emulated instruction */
6c26e03b 716 emulate_single_step(regs);
1da177e4
LT		 717 return;
718 }
719 if (fixed == -EFAULT) {
4393c4f6
BH		 720 sig = SIGSEGV;
721 code = SEGV_ACCERR;
722 } else {
723 sig = SIGBUS;
724 code = BUS_ADRALN;
1da177e4 725 }
4393c4f6
BH		 726 if (user_mode(regs))
727 _exception(sig, regs, code, regs->dar);
728 else
729 bad_page_fault(regs, regs->dar, sig);
1da177e4
LT		 730}
731
732void StackOverflow(struct pt_regs *regs)
733{
734 printk(KERN_CRIT "Kernel stack overflow in process %p, r1=%lx\n",
735 current, regs->gpr[1]);
736 debugger(regs);
737 show_regs(regs);
738 panic("kernel stack overflow");
739}
740
741void nonrecoverable_exception(struct pt_regs *regs)
742{
743 printk(KERN_ERR "Non-recoverable exception at PC=%lx MSR=%lx\n",
744 regs->nip, regs->msr);
745 debugger(regs);
746 die("nonrecoverable exception", regs, SIGKILL);
747}
748
749void trace_syscall(struct pt_regs *regs)
750{
751 printk("Task: %p(%d), PC: %08lX/%08lX, Syscall: %3ld, Result: %s%ld %s\n",
752 current, current->pid, regs->nip, regs->link, regs->gpr[0],
753 regs->ccr&0x10000000?"Error=":"", regs->gpr[3], print_tainted());
754}
755
756#ifdef CONFIG_8xx
757void SoftwareEmulation(struct pt_regs *regs)
758{
759 extern int do_mathemu(struct pt_regs *);
760 extern int Soft_emulate_8xx(struct pt_regs *);
761 int errcode;
762
763 CHECK_FULL_REGS(regs);
764
765 if (!user_mode(regs)) {
766 debugger(regs);
767 die("Kernel Mode Software FPU Emulation", regs, SIGFPE);
768 }
769
770#ifdef CONFIG_MATH_EMULATION
771 errcode = do_mathemu(regs);
772#else
773 errcode = Soft_emulate_8xx(regs);
774#endif
775 if (errcode) {
776 if (errcode > 0)
777 _exception(SIGFPE, regs, 0, 0);
778 else if (errcode == -EFAULT)
779 _exception(SIGSEGV, regs, 0, 0);
780 else
781 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
782 } else
783 emulate_single_step(regs);
784}
785#endif /* CONFIG_8xx */
786
787#if defined(CONFIG_40x) || defined(CONFIG_BOOKE)
788
789void DebugException(struct pt_regs *regs, unsigned long debug_status)
790{
791 if (debug_status & DBSR_IC) { /* instruction completion */
792 regs->msr &= ~MSR_DE;
793 if (user_mode(regs)) {
794 current->thread.dbcr0 &= ~DBCR0_IC;
795 } else {
796 /* Disable instruction completion */
797 mtspr(SPRN_DBCR0, mfspr(SPRN_DBCR0) & ~DBCR0_IC);
798 /* Clear the instruction completion event */
799 mtspr(SPRN_DBSR, DBSR_IC);
800 if (debugger_sstep(regs))
801 return;
802 }
803 _exception(SIGTRAP, regs, TRAP_TRACE, 0);
804 }
805}
806#endif /* CONFIG_4xx || CONFIG_BOOKE */
807
808#if !defined(CONFIG_TAU_INT)
809void TAUException(struct pt_regs *regs)
810{
811 printk("TAU trap at PC: %lx, MSR: %lx, vector=%lx %s\n",
812 regs->nip, regs->msr, regs->trap, print_tainted());
813}
814#endif /* CONFIG_INT_TAU */
815
fd582ec8
PM		 816/*
817 * FP unavailable trap from kernel - print a message, but let
818 * the task use FP in the kernel until it returns to user mode.
819 */
820void kernel_fp_unavailable_exception(struct pt_regs *regs)
821{
822 regs->msr |= MSR_FP;
823 printk(KERN_ERR "floating point used in kernel (task=%p, pc=%lx)\n",
824 current, regs->nip);
825}
826
dc1c1ca3 827void altivec_unavailable_exception(struct pt_regs *regs)
1da177e4
LT		 828{
829 static int kernel_altivec_count;
830
831#ifndef CONFIG_ALTIVEC
832 if (user_mode(regs)) {
833 /* A user program has executed an altivec instruction,
834 but this kernel doesn't support altivec. */
835 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
836 return;
837 }
838#endif
839 /* The kernel has executed an altivec instruction without
840 first enabling altivec. Whinge but let it do it. */
841 if (++kernel_altivec_count < 10)
842 printk(KERN_ERR "AltiVec used in kernel (task=%p, pc=%lx)\n",
843 current, regs->nip);
844 regs->msr |= MSR_VEC;
845}
846
847#ifdef CONFIG_ALTIVEC
dc1c1ca3 848void altivec_assist_exception(struct pt_regs *regs)
1da177e4
LT		 849{
850 int err;
851
852 preempt_disable();
853 if (regs->msr & MSR_VEC)
854 giveup_altivec(current);
855 preempt_enable();
e378cc16
PM		 856 if (!user_mode(regs)) {
857 printk(KERN_ERR "altivec assist exception in kernel mode"
858 " at %lx\n", regs->nip);
859 debugger(regs);
860 die("altivec assist exception", regs, SIGFPE);
861 return;
862 }
1da177e4
LT		 863
864 err = emulate_altivec(regs);
865 if (err == 0) {
866 regs->nip += 4; /* skip emulated instruction */
867 emulate_single_step(regs);
868 return;
869 }
870
871 if (err == -EFAULT) {
872 /* got an error reading the instruction */
873 _exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip);
874 } else {
875 /* didn't recognize the instruction */
876 /* XXX quick hack for now: set the non-Java bit in the VSCR */
877 printk(KERN_ERR "unrecognized altivec instruction "
878 "in %s at %lx\n", current->comm, regs->nip);
879 current->thread.vscr.u[3] |= 0x10000;
880 }
881}
882#endif /* CONFIG_ALTIVEC */
883
83f7da8a 884#ifdef CONFIG_E500
dc1c1ca3 885void performance_monitor_exception(struct pt_regs *regs)
1da177e4
LT		 886{
887 perf_irq(regs);
888}
83f7da8a 889#endif
1da177e4
LT		 890
891#ifdef CONFIG_FSL_BOOKE
892void CacheLockingException(struct pt_regs *regs, unsigned long address,
893 unsigned long error_code)
894{
895 /* We treat cache locking instructions from the user
896 * as priv ops, in the future we could try to do
897 * something smarter
898 */
899 if (error_code & (ESR_DLK|ESR_ILK))
900 _exception(SIGILL, regs, ILL_PRVOPC, regs->nip);
901 return;
902}
903#endif /* CONFIG_FSL_BOOKE */
904
905#ifdef CONFIG_SPE
906void SPEFloatingPointException(struct pt_regs *regs)
907{
908 unsigned long spefscr;
909 int fpexc_mode;
910 int code = 0;
911
912 spefscr = current->thread.spefscr;
913 fpexc_mode = current->thread.fpexc_mode;
914
915 /* Hardware does not neccessarily set sticky
916 * underflow/overflow/invalid flags */
917 if ((spefscr & SPEFSCR_FOVF) && (fpexc_mode & PR_FP_EXC_OVF)) {
918 code = FPE_FLTOVF;
919 spefscr |= SPEFSCR_FOVFS;
920 }
921 else if ((spefscr & SPEFSCR_FUNF) && (fpexc_mode & PR_FP_EXC_UND)) {
922 code = FPE_FLTUND;
923 spefscr |= SPEFSCR_FUNFS;
924 }
925 else if ((spefscr & SPEFSCR_FDBZ) && (fpexc_mode & PR_FP_EXC_DIV))
926 code = FPE_FLTDIV;
927 else if ((spefscr & SPEFSCR_FINV) && (fpexc_mode & PR_FP_EXC_INV)) {
928 code = FPE_FLTINV;
929 spefscr |= SPEFSCR_FINVS;
930 }
931 else if ((spefscr & (SPEFSCR_FG | SPEFSCR_FX)) && (fpexc_mode & PR_FP_EXC_RES))
932 code = FPE_FLTRES;
933
934 current->thread.spefscr = spefscr;
935
936 _exception(SIGFPE, regs, code, regs->nip);
937 return;
938}
939#endif
940
a2f40ccd
KG		 941#ifdef CONFIG_BOOKE_WDT
942/*
943 * Default handler for a Watchdog exception,
944 * spins until a reboot occurs
945 */
946void __attribute__ ((weak)) WatchdogHandler(struct pt_regs *regs)
947{
948 /* Generic WatchdogHandler, implement your own */
949 mtspr(SPRN_TCR, mfspr(SPRN_TCR)&(~TCR_WIE));
950 return;
951}
952
953void WatchdogException(struct pt_regs *regs)
954{
955 printk (KERN_EMERG "PowerPC Book-E Watchdog Exception\n");
956 WatchdogHandler(regs);
957}
958#endif
959
1da177e4
LT		 960void __init trap_init(void)
961{
962}
Linux 6.x block layer and io_uring tree(s)